High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Synchronous CF and F1/F2 outputs
Logic output REVP provides information regarding the sign
of the active power
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Programmable gain amplifier (PGA) in the current channel
facilitates usage of small shunts and burden resistors
Proprietary ADCs and DSPs provide high accuracy over large
variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with
external overdrive capability
Single 5 V supply, low power (15 mW typical)
Low cost CMOS process
ADE7755
GENERAL DESCRIPTION
The ADE7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements as
quoted in the IEC 1036 standard.
The only analog circuitry used in the ADE7755 is in the ADCs
and reference circuit. All other signal processing (for example,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7755 supplies average active power information on the
low frequency outputs, F1 and F2. These logic outputs can be
used to directly drive an electromechanical counter or interface to
an MCU. The CF logic output gives instantaneous active power
information. This output is intended to be used for calibration
purposes or for interfacing to an MCU.
The ADE7755 includes a power supply monitoring circuit on the
AV
supply pin. The ADE7755 remains in a reset condition until
DD
the supply voltage on AV
4 V, the ADE7755 resets and no pulse is issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Channel 1
is on or off. An internal no load threshold ensures that the
ADE7755 does not exhibit any creep when there is no load.
The ADE7755 is available in a 24-lead SSOP package.
reaches 4 V. If the supply falls below
DD
FUNCTIONAL BLOCK DIAGRAM
G0 G1
5
V1P
6
V1N
V2P
V2N
8
7
REFERENCE
×1, ×2, ×8, ×16
2.5V
1
U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY
1, 2
Measurement Error1 on Channel 1 Channel 2 with full-scale signal (±660 mV), 25°C
Gain = 1 0.1 % reading Over a dynamic range of 500 to 1
Gain = 2 0.1 % reading Over a dynamic range of 500 to 1
Gain = 8 0.1 % reading Over a dynamic range of 500 to 1
Gain = 16 0.1 % reading Over a dynamic range of 500 to 1
Phase Error1 Between Channels Line frequency = 45 Hz to 65 Hz
V1 Phase Lead 37° (PF = 0.8 Capacitive) ±0.1 Degrees
V1 Phase Lag 60° (PF = 0.5 Inductive) ±0.1 Degrees
t2 See Tabl e 7 sec Output pulse period; see the Transfer Function section
t3 1/2 t2 sec Time between F1 falling edge and F2 falling edge
3, 4
t
90 ms CF pulse width (logic high)
4
t5 See Tabl e 8 sec CF pulse period; see the Transfer Function section
t6 CLKIN/4 sec Minimum time between F1 and F2 pulse
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 2.
3
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
4
The CF pulse is always 18 μs in the high frequency mode. See the Frequency Outputs section and Table 8.
t
1
F1
t
6
t
2
F2
CF
t
3
t
4
t
5
2896-002
Figure 2. Timing Diagram for Frequency Outputs
Rev. A | Page 4 of 20
ADE7755
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
DV
to AVDD −0.3 V to +0.3 V
DD
Analog Input Voltage to AGND
V1P, V1N, V2P, and V2N −6 V to +6 V
Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
24-Lead SSOP, Power Dissipation 450 mW
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 20
ADE7755
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 DVDD
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7755. The supply
voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor.
2
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (current channel). A Logic 1 on
AC/DC
this pin enables the HPF. The associated phase response of this filter is internally compensated over a
frequency range of 45 Hz to 1 kHz. The HPF should be enabled in power metering applications.
3 AVDD
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7755. The supply
should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power
supply ripple and noise at this pin by the use of proper decoupling. This pin should be decoupled to AGND
with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
4, 19 NC No Connect.
5, 6 V1P, V1N
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with a
maximum differential signal level of ±470 mV for specified operation. Channel 1 also has a PGA, and the gain
selections are outlined in Tab le 5. The maximum signal level at these pins is ±1 V with respect to AGND. Both
inputs have internal ESD protection circuitry. An overvoltage of ±6 V can be sustained on these inputs without
risk of permanent damage.
7, 8 V2N, V2P
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential input pair
with a maximum differential input voltage of ±660 mV for specified operation. The maximum signal level at
these pins is ±1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage
of ±6 V can be sustained on these inputs without risk of permanent damage.
9
Reset Pin. A logic low on this pin holds the ADCs and digital circuitry in a reset condition.
RESET
Bringing this pin logic low clears the ADE7755 internal registers.
10 REF
IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor and
a 100 nF ceramic capacitor.
11 AGND
This pin provides the ground reference for the analog circuitry in the ADE7755, that is, the ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference
for all analog circuitry, for example, antialiasing filters and current and voltage transducers. For good noise
suppression, the analog ground plane should be connected to the digital ground plane at one point only. A
star ground configuration helps to keep noisy digital currents away from the analog circuits.
12 SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output, CF.
Tab le 8 shows how the calibration frequencies are selected.
13, 14 S1, S0
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for
an Energy Meter Application section.
15, 16 G1, G0
These logic inputs are used to select one of four possible gains for Channel 1, that is, V1. The possible gains
are 1, 2, 8, and 16. See the Analog Inputs section.
DV
DD
AC/DC
2
3
AV
DD
NC
4
V1P
5
V1N
6
V2N
7
8
V2P
RESET
9
IN/OUT
AGND
SCF
10
11
12
NC = NO CONNECT
REF
Figure 3. Pin Configuration
ADE7755
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
F1
F2
CF
DGND
REVP
NC
CLKOUT
CLKIN
G0
G1
S0
S1
02896-003
Rev. A | Page 6 of 20
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