ANALOG DEVICES ADE7755 Service Manual

Energy Metering IC with Pulse Output

FEATURES

High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and

supplies instantaneous active power
Synchronous CF and F1/F2 outputs
Logic output REVP provides information regarding the sign

of the active power
Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)
Programmable gain amplifier (PGA) in the current channel

facilitates usage of small shunts and burden resistors
Proprietary ADCs and DSPs provide high accuracy over large

variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with

external overdrive capability
Single 5 V supply, low power (15 mW typical)
Low cost CMOS process

ADE7755

GENERAL DESCRIPTION

The ADE7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements as
quoted in the IEC 1036 standard.

The only analog circuitry used in the ADE7755 is in the ADCs
and reference circuit. All other signal processing (for example,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
extremes in environmental conditions and over time.

The ADE7755 supplies average active power information on the
low frequency outputs, F1 and F2. These logic outputs can be
used to directly drive an electromechanical counter or interface to
an MCU. The CF logic output gives instantaneous active power
information. This output is intended to be used for calibration
purposes or for interfacing to an MCU.

The ADE7755 includes a power supply monitoring circuit on the
AV

supply pin. The ADE7755 remains in a reset condition until

DD

the supply voltage on AV
4 V, the ADE7755 resets and no pulse is issued on F1, F2, and CF.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Channel 1
is on or off. An internal no load threshold ensures that the
ADE7755 does not exhibit any creep when there is no load.

The ADE7755 is available in a 24-lead SSOP package.

reaches 4 V. If the supply falls below

DD

FUNCTIONAL BLOCK DIAGRAM

G0 G1

5

V1P

6

V1N

V2P

V2N

8

7

REFERENCE

×1, ×2, ×8, ×16

2.5V

1

U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

AV

POWER

SUPPLY MONITOR

PGA

ADC

ADC

4kΩ

IN/OUT

DD

AGND

...110101. ..

...11011001. ..

ADE7755

CORRECTION

PHASE

MULTIPLIER

Figure 1.

DV

DCAC/

HPF

DIGITAL -TO-FREQUENCY

CONVERTER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2009 Analog Devices, Inc. All rights reserved.

DGND

DD

PROCESSING

LPF

21121131516

SIGNAL

BLOCK

242220131412181710

9

RESET

23

F2F1CFREVPS1S0SCFCLKOUTCLKINREF

02896-001

ADE7755

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Power Factor Considerations .................................................... 12

Nonsinusoidal Voltage and Current ........................................ 13

Analog Inputs ............................................................................. 13

Typical Connection Diagrams .................................................. 14

Power Supply Monitor ............................................................... 14

Digital-to-Frequency Conversion ............................................ 15

Interfacing the ADE7755 to a Microcontroller for Energy

Measurement ............................................................................... 16

Power Measurement Considerations ....................................... 16

Transfer Function ....................................................................... 17

Selecting a Frequency for an Energy Meter Application ...... 18

Frequency Outputs ..................................................................... 18

No Load Threshold .................................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20



REVISION HISTORY

8/09—Rev. 0 to Rev. A

Changes to Format ............................................................. Universal

Changes to Features Section and General Description Section . 1

Moved Figure 2 ................................................................................. 4

Changes to Pin 22, Pin 23, and Pin 24 Descriptions, Table 4 ..... 7

Changes to Terminology Section.................................................. 11

Changes to Theory of Operation Section, Figure 22, Power

Factor Considerations Section, and Figure 23 ............................ 12

Changes to Nonsinusoidal Voltage and Current Section and

Analog Inputs Section .................................................................... 13

Changes to Figure 27 ...................................................................... 14

Changes to HPF and Offset Effects Section, Figure 29, and

Digital-to-Frequency Conversion Section .................................. 15

Changes to Figure 32 ...................................................................... 16

Changes to Transfer Function Section ......................................... 17

Changes to Selecting a Frequency for an Energy Meter

Application Section ........................................................................ 18

Changes to No Load Threshold Section ...................................... 19

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

5/02—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADE7755

SPECIFICATIONS

AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

ACCURACY

1, 2

Measurement Error1 on Channel 1 Channel 2 with full-scale signal (±660 mV), 25°C

Gain = 1 0.1 % reading Over a dynamic range of 500 to 1
Gain = 2 0.1 % reading Over a dynamic range of 500 to 1
Gain = 8 0.1 % reading Over a dynamic range of 500 to 1
Gain = 16 0.1 % reading Over a dynamic range of 500 to 1

Phase Error1 Between Channels Line frequency = 45 Hz to 65 Hz

V1 Phase Lead 37° (PF = 0.8 Capacitive) ±0.1 Degrees
V1 Phase Lag 60° (PF = 0.5 Inductive) ±0.1 Degrees

AC Power Supply Rejection

1

Output Frequency Variation (CF) 0.2 % reading

AC/DC
AC/DC
AC/DC
V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz,

ripple on AV

DC Power Supply Rejection

Output Frequency Variation (CF) ±0.3 % reading

1

AC/DC
V1 = 100 mV rms, V2 = 100 mV rms,

AVDD = DVDD = 5 V ± 250 mV

ANALOG INPUTS See the Analog Inputs section

Maximum Signal Levels ±1 V V1P, V1N, V2N, and V2P to AGND
Input Impedance (DC) 390 kΩ CLKIN = 3.58 MHz

−3 dB Bandwidth 14 kHz CLKIN/256, CLKIN = 3.58 MHz
ADC Offset Error
Gain Error

1, 2

1

±25 mV Gain = 1

±7 % ideal External 2.5 V reference, gain = 1

V1 = 470 mV dc, V2 = 660 mV dc
Gain Error Match

1

±0.2 % ideal External 2.5 V reference

REFERENCE INPUT

REF

Input Voltage Range 2.7 V 2.5 V + 8%

IN/OUT

2.3 V 2.5 V − 8%
Input Impedance 3.2 kΩ
Input Capacitance 10 pF

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±200 mV
Temperature Coefficient ±30 ppm/°C

CLKIN Note all specifications for CLKIN of 3.58 MHz

Input Clock Frequency 4 MHz
1 MHz
LOGIC INPUTS3

SCF, S0, S1, AC/DC, RESET, G0, and G1

Input High Voltage, V
Input Low Voltage, V

2.4 V DVDD = 5 V ± 5%

INH

0.8 V DVDD = 5 V ± 5%

INL

Input Current, IIN ±3 μA Typically 10 nA, VIN = 0 V to DVDD
Input Capacitance, CIN 10 pF

LOGIC OUTPUTS3

F1 and F2

Output High Voltage, VOH 4.5 V I
Output Low Voltage, VOL 0.5 V I

SOURCE

SINK

CF and REVP

Output High Voltage, VOH 4 V I
Output Low Voltage, VOL 0.5 V I

SOURCE

SINK

to T

MIN

= −40°C to +85°C.

MAX

= 0 and AC/DC = 1
= 0 and AC/DC = 1
= 1, S0 = S1 = 1, G0 = G1 = 0

of 200 mV rms @ 100 Hz

DD

= 1, S0 = S1 = 1, G0 = G1 = 0

1, 2

= 10 mA, DVDD = 5 V

= 10 mA, DVDD = 5 V

= 5 mA, DVDD = 5 V

= 5 mA, DVDD = 5 V

Rev. A | Page 3 of 20

ADE7755

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY For specified performance

AVDD 4.75 V 5 V − 5%

5.25 V 5 V + 5%
DVDD 4.75 V 5 V − 5%

5.25 V 5 V + 5%
AIDD 3 mA Typically 2 mA
DIDD 2.5 mA Typically 1.5 mA

1

See the Terminology section.

2

See the Typical Performance Characteristics section for the plots.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

TIMING CHARACTERISTICS

AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T

MIN

to T

= −40°C to +85°C.

MAX

Table 2.

Parameter

3

t

275 ms F1 and F2 pulse width (logic low)

1

1, 2

Specification Unit Test Conditions/Comments

t2 See Tabl e 7 sec Output pulse period; see the Transfer Function section
t3 1/2 t2 sec Time between F1 falling edge and F2 falling edge

3, 4

t

90 ms CF pulse width (logic high)

4

t5 See Tabl e 8 sec CF pulse period; see the Transfer Function section
t6 CLKIN/4 sec Minimum time between F1 and F2 pulse

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See Figure 2.

3

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

4

The CF pulse is always 18 μs in the high frequency mode. See the Frequency Outputs section and Table 8.

t

1

F1

t

6

t

2

F2

CF

t

3

t

4

t

5

2896-002

Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 4 of 20

ADE7755

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
DV

to AVDD −0.3 V to +0.3 V

DD

Analog Input Voltage to AGND

V1P, V1N, V2P, and V2N −6 V to +6 V
Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
24-Lead SSOP, Power Dissipation 450 mW

θJA Thermal Impedance 112°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 20

ADE7755

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 DVDD

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7755. The supply
voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor.

2

High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (current channel). A Logic 1 on

AC/DC

this pin enables the HPF. The associated phase response of this filter is internally compensated over a
frequency range of 45 Hz to 1 kHz. The HPF should be enabled in power metering applications.

3 AVDD

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7755. The supply
should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power
supply ripple and noise at this pin by the use of proper decoupling. This pin should be decoupled to AGND

with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
4, 19 NC No Connect.
5, 6 V1P, V1N

Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with a

maximum differential signal level of ±470 mV for specified operation. Channel 1 also has a PGA, and the gain

selections are outlined in Tab le 5. The maximum signal level at these pins is ±1 V with respect to AGND. Both

inputs have internal ESD protection circuitry. An overvoltage of ±6 V can be sustained on these inputs without

risk of permanent damage.
7, 8 V2N, V2P

Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential input pair

with a maximum differential input voltage of ±660 mV for specified operation. The maximum signal level at

these pins is ±1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage

of ±6 V can be sustained on these inputs without risk of permanent damage.
9

Reset Pin. A logic low on this pin holds the ADCs and digital circuitry in a reset condition.

RESET

Bringing this pin logic low clears the ADE7755 internal registers.
10 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also be

connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor and

a 100 nF ceramic capacitor.
11 AGND

This pin provides the ground reference for the analog circuitry in the ADE7755, that is, the ADCs and reference.

This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference

for all analog circuitry, for example, antialiasing filters and current and voltage transducers. For good noise

suppression, the analog ground plane should be connected to the digital ground plane at one point only. A

star ground configuration helps to keep noisy digital currents away from the analog circuits.
12 SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output, CF.

Tab le 8 shows how the calibration frequencies are selected.
13, 14 S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.

This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for

an Energy Meter Application section.
15, 16 G1, G0

These logic inputs are used to select one of four possible gains for Channel 1, that is, V1. The possible gains

are 1, 2, 8, and 16. See the Analog Inputs section.

DV

DD

AC/DC

2

3

AV

DD

NC

4

V1P

5

V1N

6

V2N

7

8

V2P

RESET

9

IN/OUT

AGND

SCF

10

11

12

NC = NO CONNECT

REF

Figure 3. Pin Configuration

ADE7755

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

F1

F2

CF

DGND

REVP

NC

CLKOUT

CLKIN

G0

G1

S0

S1

02896-003

Rev. A | Page 6 of 20

ADE7755

Pin No. Mnemonic Description

17 CLKIN

18 CLKOUT

20 REVP

21 DGND

22 CF

23, 24 F2, F1

An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across CLKIN and CLKOUT to provide a clock source for the ADE7755. The clock frequency for
specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and 33 pF (ceramic) should
be used with the gate oscillator circuit.

A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7755. The CLKOUT
pin can drive one CMOS load when an external clock is supplied at CLKIN or by the gate oscillator circuit.

This logic output goes logic high when negative power is detected, that is, when the phase angle between
the voltage and current signals is greater than 90°. This output is not latched and is reset when positive power
is detected again. The output goes high or low at the same time that a pulse is issued on CF.

This pin provides the ground reference for digital circuitry in the ADE7755, that is, the multiplier, filters, and
digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground
plane is the ground reference for all digital circuitry, for example, counters (mechanical and digital), MCUs, and
indicator LEDs. For good noise suppression, the analog ground plane should be connected to the digital ground
plane at one point only, for example, a star ground.

Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information.
This output is intended to be used for calibration purposes. Also, see the SCF pin description.

Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can
be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function
section.

Rev. A | Page 7 of 20

ADE7755

TYPICAL PERFORMANCE CHARACTERISTICS

0.5

0.4

0.3

0.2

0.1

0

ERROR (%)

–0.1

–0.2

–0.3

PF = 1
GAIN = 1

–0.4

ON-CHIP REFE RENCE

–0.5

0.5

0.4

0.3

0.2

0.1

0

ERROR (%)

–0.1

–0.2

–0.3

–0.4

–0.5

0.6

0.5

0.4

0.3
PF = 1

GAIN = 8

0.2
ON-CHIP REFE RENCE

0.1

ERROR (%)

0

–0.1

–0.2

–0.3

–0.4

–40°C

+25°C

+85°C

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 4. Error as a % of Reading (Gain = 1)

–40°C

+25°C

+85°C

PF = 1
GAIN = 2
ON-CHIP REFE RENCE

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 5. Error as a % of Reading (Gain = 2)

–40°C

+25°C

+85°C

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 6. Error as a % of Reading (Gain = 8)

100

02896-004

100

02896-005

100

02896-006

0.5

0.4

0.3

0.2
PF = 1

GAIN = 16

0.1

ON-CHIP REFERE NCE

0

ERROR (%)

–0.1

–0.2

–0.3

–0.4

–0.5

0.6

0.4

0.2

0

ERROR (%)

–0.2

–0.4

–0.6

0.6

0.4

0.2

0

ERROR (%)

–0.2

–0.4

–0.6

–40°C

+25°C

+85°C

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 7. Error as a % of Reading (Gain = 16)

PF = 0.5
GAIN = 1
ON-CHIP REFERENCE

–40°C PF = 0. 5

+25°C PF = 1

+25°C PF = 0.5

+85°C PF = 0. 5

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 8. Error as a % of Reading (Gain = 1)

PF = 0.5
GAIN = 2
ON-CHIP REFE RENCE

–40°C PF = 0. 5

+25°C PF = 1

+25°C PF = 0. 5

+85°C PF = 0. 5

0.10.01 1 10
FULL-SCAL E CURRENT (%)

Figure 9. Error as a % of Reading (Gain = 2)

100

02896-007

100

02896-008

100

02896-009

Rev. A | Page 8 of 20

ADE7755

V

0.8

0.6

0.4

–40°C PF = 0. 5

PF = 0.5
GAIN = 8
ON-CHIP REFERENCE

0.4

PF = 1
GAIN = 16

0.3
EXTERNAL REFERENCE

0.2

–40°C

0.2

+25°C PF = 1

+25°C PF = 0.5

ERROR (%)

–0.2

–0.4

0

+85°C PF = 0. 5

–0.6

–0.8

0.10.01 1 10

100

FULL-SCAL E CURRENT (%)

Figure 10. Error as a % of Reading (Gain = 8)

0.4

0.2

–40°C PF = 0. 5

0

+25°C PF = 1

–0.2

–0.4

ERROR (%)

–0.6

PF = 0.5

–0.8

GAIN = 16
ON-CHIP REFERENCE

–1.0

0.10.01 1 10

+25°C PF = 0.5

+85°C PF = 0. 5

100

FULL-SCAL E CURRENT (%)

Figure 11. Error as a % of Reading (Gain = 16)

0.4

PF = 1
GAIN = 2

0.3
EXTERNAL REF ERENCE

0.2

–40°C

0.1

+25°C

0

ERROR (%)

–0.1

+85°C

–0.2

–0.3

–0.4

0.10.01 1 10

100

FULL-SCAL E CURRENT (%)

Figure 12. Error as a % of Reading over Temperature with an External

Reference (Gain = 2)

0.1

+25°C

ERROR (%)

–0.1

–0.2

0

+85°C

–0.3

–0.4

02896-010

0.10.01 1 10
FULL-SCAL E CURRENT (%)

100

02896-013

Figure 13. Error as a % of Reading over Temperature with an External

Reference (Gain = 16)

0.8

0.6

PF = 1

0.4

0.2

ERROR (%)

PF = 0.5

0

–0.2

–0.4

–0.6

2896-011

5045 6055 7065

FREQUENCY (Hz)

75

02896-014

Figure 14. Error as a % of Reading over Frequency

DD

10µF 100n F

40A TO

40mA

1kΩ

500µΩ

1.5mΩ
10mΩ

220V

02896-012

NC = NO CONNECT

10µF

1MΩ

1kΩ

33nF

1kΩ

33nF

1kΩ

33nF

33nF

100nF

321

AV

AC/DC DV

DD

4

NC

5

V1P

ADE7755

6

V1N

7

V2N

8

V2P

10

REF

IN/OUT

RESET AGND DGND

9

V

DD

U1

CLKOUT

CLKIN

100nF 10µF

DD

24

F1

23

F2

22

CF

20

REVP

19

NC

18

17

16

G0

15

G1

14

S0

13

S1

12

SCF

2111

Y1

3.58MHz

GAIN
SELECT

1

2

33pF

33pF

U3

PS2501-1

K7

4

3

K8

V

DD

10kΩ

10nF10n F10nF

02896-015

Figure 15. Test Circuit for Performance Curves

Rev. A | Page 9 of 20

ADE7755

16

DISTRIBUTI ON CHARACTERIST ICS
NUMBER POINTS: 101
MINIMUM: –9.78871

14

MAXIMUM: 7.2939
MEAN: –1.73203

12

STD. DEV: 3.61157

10

GAIN = 1
TEMPERATURE = 25°C

30

DISTRIBUTI ON CHARACTERIST ICS
NUMBER POINTS: 101
MINIMUM: –2.48959

25

MAXIMUM: 5.81126
MEAN: –1.26847
STD. DEV: 1. 57404

20

GAIN = 8
TEMPERATURE = 25°C

8

HITS

6

4

2

0

–9 –3–15 3 9

CH1 OFFSET (mV)

Figure 16. Channel 1 Offset Distribution (Gain = 1)

18

DISTRIBUTI ON
CHARACTERISTICS

16

NUMBER POINTS: 101
MINIMUM: –5.61779

14

MAXIMUM: 6. 40821
MEAN: –0.01746
STD. DEV: 2.35129

12

10

HITS

8

6

4

2

0

–9 –3–15 3 9

CH1 OFFSET (mV)

GAIN = 2
TEMPERATURE = 25°C

Figure 17. Channel 1 Offset Distribution (Gain = 2)

0.5

ERROR (%)

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

0.4

0.3

0.2

0.1

0

0.10.01 1 10
FULL-SCAL E CURRENT (%)

5.25V

5V

4.75V

Figure 18. PSR with Internal Reference (Gain = 16)

15

15

100

15

HITS

10

5

0

02896-016

–9 –3–15 3 9

CH1 OFFSET (mV)

15

02896-019

Figure 19. Channel 1 Offset Distribution (Gain = 8)

35

DISTRIBUTI ON CHARACTERIST ICS
NUMBER POINTS: 101
MINIMUM: –1.96823

30

MAXIMUM: 5.71177
MEAN: –1.48279
STD. DEV: 1. 47802

25

20

HITS

15

10

5

02896-017

0

–9 –3–15 3 9

CH1 OFFSET (mV)

GAIN = 16
TEMPERATURE = 25°C

15

02896-020

Figure 20. Channel 1 Offset Distribution (Gain = 16)

0.5

0.4

0.3

0.2

0.1

0

–0.1

ERROR (%)

–0.2

–0.3

–0.4

–0.5

–0.6

02896-018

0.10.01 1 10
FULL-SCAL E CURRENT (%)

5.25V

5V

4.75V

100

02896-021

Figure 21. PSR with External Reference (Gain = 16)

Rev. A | Page 10 of 20

ADE7755

r

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7755 is defined by the following formula:

=

Percentage

Phase Error Between Channels

The high-pass filter (HPF) in Channel 1 has a phase lead response.
To offset this phase response and equalize the phase response
between channels, a phase compensation network is also placed
in Channel 1. The phase compensation network matches the
phase to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range of 40 Hz to 1 kHz. See Figure 30 and Figure 31.

Power Supply Rejection (PSR)

The PSR quantifies the ADE7755 measurement error as a
percentage of the reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of the reading (see the Measurement Error definition).

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.

Erro

7755×−

EnergyTrue

EnergyTrueADEthebyRegisteredEnergy

%100

ADC Offset Error

The ADC offset error refers to the dc offset associated with the
analog inputs to the ADCs. It means that with the analog inputs
connected to AGND, the ADCs still see a small dc signal
(offset). The offset decreases with increasing gain in Channel 1.
This specification is measured at a gain of 1. At a gain of 16, the
dc offset is typically less than 1 mV. However, when the HPF is
switched on, the offset is removed from the current channel,
and the power calculation is not affected by this offset.

Gain Error

The gain error of the ADE7755 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel 1.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7755 transfer
function (see the

Gain Error Match

The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output frequency
obtained under a gain of 1. This gives the gain error observed
when the gain selection is changed from 1 to 2, 8, or 16.

Transfer Func tion section).

Rev. A | Page 11 of 20

ADE7755

V

V

A

THEORY OF OPERATION

The two ADCs of the ADE7755 digitize the voltage signals from
the current and voltage transducers. These ADCs are 16-bit,
second-order Σ-Δ with an oversampling rate of 900 kHz. This
analog input structure greatly simplifies transducer interfacing
by providing a wide dynamic range for direct connection to the
transducer and also by simplifying the antialiasing filter design.
A programmable gain stage in the current channel further
facilitates easy transducer interfacing. A high-pass filter in the
current channel removes any dc components from the current
signal. This removal eliminates any inaccuracies in the active
power calculation due to offsets in the voltage or current signals
(see the HPF and Offset Effects section).

The active power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. To
extract the active power component (that is, the dc component),
the instantaneous power signal is low-pass filtered. Figure 22
illustrates the instantaneous active power signal and shows how
the active power information can be extracted by low-pass filtering
the instantaneous power signal. This scheme correctly calculates
active power for nonsinusoidal current and voltage waveforms
at all power factors. All signal processing is carried out in the
digital domain for superior stability over temperature and time.

DIGITAL-TO-

CH1

CH2

ADCPGA

MULTIPLIER

ADC

HPF

LPF

FREQUENCY

DIGITAL-TO-

FREQUENCY

F1

F2

CF

POWER FACTOR CONSIDERATIONS

The method used to extract the active power information from
the instantaneous power signal (that is, by low-pass filtering) is
valid even when the voltage and current signals are not in phase.
Figure 23 displays the unity power factor condition and a
displacement power factor (DPF) = 0.5, that is, current signal
lagging the voltage by 60°. Assuming that the voltage and current
waveforms are sinusoidal, the active power component of the
instantaneous power signal (that is, the dc term) is given by

×

IV

⎛

⎞

()

60cos

⎜

⎟

2

⎝

⎠

This is the correct active power calculation.

V× I

2

0V

V× I

cos(60°)

2

0V

°×

INSTANTANEOUS

POWER SIGNAL

CURRENT

VOLTAGE

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS ACTIVE

POWER SIGNAL

CTIVE

INSTANTANEOUS ACTIV E

POWER SIGNAL

V × I

2

× I

× I
2

INSTANTANEOUS

POWER SIGNAL {p(t)}

p(t) = i(t) × v(t)
WHERE:
v(t) = V × cos(ωt)
i(t) = I × cos(ωt)

V × I

p(t) =

TIME

Figure 22. Signal Processing Block Diagram

{1+cos (2ωt)}

2

The low frequency output of the ADE7755 is generated by
accumulating this active power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is therefore proportional to the
average active power. This average active power information
can, in turn, be accumulated (for example, by a counter) to
generate active energy information. Because of its high output
frequency and shorter integration time, the calibration frequency
(CF) output is proportional to the instantaneous active power.
This is useful for system calibration purposes that take place
under steady load conditions.

Rev. A | Page 12 of 20

VOLTAGE CURRENT

Figure 23. DC Component of Instantaneous Power Signal Conveys

Active Power Information PF < 1

60°

2896-023

2896-022

ADE7755

V

–

V

V

NONSINUSOIDAL VOLTAGE AND CURRENT

The active power calculation method also holds true for non­sinusoidal current and voltage waveforms. All voltage and current
waveforms in practical applications have some harmonic content.
Using the Fourier Transform operation, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content.

∞

O

∑

0

h

≠

where:

v(t) is the instantaneous voltage.
V

is the average voltage value.

O

V

is the rms value of the voltage harmonic, h.

h

a

is the phase angle of the voltage harmonic.

h

∞

O

∑

0

h

≠

where:
i(t) is the instantaneous current.

is the current dc component.

I

O

is the rms value of the current harmonic, h.

I

h

β

is the phase angle of the current harmonic.

h

Using Equation 1 and Equation 2, the active power (P) can be
expressed in terms of its fundamental active power (P1) and
harmonic active power (P

P = P

+ PH (3)

1

where:

is the active power of the fundamental component:

P

1

= V1 × I1 cosΦ1

P

1

Φ

= α1 – β1

1

and

P

is the active power of all harmonic components:

H

H

= αh – βh

Φ

h

∑

h

∞

1

≠

Φ×=

cos

IVP

).

H

hhh

(

)

+××+=

tsin2)(

ahωVVtv

(1)

hh

+××+=

)tsin(2)(

βhωIIti (2)

hh

A harmonic active power component is generated for every
harmonic, provided that the harmonic is present in both the
voltage and current waveforms. The power factor calculation
previously shown is accurate in the case of a pure sinusoid;
therefore, the harmonic active power must also correctly
account for the power factor because it is made up of a series of
pure sinusoids.

Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.

ANALOG INPUTS

Channel 1 (Current Channel)

The voltage output from the current transducer is connected
to the ADE7755 at Channel 1. Channel 1 is a fully differential
voltage input. V1P is the positive input with respect to V1N.

The maximum peak differential signal on Channel 1 should be
less than ±470 mV (330 mV rms for a pure sinusoidal signal)
for specified operation. Note that Channel 1 has a programmable
gain amplifier (PGA) with user-selectable gain of 1, 2, 8, or 16
(see Table 5). These gains facilitate easy transducer interfacing.

1

+470m

DIFFERENTIAL INPUT

V

CM

470m

Figure 24. Maximum Signal Levels, Channel 1, Gain = 1

±470mV MAX PEAK

COMMON-MODE

±100mV MAX

Figure 24 illustrates the maximum signal levels on V1P and
V1N. The maximum differential voltage is ±470 mV divided by
the gain selection. The differential voltage signal on the inputs
must be referenced to a common mode, for example, AGND.
The maximum common-mode signal is ±100 mV, as shown in
Figure 24.

Table 5. Gain Selection for Channel 1

G1 G0 Gain Maximum Differential Signal (mV)

0 0 1 ±470
0 1 2 ±235
1 0 8

±60

1 1 16 ±30

AGND

V1P

V1

V1N

V

CM

02896-024

Rev. A | Page 13 of 20

ADE7755

V

–

V

V

L

Channel 2 (Voltage Channel)

The output of the line voltage transducer is connected to the
ADE7755 at this analog input. Channel 2 is a fully differential
voltage input. The maximum peak differential signal on Channel 2
is ±660 mV. Figure 25 illustrates the maximum signal levels that
can be connected to Channel 2 of the ADE7755.

2

+660m

660m

DIFFERENTIAL INPUT

V

CM

±660mV MAX PEAK

COMMON-MODE

±100mV MAX

AGND

V2P

V2

V2N

V

CM

02896-025

Figure 25. Maximum Signal Levels, Channel 2

Channel 2 must be driven from a common-mode voltage, that
is, the differential voltage signal on the input must be referenced
to a common mode (usually AGND). The analog inputs of the
ADE7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are achieved
using a common mode equal to AGND.

TYPICAL CONNECTION DIAGRAMS

Figure 26 shows a typical connection diagram for Channel 1. A
current transformer (CT) is the current transducer selected for
this example. Note that the common-mode voltage for Channel 1
is AGND and is derived by center-tapping the burden resistor to
AGND. This provides the complementary analog input signals for
V1P and V1N. The CT turns ratio and burden resistor Rb are
selected to give a peak differential voltage of ±470 mV/gain at
maximum load.

CT

IP

AGND

NEUTRALPHASE

Rf

Rb

±470mV

GAIN

Rf

Figure 26. Typical Connection for Channel 1

Figure 27 shows two typical connections for Channel 2. The first
option uses a potential transformer (PT) to provide complete
isolation from the power line. In the second option, the ADE7755
is biased around the neutral wire, and a resistor divider provides
a voltage signal that is proportional to the line voltage. Adjusting
the ratio of Ra, Rb, and VR is also a convenient way of carrying
out a gain calibration on the meter.

V1P

Cf

V1N

Cf

PT

±660mV

AGND

NEUTRALPHASE

Cf

1

Ra

1

Rb

±660mV

1

VR

1

NEUTRALPHASE

Ra >> Rb + VR
Rb + VR = Rf

Rf

Rf

Rf

Figure 27. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The ADE7755 contains an on-chip power supply monitor. The
analog supply (AV
If the supply is less than 4 V ± 5%, the ADE7755 resets. This is
useful to ensure correct device startup at power-up and power­down. The power supply monitor has built-in hysteresis and
filtering. These features give a high degree of immunity to false
triggering due to noisy supplies.

In Figure 28, the trigger level is nominally set at 4 V. The
tolerance on this trigger level is about ±5%. The power supply
and decoupling for the part should be such that the ripple at

does not exceed 5 V ± 5%, as specified for normal

AV

DD

operation.

AV

DD

5V
4V

0V

2896-026

INTERNA

RESET

) is continuously monitored by the ADE7755.

DD

TIME

RESET ACTIVE RESET

Figure 28. On-Chip Power Supply Monitor

V2P

Cf

V2N

Cf

V2P

V2N

Cf

02896-027

2896-028

Rev. A | Page 14 of 20

ADE7755

V

HPF and Offset Effects

Figure 29 shows the effect of offsets on the active power calculation.
An offset on Channel 1 and Channel 2 contributes a dc component
after multiplication. Because the dc component is extracted by
the LPF, it accumulates as active power. If not properly filtered, dc
offsets introduce error to the energy accumulation. This problem is

DC

easily avoided by enabling the HPF (that is, the AC/

pin is
set to logic high) in Channel 1. By removing the offset from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at cos(ωt) are removed by the
LPF and the digital-to-frequency conversion (see the
Frequency Conversion

{V cos(ωt) + V

IV

×

2

IV

×

2

× I

OS

OS

V × I

2

0 ω 2ω

Figure 29. Effect of Channel Offset on the Active Power Calculation

section).

} × {I cos(ωt) + IOS} =

OS

OSOSOSOS

t

)2cos(

ω×

DC COMPONENT (INCLUDING ERRO R TERM)
IS EXTRACTE D BY THE LPF FOR ACTIVE
POWER CALCULATION

IOS × V

V

× I

OS

FREQUENCY ( RAD/s)

Digital-to-

)cos()cos(

tVItIVIV

+ω×+ω×+×+

02896-029

The HPF in Channel 1 has an associated phase response that is
compensated for on chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figure 30 and Figure 31 show the phase error between
channels with the compensation network activated. The ADE7755
is phase compensated up to 1 kHz, as shown. This ensures correct
active harmonic power calculation even at low power factors.

0.30

0.25

0.20

0.15

0.30

0.25

0.20

0.15

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

40 45 50 55 60 65 70

Figure 31. Phase Error Between Channels (40 Hz to 70 Hz)

FREQUENCY (Hz)

2896-031

DIGITAL-TO-FREQUENCY CONVERSION

The digital output of the low-pass filter after multiplication
contains the active power information. However, because this
LPF is not an ideal brick-wall filter implementation, the output
signal also contains attenuated components at the line frequency
and its harmonics, that is, cos(hωt) where h = 1, 2, 3, and so on.

The magnitude response of the filter is given by

)(ffH+= (4)

For a line frequency of 50 Hz, the filter gives an attenuation
of the 2ω (100 Hz) component of approximately −22 dB. The
dominating harmonic is at twice the line frequency, that is,
cos(2 ωt), which is due to the instantaneous power signal.

Figure 32 shows the instantaneous active power signal at the
output of the LPF, which still contains a significant amount of
instantaneous power information, that is, cos(2 ωt). This signal
is then passed to the digital-to-frequency converter where it is
integrated (accumulated) over time to produce an output frequency.
This accumulation of the signal suppresses or averages out any
non-dc components in the instantaneous active power signal. The
average value of a sinusoidal signal is 0. Therefore, the frequency
generated by the ADE7755 is proportional to the average active
power. Figure 32 shows the digital-to-frequency conversion for
steady load conditions, that is, constant voltage and current.

1

)Hz8.9/(1

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

0 100 200 300 400 500 600 700 800 900 1000

Figure 30. Phase Error Between Channels (0 Hz to 1 kHz)

FREQUENCY (Hz)

2896-030

Rev. A | Page 15 of 20

ADE7755

r

V

MULTIPLIER

I

V×I

2

0

INSTANTANEOUS ACTIVE POWER SIGNAL

(FREQUENCY DOMAIN)

LPF

LPF TO EXTRACT

REAL POWER

(DC TERM)

cos(2ωt)

ATTENUATED BY LPF

ω

2ω

FREQUENCY (RAD/ s)

Figure 32. Active Power-to-Frequency Conversion

DIGITAL-TO-

FREQUENCY

DIGITAL-TO-

FREQUENCY

F1

F1

F2

CF

TIME

f

OUT

FREQUENCY FREQUENCY

TIME

As can be seen in Figure 32, the frequency output CF varies over
time, even under steady load conditions. This frequency variation
is primarily due to the cos(2 ωt) component in the instantaneous
active power signal. The output frequency on CF can be up to
2048 times higher than the frequency on F1 and F2. This higher
output frequency is generated by accumulating the instantaneous
active power signal over a much shorter time while converting
it to a frequency. This shorter accumulation period means less
averaging of the cos(2 ωt) component. Consequently, some of
this instantaneous power signal passes through the digital-to­frequency conversion, which is not a problem in the
application. When CF is used for calibration purposes, the
frequency should be averaged by the frequency counter. This
averaging operation removes any ripple. If CF is measuring
energy, for example, in a microprocessor-based application, the
CF output should also be averaged to calculate power. Because
the outputs, F1 and F2, operate at a much lower frequency,
more averaging of the instantaneous active power signal is
carried out. The result is a greatly attenuated sinusoidal content
and a virtually ripple-free frequency output.

INTERFACING THE ADE7755 TO A MICROCONTROLLER FOR ENERGY MEASUREMENT

The easiest way to interface the ADE7755 to a microcontroller
is to use the CF high frequency output with the output frequency
scaling set to 2048 × F1, F2. This is done by setting SCF = 0 and
S0 = S1 = 1 (see Table 8). With full-scale ac signals on the analog
inputs, the output frequency on CF is approximately 5.5 kHz.
Figure 33 illustrates one scheme that can be used to digitize the
output frequency and carry out the necessary averaging described
in the Digital-to-Frequency Conversion section.

CF

FREQUENCY

RIPPLE

AVERAGE

FREQUENCY

TIME

ADE7755

CF

1

REVP

1

REVP MUST BE USE D IF THE METER IS BIDI RECTIONAL OR

02896-032

DIRECTION O F ENERGY F LOW I S NEEDED

Figure 33. Interfacing the ADE7755 to an MCU

COUNTER

UP/DOWN

MCU

TIMER

±10%

02896-033

As shown in Figure 33, the frequency output CF is connected to
an MCU counter or port, which counts the number of pulses in
a given integration time that is determined by an MCU internal
timer. The average power proportional to the average frequency
is given by

PowerActiveAverageFrequencyAverage ==

Counter

Time

The energy consumed during an integration period is given by

Counter

TimePowerAverageEnergy =×=×=

Time

CounterTime

For the purpose of calibration, this integration time can be
10 seconds to 20 seconds to accumulate enough pulses to ensure
correct averaging of the frequency. In normal operation, the
integration time can be reduced to 1 second or 2 seconds
depending, for example, on the required update rate of a display.
With shorter integration times on the MCU, the amount of
energy in each update may still have some small amount of
ripple, even under steady load conditions. However, over a
minute or more, the measured energy has no ripple.

POWER MEASUREMENT CONSIDERATIONS

Calculating and displaying power information always has some
associated ripple that depends on the integration period used in
the MCU to determine average power and also the load. For
example, at light loads, the output frequency can be 10 Hz. With
an integration period of 2 seconds, only about 20 pulses are
counted. The possibility of missing one pulse always exists because
the ADE7755 output frequency is running asynchronously to the
MCU timer. This possibility results in a 1-in-20 (or 5%) error in
the power measurement.

Rev. A | Page 16 of 20

ADE7755

×

×

TRANSFER FUNCTION

Frequency Outputs F1 and F2

The ADE7755 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract active power information. This active power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, for example, 0.34 Hz
maximum for ac signals with S0 = S1 = 0 (see Tabl e 7). This
means that the frequency at these outputs is generated from
active power information accumulated over a relatively long
time. The result is an output frequency that is proportional to
the average active power. The averaging of the active power
signal is implicit to the digital-to-frequency conversion. The
output frequency or pulse rate is related to the input voltage
signals by the following equation:

fGainV2V1

Freq

06.8

=

V

REF

where:

Freq = output frequency on F1 and F2 (Hz).
V1 = differential rms voltage signal on Channel 1 (volts).
V2 = differential rms voltage signal on Channel 2 (volts).
Gain = 1, 2, 8, or 16, depending on the PGA gain selection

made using logic inputs G0 and G1.

V

= the reference voltage (2.5 V ± 8%) (volts).

REF

fi = one of the four possible frequencies (f

by using the logic inputs S0 and S1, see Table 6.

Table 6. f1, f2, f3, and f4 Frequency Selection

S1 S0 f1, f2, f3, and f4 (Hz)

0 0 f1 = 1.7 3.579 MHz/221
0 1 f2 = 3.4 3.579 MHz/220
1 0 f
1 1 f

1

f1, f2, f3, or f4 is a binary fraction of the master clock and, therefore, varies if

the specified CLKIN frequency is altered.

= 6.8 3.579 MHz/219

3

= 13.6 3.579 MHz/218

4

Example 1

If full-scale differential dc voltages of +470 mV and −660 mV
are applied to V1 and V2, respectively (470 mV is the maximum
differential voltage that can be connected to Channel 1, and
660 mV is the maximum differential voltage that can be
connected to Channel 2), the expected output frequency
is calculated as follows:

Freq

06.8

=

V

REF

where:

Gain = 1, G0 = G1 = 0.
f

= f

= 1.7 Hz, S0 = S1 = 0.

i

1

V1 = +470 mV dc = 0.47 V (rms of dc = dc).
V2 = −660 mV dc = 0.66 V (rms of dc = |dc|).
V

= 2.5 V (nominal reference value).

REF

××××

i

2

, f2, f3, or f4) selected

1

XTAL/CLKIN1

fGainV2V1

××××

i

2

If the on-chip reference is used, actual output frequencies may
vary from device to device due to a reference tolerance of ±8%.

Example 2

In this example, with ac voltages of ±470 mV peak applied to
V1 and ±660 mV peak applied to V2, the expected output
frequency is calculated as follows:

7.1166.047.006.8

=Freq

××

2

5.222

××

34.0

=

where:

Gain = 1, G0 = G1 = 0.
f

= f

= 1.7 Hz, S0 = S1 = 0.

i

1

V1 = rms of 470 mV peak ac = 0.47/√2 V.
V2 = rms of 660 mV peak ac = 0.66/√2 V.
V

= 2.5 V (nominal reference value).

REF

If the on-chip reference is used, actual output frequencies may
vary from device to device due to a reference tolerance of ±8%.

As can be seen from these two example calculations, the maximum
output frequency for ac inputs is always half that for dc input
signals. Table 7 shows a complete listing of all the maximum
output frequencies.

Table 7. Maximum Output Frequency on F1 and F2

S1 S0

Maximum Frequency
for DC Inputs (Hz)

Maximum Frequency
for AC Inputs (Hz)

0 0 0.68 0.34
0 1 1.36 0.68
1 0 2.72

1.36

1 1 5.44 2.72

Frequency Output CF

The pulse output CF is intended for use during calibration. The
output pulse rate on CF can be up to 2048 times the pulse rate
on F1 and F2. The lower the f

frequency selected (i = 1, 2, 3, or 4),

i

the higher the CF scaling (except for the high frequency mode
SCF = 0, S1 = S0 = 1). Table 8 shows how the two frequencies
are related, depending on the state of the logic inputs, S0, S1,
and SCF. Because of its relatively high pulse rate, the frequency
at CF is proportional to the instantaneous active power. As is
the case with F1 and F2, the frequency is derived from the
output of the low-pass filter after multiplication. However, because
the output frequency is high, this active power information is
accumulated over a much shorter time. Therefore, less averaging is
carried out in the digital-to-frequency conversion. With much
less averaging of the active power signal, the CF output is much
more responsive to power fluctuations (see the signal processing
block diagram in Figure 22).

Rev. A | Page 17 of 20

ADE7755

Table 8. Maximum Output Frequency on CF

SCF S1 S0 f1, f2, f3, and f4 (Hz) CF Maximum for AC Signals

1 0 0 f1 = 1.7 128 × F1, F2 = 43.52 Hz
0 0 0 f1 = 1.7 64 × F1, F2 = 21.76 Hz
1 0 1 f2 = 3.4 64 × F1, F2 = 43.52 Hz
0 0 1 f2 = 3.4 32 × F1, F2 = 21.76 Hz
1 1 0 f3 = 6.8 32 × F1, F2 = 43.52 Hz
0 1 0 f3 = 6.8 16 × F1, F2 = 21.76 Hz
1 1 1 f4 = 13.6 16 × F1, F2 = 43.52 Hz
0 1 1 f4 = 13.6 2048 × F1, F2 = 5.57 kHz

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Ta ble 6, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended to be used to drive
the energy register (electromechanical or other). Because only
four different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant of
100 imp/kWh with a maximum current between 10 A and 120 A.
Table 9 shows the output frequency for several maximum currents

) with a line voltage of 220 V. In all cases, the meter

(I

MAX

constant is 100 imp/kWh.

Table 9. F1 and F2 Frequency at 100 imp/kWh

I

(A) F1 and F2 (Hz)

MAX

12.5 0.076
25 0.153
40 0.244
60 0.367
80 0.489
120 0.733

The fi frequencies (i = 1, 2, 3, or 4) allow complete coverage of
this range of output frequencies on F1 and F2. When designing
an energy meter, the nominal design voltage on Channel 2 (voltage)
should be set to half scale to allow for calibration of the meter
constant. The current channel should also be no more than half
scale when the meter sees maximum load. This allows overcurrent
signals and signals with high crest factors to be accommodated.
Table 10 shows the output frequency on F1 and F2 when both
analog inputs are half scale. The frequencies listed in Tabl e 10
align well with those listed in Table 9 for maximum load.

Table 10. F1 and F2 Frequency with Half-Scale AC Inputs

F1 and F2 Frequency on CH1 and

S1 S0 f1, f2, f3, and f4 (Hz)

0 0 f1 = 1.7 0.085
0 1 f2 = 3.4 0.17
1 0 f3 = 6.8 0.34
1 1 f4 = 13.6 0.68

CH2 Half-Scale AC Inputs (Hz)

When selecting a suitable f
meter design, the frequency output at I
with a meter constant of 100 imp/kWh should be compared with
Column 4 of Tabl e 10 . The frequency that is closest in Table 10
determines the best choice of f
example, if a meter with a maximum current of 25 A is being
designed, the output frequency on F1 and F2 with a meter constant
of 100 imp/kWh is 0.153 Hz at 25 A and 220 V (from Tab le 9).
Table 10 , the closest frequency to 0.153 Hz in Column 4, is 0.17 Hz.
Therefore, f

(3.4 Hz, see Table 6) is selected for this design.

2

FREQUENCY OUTPUTS

Figure 2 shows a timing diagram for the various frequency
outputs. The F1 and F2 outputs are the low frequency outputs
that can be used to directly drive a stepper motor or electro­mechanical impulse counter. The F1 and F2 outputs provide
two alternating low going pulses. The pulse width (t
275 ms, and the time between the falling edges of F1 and F2 (t
is approximately half the period of F1 (t
F1 and F2 falls below 550 ms (1.81 Hz), the pulse width of F1 and
F2 is set to half of their period. The maximum output frequencies
for F1 and F2 are shown in Table 7 .

The high frequency CF output is intended to be used for
communications and calibration purposes. CF produces a
90 ms wide active high pulse (t
to active power. The CF output frequencies are listed in Table 8.
As in the case of F1 and F2, if the period of CF (t
180 ms, the CF pulse width is set to half the period. For example,
if the CF frequency is 20 Hz, the CF pulse width is 25 ms.

When the high frequency mode is selected (that is, SCF = 0,
S1 = S0 = 1), the CF pulse width is fixed at 18 μs. Therefore, t
is always 18 μs, regardless of the output frequency on CF.

frequency (i = 1, 2, 3, or 4) for a

i

(maximum load)

MAX

frequency (i = 1, 2, 3, or 4). For

i

) is set at

1

). If, however, the period of

2

) at a frequency proportional

4

) falls below

5

)

3

4

Rev. A | Page 18 of 20

ADE7755

NO LOAD THRESHOLD

The ADE7755 also includes a no load threshold and start-up
current feature that eliminates any creep effects in the meter. The
ADE7755 is designed to issue a minimum output frequency in all
modes except when SCF = 0 and S1 = S0 = 1. The no load detection
threshold is disabled in this output mode to accommodate
specialized application of the ADE7755. Any load generating a
frequency lower than this minimum frequency will not cause a
pulse to be issued on F1, F2, or CF. The minimum output
frequency is given as 0.0014% of the full-scale output frequency
for each of the f

frequencies (i = 1, 2, 3, or 4), see Tab le 6 .

i

For example, in an energy meter with a meter constant of
100 imp/kWh on F1 and F2 using f
output frequency at F1 or F2 is 0.0014% of 3.4 Hz or 4.76 × 10

−3

This is 3.05 × 10

Hz at CF (64 × F1 Hz). In this example, the no

(3.4 Hz), the maximum

2

−5

Hz.

load threshold is equivalent to 1.7 W of the load or a start-up
current of 8 mA at 220 V. IEC 1036 states that the meter must
start up with a load current equal to or less than 0.4% Ib. For a
5 A (Ib) meter, 0.4% Ib is equivalent to 20 mA. The start-up
current of this design therefore satisfies the IEC requirement.
As illustrated in this example, the choice of f

frequency

i

(i = 1, 2, 3, or 4) and the ratio of the stepper motor display
determine the start-up current.

Rev. A | Page 19 of 20

ADE7755

OUTLINE DIMENSIONS

8.50

8.20

7.90

0.38

0.22

13

5.60

5.30

8.20

5.00

7.80

1.85

1.75

1.65

SEATING
PLANE

7.40

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

060106-A

12

2.00 MAX

0.05 MIN

COPLANARITY

0.10

24

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AG

Figure 34. 24-Lead Shrink Small Outline Package [SSOP]

(RS-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADE7755ARSZ
ADE7755ARSRLZ
EVAL-ADE7755EBZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24

1

−40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP], 13” Tape and Reel RS-24

1

−40°C to +85°C Evaluation Board

©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02896-0-8/09(A)

Rev. A | Page 20 of 20