Analog Devices ADE7752 b Datasheet

Polyphase Energy Metering IC

FEATURES

High accuracy, supports 50 Hz/60 Hz IEC 687/61036
Less than 0.1% error over a dynamic range of 500 to 1
Compatible with 3-phase/3-wire delta and 3-phase/4-wire Wye

configurations

The ADE7752* supplies average real power on the frequency

outputs F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous real power

Logic output NEGP indicates a potential miswiring or negative

power for each phase

Direct drive for electromechanical counters and 2-phase stepper

motors (F1 and F2)

Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.4 V ±8% (20 ppm/°C typical) with external

overdrive capability
Single 5 V supply, low power (60 mW typical)
Low cost CMOS process

*Patent pending.

with Pulse Output

ADE7752

GENERAL DESCRIPTION

The ADE7752 is a high accuracy polyphase electrical energy
measurement IC. The part specifications surpass the accuracy
requirements as quoted in the IEC61036 standard. The only analog
circuitry used in the ADE7752 is in the ADCs and reference circuit.
All other signal processing (e.g., multiplication, filtering, and sum­mation) is carried out in the digital domain. This approach
provides superior stability and accuracy over extremes in environ­mental conditions and over time.

The ADE7752 supplies average real power information on the low
frequency outputs, F1 and F2. These logic outputs may be used to
directly drive an electromechanical counter or to interface with an
MCU. The CF logic output gives instantaneous real power informa­tion. This output is intended to be used for calibration purposes.

The ADE7752 includes a power supply monitoring circuit on the
V

pin. The ADE7752 will remain inactive until the supply voltage

DD

on V

reaches 4 V. If the supply falls below 4 V, the ADE7752 will

DD

also be reset and no pulses will be issued on F1, F2, and CF.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no load threshold
ensures the part does not exhibit any creep when there is no load.

FUNCTIONAL BLOCK DIAGRAM

5

IAP

IAN

6

16

VA P

IBP

7

8

IBN

15

VBP

9

ICP

10

ICN

VCP

14

13

VN

2.4V REF

11 12 4 18 21 22 23 24 1

AGND

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

ADC

ADC

ADC

ADC

ADC

ADC

Ω

4k

REF

IN/OUT

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

Figure 1. Functional Block Diagram

The ADE7752 is available in a 24-lead SOIC package.

ADE7752

Σ

V

DD

3

POWER
SUPPLY

MONITOR

2

DGND

19

CLKIN

CLKOUT

20

CFS1 F1F2S0SCFNEGP

02676-A-001

ABS

17

LPF

LPF

LPF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

X

X

X

DIGITAL-TO-FREQUENCY CONVER TER

Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADE7752

TABLE OF CONTENTS

Specifications..................................................................................... 3

Meter Connections..................................................................... 15

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Test Circuit ......................................................................................11

Theory of Operation...................................................................... 12

Power Factor Considerations.................................................... 12

Nonsinusoidal Voltage and Current......................................... 13

Analog Inputs.................................................................................. 14

Current Channels....................................................................... 14

Voltage Channels........................................................................ 14

Typical Connection Diagrams ...................................................... 15

Current Channel Connection................................................... 15

Voltage Channels Connection .................................................. 15

Power Supply Monitor ................................................................... 17

HPF and Offset Effects .............................................................. 17

Digital-to-Frequency Conversion................................................ 18

Mode Selection of the Sum of the Three Active Energies .... 19

Power Measurement Considerations....................................... 19

Transfer Function........................................................................... 20

Frequency Outputs F1 and F2.................................................. 20

Frequency Output CF................................................................ 21

Selecting a Frequency for an Energy Meter Application........... 22

Frequency Outputs..................................................................... 22

No Load Threshold .................................................................... 23

Negative Power Information..................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

Location Page

9/03—Data Sheet Changed from Rev. A to Rev. B

Updated Format................................................................................................................................................................................................... Universal

Change to Figure 19 .........................................................................................................................................................................................................15

5/03—Data Sheet Changed from Rev. 0 to Rev. A

to F

Changed F

Change to Figure 6 ...........................................................................................................................................................................................................10

Changes to Frequency Outputs F1 and F2 section ......................................................................................................................................................13

Replaced Table II ..............................................................................................................................................................................................................13

Changes to Examples 1, 2, and 3.....................................................................................................................................................................................14

Replaced Table III.............................................................................................................................................................................................................14

Replaced Tables IV, V, and VI ..........................................................................................................................................................................................15

Changes to SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION section.......................................................................15

Changes to NO LOAD THRESHOLD section .............................................................................................................................................................16

Replaced Table VII............................................................................................................................................................................................................16

1–5

............................................................................................................................................................................................. Universal

1–7

Rev. B | Page 2 of 24

ADE7752

SPECIFICATIONS

Table 1. VDD = 5 V± 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, T

Parameter Conditions Min Typ Max Unit

ACCURACY

Measurement Error on Current

Channel

Phase Error between Channels

1, 2

PF = 0.8 Capacitive
PF = 0.5 Capacitive

Voltage Channel with Full-Scale Signal (±500 mV), 25°C,
Over a Dynamic Range of 500 to 1 0.1 % Reading

AC Power Supply Rejection SCF = 0; S0 = S1 = 1

Output Frequency Variation (CF)

IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms,
@ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz

DC Power Supply Rejection S1 = 1; S0 = SCF = 0

Output Frequency Variation (CF)

V1 = 100 mV rms, V2 = 100 mV rms, V

= 5 V ±250 mV 0.1

DD

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels VAP–VN, VBP–VN, VCP–VN, IAP–IAN, IBP–IBN, ICP–ICN ±0.5 V peak Diff.

Input Impedance (DC) CLKIN = 10 MHz 370 410 kΩ

Bandwidth (–3 dB) CLKIN/256, CLKIN = 10 MHz 14 kHz

ADC Offset Error

1, 2

Gain Error External 2.5 V Reference, IA = IB = IC = 500 mV dc ±9

REFERENCE INPUT

REF

Input Voltage Range 2.4 V + 8%

IN/OUT

Input Impedance

Input Capacitance

2.4 V – 8% 2.2

ON-CHIP REFERENCE Nominal 2.4 V

Reference Error

Temperature Coefficient
CLKIN All Specifications for CLKIN of 10 MHz

Input Clock Frequency
LOGIC INPUTS3

ACF, S0, S1, and ABS

Input High Voltage, V
Input Low Voltage, V

V

INH

V

INL

= 5 V ±5% 2.4

DD

= 5 V ±5%

DD

Input Current, IIN Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN

LOGIC OUTPUTS3

F1 and F2

Output High Voltage, VOH I
Output Low Voltage, VOL I

CF and NEGP

Output High Voltage, VOH V
Output Low Voltage, VOL V

= 10 mA, V

SOURCE

= 10 mA, VDD = 5 V

SINK

= 5 V 4.5

DD

= 5 V, I

DD

= 5 V, I

DD

= 5 mA 4

SOURCE

= 5 mA

SINK

POWER SUPPLY For Specified Performance

VDD 5 V ±5% 4.75

IDD

1

See section for explanation of specifications. Terminology

2

See plots in Typi . cal Performance Characteristics

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

MIN

to T

= –40°C to+ 85°C

MAX

±0.1 °(Degrees)
±0.1 °(Degrees)

0.01 % Reading

3.3

±25 mV

2.6 V

10 pF

% Reading

% Ideal

V
kΩ

±200 mV

25 ppm/°C

10 MHz

0.8 V
±3 µA

V

10 pF

0.5 V

0.5 V

V

V

5.25 V

12 16 mA

Rev. B | Page 3 of 24

ADE7752

TIMING CHARACTERISTICS

Table 2. VDD = 5 V ± 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, T

MIN

to T

= –40°C to +85°C

MAX

Parameter Conditions Unit

3

t

275 F1 and F2 Pulse Width (Logic High) ms

1

t2 See Table 6 Output Pulse Period. See Transfer Function section. sec
t3 1/2 t2 Time between F1 Falling Edge and F2 Falling Edge sec

3, 4

t

96 CF Pulse Width (Logic High) ms

4

5

t

See Table 7 CF Pulse Period. See Transfer Function section. sec

5

t6 CLKIN/4 Minimum Time between F1 and F2 Pulse sec

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See . Figure 2

3

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Fre section. quency Outputs

4

CF is not synchronous to F1 or F2 frequency outputs.

5

The CF pulse is always 1 µs in the high frequency mode. See section.

Frequency Outputs

t

1

F1

t

6

t

2

t

F2

3

1, 2

t

4

CF

t

5

02676-A-003

Figure 2. Timing Diagram for Frequency Outputs

Rev. B | Page 4 of 24

ADE7752

ABSOLUTE MAXIMUM RATINGS

Table 3. TA = 25°C, unless otherwise noted

Parameter Rating

VDD to AGND –0.3 V to +7 V
VDD to DGND –0.3 V to +7 V
Analog Input Voltage to AGND

VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN,

ICP, and ICN –6 V to +6 V
Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
24-Lead SOIC, Power Dissipation 88 mW
θJA Thermal Impedance 250°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 5 of 24

ADE7752

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7752 is defined by the following formula:



=

ErrorPercentage 100




7752

EnergyTrue

Error between Channels

The HPF (high-pass filter) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
also placed in the current channel. The phase correction net­work ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range of 40 Hz to 1 kHz. See Figure 25 and
Figure 26.

Power Supply Rejection

This quantifies the ADE7752 measurement error as a
percentage of reading when the power supplies are varied.

For the ac PSR measurement, a reading at a nominal supply
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supply and a second reading is obtained under the



EnergyTrue–ADE by Registered Energy

%

×




same input signal levels. Any error introduced is expressed as a
percentage of reading. See definition for Measurement Error.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

ADC Offset Error

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see an analog input signal offset.
However, as the HPF is always present, the offset is removed
from the current channel and the power calculation is not
affected by this offset.

Gain Error

The gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function. See the Transfer
Function section.

Rev. B | Page 6 of 24

ADE7752

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CF

Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This
output is intended to be used for calibration purposes. See the SCF pin description.

2 DGND

This provides the ground reference for the digital circuitry in the ADE7752, i.e., multiplier, filters, and digital-to­frequency converter. Because the digital return currents in the ADE7752 are small, it is acceptable to connect
this pin to the analog ground plane of the whole system.

3 VDD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply voltage
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF
capacitor in parallel with a 100 nF ceramic capacitor.

4 NEGP

This logic output will go logic high when negative power is detected on any of the three phase inputs, i.e.,
when the phase angle between the voltage and the current signals is greater than 90°. This output is not
latched and will be reset when positive power is once again detected. See the
section.

5, 6;
7, 8;
9, 10

IAP, IAN;
IBP, IBN;
ICP, ICN

Analog Inputs for Current Channel. This channel is intended for use with the current transducer and is
referenced in this document as the current channel. These inputs are fully differential voltage inputs with
maximum differential input signal levels of ±0.5 V. See the Analog Inputs section. Both inputs have internal ESD
protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of
permanent damage.

11 AGND

This pin provides the ground reference for the analog circuitry in the ADE7752, i.e., ADCs, temperature sensor,
and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the
system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and
voltage transducers, and so on. To keep ground noise around the ADE7752 to a minimum, the quiet ground
plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device
on the analog ground plane.

12 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ±
8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at
this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor.

13–16

VN, VCP, VBP,
VAP

Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer and is
referenced in this document as the voltage channel. These inputs are single-ended voltage inputs with a
maximum signal level of ±0.5 V with respect to VN for specified operation. All inputs have internal ESD
protection circuitry; in addition, an overvoltage of ± 6 V can be sustained on these inputs without risk of
permanent damage.

17

This logic input is used to select the way the three active energies from the three phases are summed. This

ABS

offers the designer the capability to do the arithmetical sum of the three energies (ABS
the absolute values (ABS

18 SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table
7 shows how the calibration frequencies are selected.

19 CLKIN

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of
between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data
sheet for load capacitance requirements.

23

22

21

20

19

18

17

16

15

14

13

F1

F2

S1

S0

CLKOUT

CLKIN

SCF

ABS

VAP

VBP

VCP

VN

02676-A-003

REF

124

CF

2

DGND

V

3

DD

4

NEGP

5

IAP

ADE7752

6

IAN

TOP VIEW

(Not to Scale)

7

IBP

8

IBN

9

ICP

10

ICN

11

AGND

12

IN/OUT

Figure 3. Pin Configuration

Negative Power Information

logic high) or the sum of

logic low). See the section.

Mode Selection of the Sum of the Three Active Energies

Rev. B | Page 7 of 24

ADE7752

Pin No. Mnemonic Description

20 CLKOUT

21, 22 S0, S1

24, 23 F1, F2

A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the
ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a
crystal is being used.

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the
an Energy Meter Application

Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used
to drive electromechanical counters and 2-phase stepper motors directly. See the Transfer Function section.

Selecting a Frequency for

section.

Rev. B | Page 8 of 24