ANALOG DEVICES ADDI7100 Service Manual

Complete, 12-Bit, 45 MHz

FEATURES

Pin-compatible upgrade for the AD9945 45 MHz correlated double sampler (CDS) with variable gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) Low noise optical black clamp circuit Preblanking function 12-bit, 45 MHz ADC No missing codes guaranteed 3-wire serial digital interface 3 V single-supply operation Space-saving, 32-lead, 5 mm × 5 mm LFCSP

APPLICATIONS

Digital still cameras Digital video camcorders PC cameras Portable CCD imaging devices CCTV cameras

FUNCTIONAL BLOCK DIAGRAM

CCD Signal Processor

ADDI7100

GENERAL DESCRIPTION

The ADDI7100 is a complete analog signal processor for chargecoupled device (CCD) applications. It features a 45 MHz, single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The signal chain for the ADDI7100 consists of a correlated double sampler (CDS), a digitally controlled variable gain amplifier (VGA), a black level clamp, and a 12-bit ADC.

The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. The ADDI7100 operates from a single 3 V power supply, typically dissipates 125 mW, and is packaged in a space-saving, 32-lead LFCSP.

REFT

REFB

PBL

CCDIN

AVD D

AVS S

ADDI7100

−3dB, 0dB, +3dB, +6dB

CDS

6dB TO 42dB

VGA

CONTROL

REGISTERS

DIGITAL

INTERFACE

BAND GAP

REFERENCE

12-BIT

ADC

CLP

INTERNAL

SDATASCKSL

Figure 1.

TIMING

DATACLKSHDSHP

DRVDD

DRVSS

DOUT D0 TO D11

CLPOB

DVDD

DVSS

07608-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADDI7100

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

General Specifications ................................................................. 3

Digital Specifications ................................................................... 3

System Specifications ................................................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Equivalent Input Circuits .............................................................. 10

Terminology .................................................................................... 11

Circuit Description and Operation .............................................. 12

DC Restore .................................................................................. 12

Correlated Double Sampler (CDS) .......................................... 12

Optical Black Clamp .................................................................. 12

Analog-to-Digital Converter (ADC) ....................................... 13

Variable Gain Amplifier (VGA) ............................................... 13

Digital Data Outputs .................................................................. 13

Applications Information .............................................................. 14

Initial Power-On Sequence ....................................................... 15

Grounding and Decoupling Recommendations .................... 15

Serial Interface Timing .................................................................. 16

Complete Register Listing ............................................................. 17

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

6/10—Rev. B to Rev. C

Changes to 0x0D Description and 0xFF Description in

Table 8 .............................................................................................. 18

9/09—Rev. A. to Rev. B

Changes to Features Section............................................................ 1

Changed Power-Down Mode to Full Standby Mode, Table 1 .... 3

Moved Timing Diagrams Section .................................................. 5

Changes to Table 4, Figure 3, and Figure 4 ................................... 5

Changes to Figure 9 Caption ......................................................... 10

Changes to Optical Black Clamp Section .................................... 12

Changes to Initial Power-On Sequence Section ......................... 15

Changes to Figure 16 ...................................................................... 16

Changes to Table 8 .......................................................................... 17

2/09—Rev. 0 to Rev. A

Changes to Serial Interface Timing Section ................................ 16

Changes to Figure 16 and Figure 17 ............................................. 16

10/08—Revision 0: Initial Version

Rev. C | Page 2 of 20

ADDI7100

SPECIFICATIONS

GENERAL SPECIFICATIONS

to T

MIN

Table 1.

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C Storage −65 +150 °C

POWER SUPPLY VOLTAGE

Analog, Digital, Digital Driver 2.7 3.6 V

POWER CONSUMPTION

Normal Operation 125 mW Full Standby Mode 1 mW

MAXIMUM CLOCK RATE 45 MHz

DIGITAL SPECIFICATIONS

DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.

Table 2.

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage VIH 2.1 V Low Level Input Voltage VIL 0.6 V High Level Input Current IIH 10 μA Low Level Input Current IIL 10 μA Input Capacitance CIN 10 pF

LOGIC OUTPUTS

High Level Output Voltage, IOH = 2 mA VOH 2.2 V Low Level Output Voltage, IOL = 2 mA VOL 0.5 V

, AVDD = DVDD = DRVDD = 3 V, f

MAX

= 45 MHz, unless otherwise noted.

SAMP

Rev. C | Page 3 of 20

ADDI7100

SYSTEM SPECIFICATIONS

to T

MIN

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

CDS Input characteristics definition1

Allowable CCD Reset Transient 0.5 1.2 V CDS Gain Accuracy VGA gain = 6 dB (Code 15, default value)

Maximum Input Range Before Saturation

Maximum CCD Black Pixel Amplitude Positive offset definition1

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range

BLACK LEVEL CLAMP MEASURED AT ADC OUTPUT

Clamp Level Resolution 2048 Steps Clamp Level Measured at ADC output

ADC

Resolution 12 Bits Differential Nonlinearity (DNL) −1.0 ±0.5 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (REFT) 2.0 V Reference Bottom Voltage (REFB) 1.0 V

SYSTEM PERFORMANCE Specifications include entire signal chain

Gain Accuracy

Peak Nonlinearity, 1 V Input Signal 6 dB total gain (default CDS, VGA) 0.1 % Total Output Noise AC grounded input, 6 dB total gain 0.8 LSB rms Power Supply Rejection (PSR) Measured with step change on supply 45 dB

Input signal characteristics are defined as shown in . Figure 2

, AVDD = DVDD = DRVDD = 3 V, f

MAX

= 45 MHz, unless otherwise noted.

SAMP

−3 dB CDS Gain −2.45 −2.95 −3.45 dB 0 dB CDS Gain Default setting 5.40 5.90 6.40 dB +3 dB CDS Gain 8.65 9.15 9.65 dB +6 dB CDS Gain 11.10 11.60 12.10 dB

0 dB CDS Gain Default setting 1.0 V p-p

−3 dB CDS Gain 1.4 V p-p +6 dB CDS Gain 0.5 V p-p

0 dB CDS Gain Default setting −100 +200 mV +6 dB CDS Gain −50 +100 mV

Minimum Gain (VGA Code 15) See Figure 13 for VGA curve 6.0 dB Maximum Gain (VGA Code 1023)

See Variable Gain Amplifier (VGA)

42.0 dB

section for VGA gain equation

Minimum Clamp Level (Code 0) 0 LSB Maximum Clamp Level (Code 1023) 511 LSB

Low Gain (VGA Code 15) 6 dB total gain (default CDS, VGA) 5.4 5.9 6.4 dB Maximum Gain (VGA Code 1023) 41.4 41.9 42.4 dB

500mV TYP

RESET TRANSIENT

OPTICAL BLACK PI XEL

100mV TYP

INPUT SIG NAL RANGE

Figure 2.

Rev. C | Page 4 of 20

1V TYP

7608-002

ADDI7100

TIMING SPECIFICATIONS

CL = 20 pF, f

Table 4.

Parameter Symbol Min Typ Max Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period t DATACLK High/Low Pulse Width t SHP Pulse Width t SHD Pulse Width t CLPOB Pulse Width1 2 20 Pixels SHP Rising Edge to SHD Falling Edge tS3 5.5 ns SHP Rising Edge to SHD Rising Edge tS1 9 11 t SHD Rising Edge to SHP Rising Edge tS2 9 11 t SHD Rising Edge to SHP Falling Edge tS4 5.5 ns Internal Clock Delay tID 4 ns

DATA OUTPUTS

Output Delay tOD 15 ns Pipeline Delay 15 Cycles

SERIAL INTERFACE

Maximum SCK Frequency (Must Not Exceed Pixel Rate) f SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Rising Edge to SDATA Valid Hold tDH 10 ns

Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.

Timing Diagrams

= 45 MHz, unless otherwise noted. See Figure 3, Figure 4, and Figure 16.

SAMP

22 ns

CONV

9 11 ns

ADC

5.5 ns

SHP

5.5 ns

SHD

40 MHz

SCLK

− tS2 ns

CONV

− tS1 ns

CONV

CCD SIGNAL (CCDIN)

DATACLK

OUTPUT

DATA

NOTES

1. RECOMMENDED P LACEMENT FO R DATACLK RISI NG (ACTIVE) EDGE IS NEAR THE SHP OR SHD RI SIN (ACTIVE) EDG E. THE BEST LOCATI ON FOR LOWEST NO ISE WI LL BE SYST EM DEPENDENT.

. CCD SIGNAL I S SAMPLED AT SHP AND SHD RISING EDGES.

SHP

SHD

PIXEL N PIXEL

N – 15 N – 14 N – 13 N – 1 N

N + 1

CONV

PIXEL

N + 2

Figure 3. CCD Sampling Timing (Default Polarity Settings)

Rev. C | Page 5 of 20

PIXEL N + 14

PIXEL N + 15

07608-012

ADDI7100

EFFECTIVE PIXELS

CCD SIGNAL (CCDIN)

CLPOB

PBLK

UTPUT

DATA

NOTES

1. CLPOB AND PBLK SHOUL D BE ALIGNED W ITH THE CCD S IGNAL INPUT (CCDIN) . CLPOB WI

. PBLK SIGNAL IS OPTI ONAL. KEEP THE PBLK PIN IN THE INACTI VE STATE IF NOT USED. . DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS FIFT EEN DATACLK CYCLES.

EFFECTIVE PIXEL DATA

L OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.

OPTICAL BLACK PIXELS

ACTIVE

OB PIXEL DATA DUMMY BLACK EF FECTIVE DATA

HORIZONT

BLANKING

ACTIVE

Figure 4. Typical Clamp Timing (Default Polarity Settings)

DUMMY PIXELS EFFECTIVE PIXELS

07608-013

Rev. C | Page 6 of 20

+ 14 hidden pages

ANALOG DEVICES ADDI7100 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

GENERAL SPECIFICATIONS

DIGITAL SPECIFICATIONS

SYSTEM SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams