Analog Devices ADCMP551 2 3 Datasheet

Single-Supply, High Speed

FEATURES

Single power supply
500 ps propagation delay input to output
125 ps overdrive dispersion
Differential PECL/LVPECL compatible outputs
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
700 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable hysteresis

APPLICATIONS

Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers

PECL/LVPECL Comparators

ADCMP551/ADCMP552/ADCMP553

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INPUT

INVERTING

INPUT

LATCH ENABLE
INPUT

GENERAL DESCRIPTION

The ADCMP551/ADCMP552/ADCMP553 are single-supply,
high speed comparators fabricated on Analog Devices’
proprietary XFCB process. The devices feature a 500 ps
propagation delay with less than 125 ps overdrive dispersion.
Overdrive dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP552.

A differential input stage permits consistent propagation delay
with a common-mode range from –0.2 V to VCCI – 2.0 V.
Outputs are complementary digital signals and are fully
compatible with PECL and 3.3V LVPECL logic families. The
outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to VCCO − 2 V. A latch
input is included and permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.

HYS*

ADCMP551/
ADCMP552/

ADCMP553

LATCH ENABLE
INPUT

*ADCMP552 ONLY

Figure 1.

Q OUTPUT

Q OUTPUT

04722-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The ADCMP551/ADCMP552/ADCMP553 are specified over
the –40°C to +85°C industrial temperature range. The
ADCMP551 is available in a 16-lead QSOP package; the
ADCMP552 is available in a 20-lead QSOP package; and the
ADCMP553 is available in an 8-lead MSOP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADCMP551/ADCMP552/ADCMP553

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Timing Information ....................................................................... 10

Application Information................................................................ 11

REVISION HISTORY

10/04—Revision 0: Initial Version

Clock Timing Recovery............................................................. 11

Optimizing High Speed Performance ..................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 12

Minimum Input Slew Rate Requirement ................................ 12

Typical Application Ci r c u it s ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP551/ADCMP552/ADCMP553

SPECIFICATIONS

V

= 3.3 V, V

CCI

Table 1. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range −0.2 V
Input Differential Voltage Range −3 +3 V
Input Offset Voltage V
Input Offset Voltage Channel Matching ±1.0 mV
Offset Voltage Tempco ∆VOS/d
Input Bias Current I
Input Bias Current Tempco -5.0 nA/°C
Input Offset Current −3.0 ±1.0 +3.0 µA
Input Capacitance C
Input Resistance, Differential Mode 1800 kΩ
Input Resistance, Common Mode 1000 kΩ
Active Gain A
Common-Mode Rejection Ratio CMRR VCM = −0.2 V to +1.3 V 76 dB
Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Voltage Range
Latch Enable Differential Voltage Range 0.4 1.0 V
Latch Enable Input High Current @ V
Latch Enable Input Low Current @ V
LE Voltage, Open Latch inputs not connected V
LE

Voltage, Open
Latch Setup Time t
Latch Hold Time t
Latch to Output Delay t
Latch Minimum Pulse Width t

DC OUTPUT CHARACTERISTICS

Output Voltage—High Level V
Output Voltage—Low Level V

AC OUTPUT CHARACTERISTICS

Rise Time t
Fall Time t

AC OUTPUT CHARACTERISTICS

Rise Time t
Fall Time t

AC PERFORMANCE

Propagation Delay t
V
Propagation Delay Tempco ∆tPD/d
Prop Delay Skew—Rising Transition to

Falling Transition
Within Device Propagation Delay

Skew—Channel-to-Channel
Overdrive Dispersion 20 mV ≤ VOD ≤ 100 mV 75 ps
Overdrive Dispersion 50 mV ≤ VOD ≤ 1.0 V 75 ps
Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 75 ps
Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps
Duty Cycle Dispersion 33 MHz, 1 V/ns, VCM = 0.5 V 10 ps

Common-Mode Voltage Dispersion 1 V swing, 0.3 V ≤ VCM ≤ 0.8 V 10 ps

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

OS

T

IN

IN

V

Latch inputs not connected V

S

H

, t

PLOH

PLOL

PL

OH

OL

R

F

(ADCMP553)

R

F

PD

T

V

V

– 2.0 V

CCI

−IN = 0 V, +IN = 0 V −10.0 ±2.0 +10.0 mV

2.0 µV/°C

−IN = −0.2 V, +IN = +1.3 V −28.0 -6.0 +5.0 µA

1.0 pF

60 dB

= ∞ ±0.5 mV

HYS

V

– 0.8 V −150 +150 µA

CCI

– 1.8 V −150 +150 µA

CCI

– 1.8 V

CCI

– 0.15 V

CCI

/2 – 0.075 V

CCI

– 0.8 V

CCI

CCI

/2 + 0.075 V

CCI

V

VOD = 250 mV 100 ps
VOD = 250 mV 100 ps
VOD = 250 mV 450 ps
VOD = 250 mV 700 ps

PECL 50 Ω to VDD − 2.0 V V
PECL 50 Ω to VDD − 2.0 V V

− 1.15 V

CCO

− 2.00 V

CCO

− 0.78 V

CCO

− 1.54 V

CCO

10% to 90% 510 ps
10% to 90% 490 ps

10% to 90% 440 ps
10% to 90% 410 ps

VOD = 1 V 500 ps

= 20 mV 625 ps

OD

VOD = 1 V 0.25 ps/°C

= 1 V 35 ps

OD

= 1 V 35 ps

OD

Rev. 0 | Page 3 of 16

ADCMP551/ADCMP552/ADCMP553

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE (continued)

Equivalent Input Rise Time Bandwidth1 BW

EQ

Maximum Toggle Rate >50% output swing 800 MHz
Minimum Pulse Width PW

MIN

RMS Random Jitter

Unit-to-Unit Propagation Delay Skew 50 ps

POWER SUPPLY (ADCMP551/ADCMP552)

Input Supply Current I
Output Supply Current I

VCCI

VCCO

Output Supply Current @ 3.3 V with load 40 55 70 mA
Input Supply Voltage V
Output Supply Voltage V
Positive Supply Differential V
Power Dissipation P

CCI

CCO

CCO

D

− V

Power Dissipation Dual, with load 90 110 130 mW
DC Power Supply Rejection Ratio—V
DC Power Supply Rejection Ratio—V

CCI

CCO

PSRR
PSRR

VCCI

VCCO

POWER SUPPLY (ADCMP553)

Positive Supply Current I

VCC

Positive Supply Current @ 3.3 V with load 35 42 mA
Positive Supply Voltage V
Power Dissipation P

CC

D

Power Dissipation Dual, with load 60 75 mW
DC Power Supply Rejection Ratio—V

PSRR

CC

VCC

HYSTERESIS (ADCMP552 Only)

Programmable Hysteresis 0 40 mV

1

Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/√ (tr

where tr

is the 20/80 input transition time applied to the comparator and tr

IN

0 V to 1 V swing, 2 V/ns 750 MHz

∆tPD < 25 ps 700 ps

= 250 mV, 1.3 V/ns,

V

OD

1.1 ps

500 MHz, 50% duty cycle

@ 3.3 V 8 12 17 mA
@ 3.3 V without load 3 5 9 mA

Dual 3.135 3.3 5.25 V
Dual 3.135 3.3 5.25 V
–0.2 +2.3 V

CCI

Dual, without load 40 55 75 mW

75 dB
85 dB

@ 3.3 V without load 9 13 mA

Dual 3.135 3.3 5.25 V
Dual, without load 30 42 mW

70 dB

2

2

- tr

is the effective transition time as digitized by the comparator input.

COMP

COMP

),

IN

Rev. 0 | Page 4 of 16

ADCMP551/ADCMP552/ADCMP553

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Input Supply Voltage (V
Output Supply Voltage (V
Ground Voltage Differential −0.5 V to +0.5 V

Input Voltages

Input Common-Mode Voltage −0.5 V to +3.5 V
Differential Input Voltage −4.0 V to +4.0 V
Input Voltage, Latch Controls −0.5 V to +5.5 V

Output

Output Current 30 mA

Temperature

Operating Temperature, Ambient −40°C to +85°C
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C

to GND) −0.5 V to +6.0 V

CCI

to GND) −0.5 V to +6.0 V

CCO

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP551 16-lead QSOP package has a θJA (junction-to­ambient thermal resistance) of 104°C/W in still air.

The ADCMP552 20-lead QSOP package has a θ
ambient thermal resistance) of 80°C/W in still air.

The ADCMP553 8-lead MSOP package has a θ
ambient thermal resistance) of 130°C/W in still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

(junction-to-

JA

(junction-to-

JA

Rev. 0 | Page 5 of 16

ADCMP551/ADCMP552/ADCMP553

V

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

20

19

18

17

16

15

14

13

12

11

V

CCO

QB
QB
V

CCO

LEB
LEB
AGND
–INB
+INB
HYSB

04722-003

QA
QA

CCO

LEA
LEA
V

CCI

–INA
+INA

1

2

3

ADCMP551

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

QB
QB
V

CCO

LEB
LEB
AGND
–INB
+INB

Figure 2. ADCMP551 16-Lead QSOP

Pin Configuration

04722-002

V

1

CCO

QA

2

QA

3

ADCMP552

V

4

V
–INA

+INA

HYS

CCO

LEA
LEA

CCI

TOP VIEW

5

(Not to Scale)

6

7

8

9

10

Figure 3. ADCMP552 20-Lead QSOP

Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

ADCMP551 ADCMP552 ADCMP553

3, 14 1, 4, 17, 20 V
1 2 6 QA

Mnemonic Function

CCO

Logic Supply Terminal.
One of Two Complementary Outputs for Channel A. QA is logic high if the

analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.

2 3 5

QA

One of Two Complementary Outputs for Channel A. QA is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.

4 5 2 LEA

One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just

prior to the comparator’s being placed in the latch mode.
conjunction with LEA.

5 6 1

LEA One of Two Complementary Outputs for Channel A Latch Enable. In the

compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with

6 7 V

CCI

7 8 4 −INA

Input Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The

LEA

.

inverting A input must be driven in conjunction with the noninverting A input.

8 9 3 +INA

Noninverting Analog Input of the Differential Input Stage for Channel A. The

noninverting A input must be driven in conjunction with the inverting A input.
10 HYSA Programmable Hysteresis.
11 HYSB Programmable Hysteresis.
9 12 +INB

Noninverting Analog Input of the Differential Input Stage for Channel B. The

noninverting B input must be driven in conjunction with the inverting B input.
10 13 −INB

Inverting Analog Input of the Differential Input Stage for Channel B. The

inverting B input must be driven in conjunction with the noninverting B input.
11 14 8 AGND Analog Ground.

LEA

LEA
+INA
–INA

1

ADCMP553

2

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

AGND
V

CC

QA
QA

Figure 4. ADCMP553 8-Lead MSOP

Pin Configuration

LEA

must be driven in

04722-004

Rev. 0 | Page 6 of 16

ADCMP551/ADCMP552/ADCMP553

Pin No.

ADCMP551 ADCMP552 ADCMP553

12 15

13 16 LEB

15 18

16 19 QB

7 VCCPositive Supply Terminal.

Mnemonic Function

LEB One of Two Complementary Inputs for Channel B Latch Enable. In the compare

mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction

LEB

QB

with
One of Two Complementary Inputs for Channel B Latch Enable. In the compare

mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction

with
One of Two Complementary Outputs for Channel B. QB is logic low if the analog

voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.

One of Two Complementary Outputs for Channel B. QB is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.

LEB

.

.

Rev. 0 | Page 7 of 16

ADCMP551/ADCMP552/ADCMP553

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 3.3 V, V

CCI

–5

–6

–7

–8

INPUT BIAS CURRENT (µA)

–9

–10

–0.2 0.1 0.4 0.7 1.0 1.3

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V)

Figure 5. Input Bias Current vs. Input Voltage

04722-005

(+IN = 0.5V, –IN = 0V)

+IN INPUT BIAS CURRENT (µA)

–6.5

–6.6

–6.7

–6.8

–6.9

–7.0

–7.1

–7.2

–7.3

–7.4

–7.5

–40 806040200–20

TEMPERATURE (°C)

Figure 8. Input Bias Current vs. Temperature

04722-008

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

OFFSET VOLTAGE (mV)

1.60

1.55

1.50
–40 806040200–20

525

515

505

TIME (ps)

495

485

TEMPERATURE (°C)

Figure 6. Input Offset Voltage vs. Temperature

RISE

FALL

04722-006

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

OUTPUT RISE AND FALL (V)

1.6

1.5

1.4
0 0.25 0.50 0.75 1.00

Figure 9. Rise and Fall of Outputs vs. Time

460

450

440

430

TIME (ps)

420

410

TIME (ns)

RISE

FALL

RISE

FALL

1.25 1.50 1.75

04722-012

475

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

Figure 7. ADCMP551/2 Rise/Fall Time vs. Temperature

04722-007

Rev. 0 | Page 8 of 16

400

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

Figure 10. ADCMP553 Rise/Fall Time vs. Temperature

04722-010

ADCMP551/ADCMP552/ADCMP553

515

510

505

500

495

490

PROPAGATION DELAY (ps)

485

480

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

04722-011

505

504

503

502

501

500

499

498

PROPAGATION DELAY (ps)

497

496

495

–0.2 0.1 0.4 0.7 1.0 1.3

INPUT COMMON MODE VOLTAGE (V)

04722-014

Figure 11. Propagation Delay vs. Temperature

140

120

100

80

60

40

PROPAGATION DELAY ERROR (ps)

20

0

0 0.2 0.4 0.6 0.8 1.0

OVERDRIVE VOLTAGE (V)

Figure 12. Propagation Delay vs. Overdrive Voltage

120

100

80

60

40

20

PROGRAMMED HYSTERESIS (mV)

04722-012

Figure 14. Propagation Delay vs. Common-Mode Voltage

25

20

15

10

5

0

PROPAGATION DELAY ERROR (ps)

–5

0.7 9.78.77.76.75.74.73.72.71.7
PULSE WIDTH (ns)

Figure 15. Propagation Delay Error vs. Pulse Width

140

120

100

80

60

40

PROGRAMMED HYSTERESIS (mV)

20

04722-015

0

100 10 1

Figure 13. Comparator Hysteresis vs. R

R

(kΩ)

HYS

HYS

04722-009

0

0 30025020015010050

I

HYS

Figure 16. Comparator Hysteresis vs. I

(µA)

HYS

04722-025

Rev. 0 | Page 9 of 16

ADCMP551/ADCMP552/ADCMP553

TIMING INFORMATION

LATCH ENABLE

LATCH ENABLE

V

DIFFERENTIAL

INPUT VOLTAGE

IN

50%

t

S

t

H

V

OD

t

PL

V

± V

REF

OS

Q OUTPUT

Q OUTPUT

t

t

PDL

PDH

t

F

t

R

t

PLOH

t

PLOL

50%

50%

Figure 17. System Timing Diagram

Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol Timing Description

t

PDH

Input to Output High Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition

t

PDL

Input to Output Low Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition

t

PLOH

Latch Enable to Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition

t

PLOL

Latch Enable to Output Low Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition

t

H

Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs

t

PL

t

S

Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change
Minimum Setup Time

Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs

t

R

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the
20% and 80% points

t

F

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the
20% and 80% points

V

OD

Voltage Overdrive Difference between the differential input and reference input voltages

04722-016

Rev. 0 | Page 10 of 16

ADCMP551/ADCMP552/ADCMP553

APPLICATION INFORMATION

The comparators in the ADCMP55x series are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP55x design is the use of a low impedance
ground plane. A ground plane, as part of a multilayer board, is
recommended for proper high speed performance. Using a
continuous conductive plane over the surface of the circuit
board can create this, allowing breaks in the plane only for
necessary signal paths. The ground plane provides a low
inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused by
ground bounce. A proper ground plane also minimizes the
effects of stray capacitance on the circuit board.

It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close to the power supply
pins as possible on the ADCMP55x to ground. These capacitors
act as a charge reservoir for the device during high frequency
switching.

The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input pins
may be left open. The internal pull-ups on the latch pins set the
latch to transparent mode. If the latch is to be used, valid PECL
voltages are required on the inputs for proper operation. The
PECL voltages should be referenced to V

Occasionally, one of the two comparator stages within the
ADCMP551/ADCMP552 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and
as described previously.

The best performance is achieved with the use of proper PECL
terminations. The open-emitter outputs of the ADCMP55x are
designed to be terminated through 50 Ω resistors to

− 2.0 V or any other equivalent PECL termination. If high

V

CCO

speed PECL signals must be routed more than a centimeter,
microstrip or stripline techniques may be required to ensure
proper transition times and prevent output ringing.

.

CCI

LATCH ENABLE

inputs

CLOCK TIMING RECOVERY

Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator amplifier, proper design
and layout techniques should be used to ensure optimal
performance from the ADCMP55x. The performance limits of
high speed circuitry can easily be a result of stray capacitance,
improper ground impedance, or other layout issues.

Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP55x. Source resistance in combination with equivalent
input capacitance can cause a lagged response at the input, thus
delaying the output. The input capacitance of the ADCMP55x,
in combination with stray capacitance from an input pin to
ground, could result in several picofarads of equivalent
capacitance. A combination of 3 kΩ source resistance and 5 pF
input capacitance yields a time constant of 15 ns, which is
significantly slower than the 500 ps capability of the
ADCMP55x. Source impedances should be significantly less
than 100 Ω for best performance.

Sockets should be avoided due to stray capacitance and
inductance. If proper high speed techniques are used, the
ADCMP55x should be free from oscillation when the
comparator input signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP55x has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
20 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP55x is far less sensitive to input
variations than most comparator designs.

Rev. 0 | Page 11 of 16

ADCMP551/ADCMP552/ADCMP553

Propagation delay dispersion is an important specification in
critical timing applications such as ATE, bench instruments,
and nuclear instrumentation. Overdrive dispersion is defined as
the variation in propagation delay as the input overdrive
conditions are changed (Figure 18). For the ADCMP55x,
overdrive dispersion is typically 125 ps as the overdrive is
changed from 20 mV to 1 V. This specification applies for both
positive and negative overdrive since the ADCMP55x has equal
delays for positive- and negative-going inputs.

1.5V OVERDRIVE

INPUT VOLTAGE

20mV OVERDRIVE

± V

V

REF

OS

DISPERSION

Q OUTPUT

Figure 18. Propagation Delay Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a
noisy environment or where it is not desirable for the
comparator to toggle between states when the input signal is at
the switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 19. If the input voltage
approaches the threshold from the negative direction, the
comparator switches from a 0 to a 1 when the input crosses

/2. The new switching threshold becomes −VH/2. The

+V

H

comparator remains in a 1 state until the −V
crossed coming from the positive direction. In this manner,
noise centered on 0 V input does not cause the comparator to
switch states unless it exceeds the region bounded by ±V

Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 23). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.

In the ADCMP552, hysteresis is generated through the
programmable hysteresis pin. A resistor from the HYS pin to

creates a current into the part that is used to generate

V

CCI

hysteresis. Hysteresis generated in this manner is independent
of output swing and is symmetrical around the trip point. The
hysteresis versus resistance curve is shown in Figure 20.

/2 threshold is

H

04722-017

H

/2.

A current source can also be used with the HYS pin. The
relationship between the current applied to the HYS pin and the
resulting hysteresis is shown in Figure 16.

–V

H

2

0

Figure 19. Comparator Hysteresis Transfer Function

120

100

80

60

40

20

PROGRAMMED HYSTERESIS (mV)

0

100 10 1

Figure 20. Comparator Hysteresis Transfer Function

0V

OUTPUT

R

HYS

(kΩ)

+V

H

2

INPUT

1

04722-018

04722-019

MINIMUM INPUT SLEW RATE REQUIREMENT

As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 1 V/µs
or faster to ensure a clean output transition. If slew rates less
than 1 V/µs are used, hysteresis should be added to reduce the
oscillation.

Rev. 0 | Page 12 of 16

ADCMP551/ADCMP552/ADCMP553

V

V

TYPICAL APPLICATION CIRCUITS

V

IN

V

REF

+
ADCMP551/
ADCMP552/

ADCMP553

–

LATCH

ENABLE

INPUTS

ALL RESISTORS 50Ω

Figure 21. High Speed Sampling Circuits

+V

REF

V

IN

–V

REF

ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED

+
ADCMP551/
ADCMP552/
ADCMP553

–

+
ADCMP551/
ADCMP552/
ADCMP553

–

LATCH

ENABLE

INPUTS

Figure 22. High Speed Window Comparator

V

OUTPUTS

– 2V

V

CCO

04722-020

IN

REF

ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED

ADCMP551/
ADCMP552/

ADCMP553

HYS

0Ω TO 80kΩ

CCI

OUTPUTS

V

– 2.0VV

CCO

04722-026

Figure 23. Adding Hysteresis Using the HYS Control Pin

+
ADCMP551/

OUTPUTS

V

–2V

CCO

OUTPUTS

IN

Figure 24. How to Interface a PECL Output to an Instrument with a

ADCMP552/

ADCMP553

–

50 Ω to Ground Input

50Ω

50Ω

100Ω100Ω

(V

– 2V)× 2

CCO

50Ω

50Ω

04722-024

V

–2V

CCO

04722-021

Rev. 0 | Page 13 of 16

ADCMP551/ADCMP552/ADCMP553

C

Y

OUTLINE DIMENSIONS

0.341
BSC

PIN 1

0.010

0.004

OPLANARIT

0.004

20 11

1

0.065

0.049

BSC

0.012

0.008

0.025

COMPLIANT TO JEDEC STANDARDS MO-137AD

Figure 25. 20-Lead Shrink Small Outline Package [QSOP]

0.069

0.053

10

SEATING
PLANE

0.154
BSC

0.236
BSC

0.010

0.006

8°
0°

0.050

0.016

(RQ-20)

Dimensions shown in inches

3.00
BSC

8

5

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.065

0.049

0.010

0.004

COPLANARITY

0.004

Figure 26. 16-Lead Shrink Small Outline Package [QSOP]

0.193
BSC

0.012

0.008

9

8

0.154
BSC

0.069

0.053

SEATING
PLANE

0.236
BSC

0.010

0.006

16

1

PIN 1

0.025
BSC

COMPLIANT TO JEDEC STANDARDS MO-137AB

(RQ-16)

Dimensions shown in inches

8°
0°

0.050

0.016

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADCMP551BRQ −40°C to +85°C 16-Lead QSOP RQ-16
ADCMP552BRQ −40°C to +85°C 20-Lead QSOP RQ-20
ADCMP553BRM −40°C to +85°C 8-Lead MSOP RM-8 B53
EVAL-ADCMP551BRQ EVALUATION BOARD
EVAL-ADCMP552BRQ EVALUATION BOARD

Rev. 0 | Page 14 of 16

ADCMP551/ADCMP552/ADCMP553

NOTES

Rev. 0 | Page 15 of 16

ADCMP551/ADCMP552/ADCMP553

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04722–0–10/04(0)

Rev. 0 | Page 16 of 16