ANALOG DEVICES ADCLK944 Service Manual

2.5 V/3.3 V, Four LVPECL Outputs,

V

FEATURES FEATURES

Operating frequency: 7.0 GHz Operating frequency: 7.0 GHz
Broadband random jitter: 50 fs rms Broadband random jitter: 50 fs rms
On-chip input terminations On-chip input terminations
Power supply (V

APPLICATIONS APPLICATIONS

Low jitter clock distribution Low jitter clock distribution
Clock and data signal restoration Clock and data signal restoration
Level translation Level translation
Wireless communications Wireless communications
Wired communications Wired communications
Medical and industrial imaging Medical and industrial imaging
ATE and high performance instrumentation ATE and high performance instrumentation

GENERAL DESCRIPTION

The ADCLK944 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.

The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V
pin is available for biasing ac-coupled inputs.

− VEE): 2.5 V to 3.3 V Power supply (VCC − VEE): 2.5 V to 3.3 V

CC

REF

SiGe Clock Fanout Buffer

ADCLK944

FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM

ADCLK944

REF

CLK

CLK

V

REFERENCE

T

Figure 1.

The ADCLK944 features four full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias V
operation, bias V

to the positive supply and VEE to ground. For ECL

CC

to ground and VEE to the negative supply.

CC

The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to V
tial output swing of 1.6 V.

The ADCLK944 is available in a 16-lead LFCSP and is specified
for operation over the standard industrial temperature range of

−40°C to +85°C.

LVPECL

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

8770-001

− 2 V for a total differen-

CC

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADCLK944

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Clock Inputs and Outputs ........................................................... 3

Timing Characteristics ................................................................ 3

Power .............................................................................................. 4

Absolute Maximum Ratings ............................................................ 5

Determining Junction Temperature .......................................... 5

REVISION HISTORY

3/10—Revision 0: Initial Version

ESD Caution...................................................................................5

Thermal Performance ...................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Theory of Operation .........................................................................9

Clock Inputs ...................................................................................9

Clock Outputs ................................................................................9

PCB Layout Considerations ...................................................... 10

Input Termination Options ....................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. 0 | Page 2 of 12

ADCLK944

SPECIFICATIONS

Typical values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given for the
full V

− VEE = 3.3 V + 10% to 2.5 V − 5% and TA = −40°C to +85°C variation, unless otherwise noted.

CC

CLOCK INPUTS AND OUTPUTS

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC INPUT CHARACTERISTICS

Input Common-Mode Voltage V
Input Differential Voltage VID 0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance CIN 0.4 pF
Input Resistance RIN

Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ VT open

Input Bias Current 20 μA

DC OUTPUT CHARACTERISTICS

Output Voltage High Level VOH V
Output Voltage Low Level VOL V
Output Voltage, Single-Ended VO 600 960 mV VOH − VOL, output static
Voltage Reference V

Output Voltage (VCC + 1)/2 V −500 μA to +500 μA
Output Resistance 250 Ω

V

ICM

REF

+ 1.35 VCC − 0.1 V

EE

− 1.26 VCC − 0.76 V Load = 50 Ω to (VCC − 2.0 V)

CC

− 1.99 VCC − 1.54 V Load = 50 Ω to (VCC − 2.0 V)

CC

TIMING CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

AC PERFORMANCE

Maximum Output Frequency 6.2 7.0 GHz

Output Rise/Fall Time tR 35 50 75 ps 20% to 80%, measured differentially
Propagation Delay tPD 70 100 130 ps VID = 1.6 V p-p

Temperature Coefficient 75 fs/°C

Output-to-Output Skew

1

15 ps
Part-to-Part Skew 35 ps VID = 1.6 V p-p
Additive Time Jitter

Integrated Random Jitter 26 fs rms BW = 12 kHz to 20 MHz, CLK = 1 GHz
Broadband Random Jitter2 50 fs rms VID = 1.6 V p-p, 8 V/ns, V

CLOCK OUTPUT PHASE NOISE

Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11)

fIN = 1 GHz −118 dBc/Hz 100 Hz offset

−135 dBc/Hz 1 kHz offset

−144 dBc/Hz 10 kHz offset

−150 dBc/Hz 100 kHz offset

−150 dBc/Hz >1 MHz offset

1

The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.

Differential output voltage swing > 0.8 V
(see Figure 4)

= 2 V

ICM

Rev. 0 | Page 3 of 12

ADCLK944

POWER

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage Requirement VCC − VEE 2.375 3.63 V 3.3 V + 10% to 2.5 V − 5%
Power Supply Current Static

Negative Supply Current I

I

Positive Supply Current I

I

Power Supply Rejection
Output Swing Supply Rejection

1

Change in tPD per change in VCC.

2

Change in output swing per change in VCC.

1

2

35 mA VCC − VEE = 2.5 V ± 5%

VEE

37 49 mA VCC − VEE = 3.3 V ± 10%

VEE

139 mA VCC − VEE = 2.5 V ± 5%

VCC

138 165 mA VCC − VEE = 3.3 V ± 10%

VCC

PSR

−3 ps/V

VCC

PSR

28 dB

VCC

Rev. 0 | Page 4 of 12