ANALOG DEVICES ADCLK914 Service Manual
Ultrafast, SiGe, Open-Collector
V
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FEATURES FEATURES
7.5 GHz operating frequency 7.5 GHz operating frequency
160 ps propagation delay 160 ps propagation delay
100 ps output rise/fall 100 ps output rise/fall
110 fs random jitter 110 fs random jitter
On-chip input terminations On-chip input terminations
Extended industrial temperature range: −40°C to +125°C Extended industrial temperature range: −40°C to +125°C
3.3 V power supply (V
APPLICATIONS APPLICATIONS
Clock and data signal restoration Clock and data signal restoration
High speed converter clocking High speed converter clocking
Broadband communications Broadband communications
Cellular infrastructure Cellular infrastructure
High speed line receivers High speed line receivers
ATE and high performance instrumentation ATE and high performance instrumentation
Level shifting Level shifting
Threshold detection Threshold detection
GENERAL DESCRIPTION
The ADCLK914 is an ultrafast clock/data buffer fabricated on
the Analog Devices, Inc., proprietary, complementary bipolar
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914
features high voltage differential signaling (HVDS) outputs
suitable for driving the latest Analog Devices high speed digitalto-analog converters (DACs). The ADCLK914 has a single,
differential open-collector output.
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps
propagation delay and adds only 110 fs random jitter (RJ).
− VEE) 3.3 V power supply (VCC − VEE)
CC
HVDS Clock/Data Buffer
ADCLK914
FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM
V
V
CC
REF
V
V
T
T
50Ω 50Ω
D
D
D
D
The input has a center tapped, 100 Ω, on-chip termination
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS
(ac-coupled only). A V
inputs.
The HVDS output stage is designed to directly drive 1.9 V each
side into 50 Ω terminated to V
swing of 3.8 V.
The ADCLK914 is available in a 16-lead LFCSP. It is specified
for operation over the extended industrial temperature range of
−40°C to +125°C.
CC
ADCLK914
50Ω 50Ω
Q
Q
Q
Q
V
V
EE
EE
Figure 1.
pin is available for biasing ac-coupled
REF
for a total differential output
CC
06561-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADCLK914
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
10/08—Rev. 0 to Rev. A
Changes to Input Low Voltage Parameter, Table 1 ....................... 3
Changes to Output High Voltage Parameter, Table 1 ................ 3
Changes to Output Low Voltage Parameter, Table 1 .................. 3
Output Differential Range Parameter, Table 1 ............................ 3
Changes to Absolute Maximum Ratings Section ........................ 5
7/08—Revision 0: Initial Version
Typical Performance Characteristics ..............................................7
Applications Information .................................................................9
Power/Ground Layout and Bypassing ........................................9
HVDS Output Stage ......................................................................9
Interfacing to High Speed DACs .................................................9
Optimizing High Speed Performance ........................................9
Random Jitter .................................................................................9
Typical Application Circuits ..................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Rev. A | Page 2 of 12
ADCLK914
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SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = −40°C to +125°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input High Voltage VIH V
Input Low Voltage VIL V
Input Differential Range VID 0.2 3.4 V p-p
0.2 2.8 V p-p
Input Capacitance CIN 0.4 pF
Input Resistance 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ Open termination
Input Bias Current 20 µA
DC OUTPUT CHARACTERISTICS
Output High Voltage VOH V
Output Low Voltage VOL V
Output Differential Range VOD 1.54 1.95 2.22 V
Reference Voltage V
REF
Output Voltage (VCC + 1)/2 V −500 A to +500 A
Output Resistance 250 Ω
AC PERFORMANCE
Operating Frequency 7.5 GHz
Propagation Delay tPD 127 158 202 ps
Propagation Delay Temperature
140 fs/°C
Coefficient
Propagation Delay Skew (Device
65 ps V
to Device)
Output Rise Time tR 100 125 ps 20%/80%
Output Fall Time tF 80 95 ps 80%/20%
Wideband Random Jitter
1
RJ 110 fs rms VID = 1.6 V p-p, 6 V/ns, V
Additive Phase Noise
622.08 MHz −132 dBc/Hz @10 Hz offset
−143 dBc/Hz @100 Hz offset
−151 dBc/Hz @1 kHz offset
−156 dBc/Hz @10 kHz offset
−157 dBc/Hz @100 kHz offset
−156 dBc/Hz >1 MHz offset
245.76 MHz −133 dBc/Hz @10 Hz offset
−143 dBc/Hz @100 Hz offset
−153 dBc/Hz @1 kHz offset
−158 dBc/Hz @10 kHz offset
−159 dBc/Hz @100 kHz offset
−158 dBc/Hz >1 MHz offset
+ 1.65 VCC V
EE
V
EE
− 0.2 V
CC
= −40°C to +85°C
T
A
(±1.7 V between input pins)
= 85°C to 125°C
T
A
(±1.4 V between input pins)
− 0.55 VCC − 0.40 VCC − 0.25 V
CC
− 2.75 VCC − 2.35 VCC − 1.9 V
CC
>1.1 V differential output swing,
= 3.3 V ± 10%
V
CC
= 3.3 V ± 10%,V
V
CC
V
= 1.6 V p-p
ID
= 1.6 V p-p
ID
ICM
= V
ICM
,
REF
= 1.85 V
Rev. A | Page 3 of 12
ADCLK914
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Parameter Symbol Min Typ Max Unit Test Conditions/Comments
122.88 MHz −150 dBc/Hz @10 Hz offset
−156 dBc/Hz @100 Hz offset
−160 dBc/Hz @1 kHz offset
−161 dBc/Hz @10 kHz offset
−161 dBc/Hz @100 kHz offset
−160 dBc/Hz >1 MHz offset
POWER SUPPLY
Supply Voltage Requirement VCC 2.97 3.63 V
Power Supply Current
Negative Supply Current I
Positive Supply Current I
Power Supply Rejection
2
Output Swing Supply Rejection3 −15 dB VCC = 3.3 V ± 10%
1
Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate.
2
Change in tPD per change in VCC.
3
Change in output swing per change in VCC.
66 111 150 mA Includes output current
VEE
34 55 73 mA
VCC
PSR
13 ps/V VCC = 3.3 V ± 10%
VCC
Rev. A | Page 4 of 12
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