Analog Devices ADC912AFS, ADC912AFP Datasheet

CMOS Microprocessor-Compatible

a

FEATURES Low Cost Low Transition Noise between Code 12-Bit Accurate

ⴞ1/2 LSB Nonlinearity Error over Temperature

No Missing Codes at All Temperatures 10 ␮s Conversion Time Internal or External Clock 8- or 16-Bit Data Bus Compatible Improved ESD Resistant Design Latchup Resistant Epi-CMOS Processing Low 95 mW Power Consumption Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC

APPLICATIONS Data Acquisition Systems DSP System Front End Process Control Systems Portable Instrumentation

GENERAL DESCRIPTION

The ADC912A is a monolithic 12-bit accurate CMOS A/D converter. It contains a complete successive-approximation A/D converter built with a high-accuracy D/A converter, a precision bipolar transistor high-speed comparator, and successiveapproximation logic including three-state bus interface for logic compatibility. The accuracy of the ADC912A results from the addition of precision bipolar transistors to Analog Devices’ advanced-oxide isolated silicon-gate CMOS process. Particular attention was paid to the reduction of transition noise between adjacent codes achieving a 1/6 LSB uncertainty. The low noise design produces the same digital output for dc analog inputs

12-Bit A/D Converter

ADC912A

FUNCTIONAL BLOCK DIAGRAM

V

AGND

REFIN

12-BIT DAC

ADC912A

MULTIPLEXER

THREE-STATE

OUTPUT

DRIVERS

D

11

12-BIT LATCH

8

SUCCESSIVE

APPROXIMATION

REGISTER

48

8

THREE-STATE

OUTPUT

DRIVERS

D

D4DGND D

7

3/11D0/8

not located at a transition voltage, see Figures 1 and 2. NPN digital output transistors provide excellent bus interface timing, 125 ns access and bus disconnect time which results in faster data transfer without the need for wait states. An external

1.25 MHz clock provides a 10 µs conversion time.

In stand-alone applications an internal clock can be used with external crystal.

An external negative five-volt reference sets the 0 V to 10 V input range. Plus 5 V and minus 12 V power supplies result in 95 mW of total power consumption.

A

IN

5k⍀

CONTROL

LOGIC

CLOCK

OSCILLATOR

V

DD

V

SS

BUSY

CS

RD

HBEN

CLK OUT

CLK IN

256

256 SUCCESSIVE

CONVERSIONS

192

128

64

NUMBER OF OCCURRENCES

0

2045 2049204820472046

OUTPUT CODE – Decimal

= 4.99756V

A

IN

WITH

Figure 1. Code Repetition

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

100

90

DIGITAL OUTPUT

10

0%

TRANSITION NOISE

ANALOG INPUT

Figure 2. Transition Noise Cross Plot

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

ADC912A–SPECIFICATIONS

10 V; External f

= 1.25 MHz; –40ⴗC to +85ⴗC applies to ADC912A/F unless otherwise noted.)

CLK

(VDD = +5 V ⴞ 5%, VSS = –11.4 V to –15.75 V, V

= –5 V, Analog Input O V to

REFIN

Parameter Symbol Conditions Min Typ Max Unit

STATIC ACCURACY

Integral Nonlinearity INL –1 +1 LSB Differential Nonlinearity DNL –1 +1 LSB Offset Error V Gain Error G Full-Scale Tempco

1

ZSE

FSE

TCG

FS

VDD = +5 V, VSS = –12 V –5 +5 LSB VDD = +5 V, VSS = –12 V –6 +6 LSB

5 15 ppm/°C

ANALOG INPUT

Input Voltage Range V Input Current Range I

IN

POWER SUPPLIES

Positive Supply Current I Negative Supply Current I Power Consumption P

DD

SS

DISS

Power Supply Rejection Ratio PSRR+ ∆V

VDD = +5 V VSS = –12 V VDD = +5 V2, VSS = –12 V

DD

2

= ± 5%, AIN = 10 V 1/2 4 LSB

010V 03mA

57mA 35mA 70 95 mW

PSRR– ∆VSS = ± 5%, AIN = 10 V 1/2 4 LSB

DIGITAL INPUTS

Logic Input High Voltage V Logic Input Low Voltage V Logic Input Current I Digital Input Capacitance C

INH

INL

IN

CS, RD, HBEN 2.4 V CS, RD, HBEN 0.8 V CS, RD, HBEN ± 1 µA

Digital Inputs, CS, RD, HBEN, CLKIN 7 10 pF

DIGITAL OUTPUTS

Logic Input High Voltage V Logic Input Low Voltage V Three-State Output Leakage I Digital Input Capacitance C

OH

OL

OZ

OUT

DYNAMIC PERFORMANCE

Conversion Time TC f

I

= 0.2 mA 4 V

SOURCE

I

= 1.6 mA 0.4 V

SINK

D11–D

0/8

D11–D

CLK

1

0/8

= 1.25 MHz

815pF

3

10 µA

Synchronous Clock 10.4 µs Asynchronous Clock 10.4 11.2 µs

NOTES

1

Guaranteed by design.

2

Converter inactive; CS, RD = High, AIN = 10 V.

3

See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 °C. See Typical Performance Characteristics for additional information.

Specifications subject to change without notice.

5V

OH

TO V

3k⍀

C

L

DGND

OL

(t3)

(t6)

DBN

A. HIGH-Z TO V

AND V

3k⍀

DGND

OL

TO V

OH

C

(t3)

L

(t6)

DBN

B. HIGH-Z TO V

AND V

Figure 3. Load Circuits for Access Time

–2–

5V

TO HIGH-Z

OL

3k⍀

10pF

DGND

DBN

A. V

3k⍀

DGND

TO HIGH-Z

OH

10pF

DBN

B. V

Figure 4. Load Circuits for Output Float Delay

REV. B

ADC912A

CS

RD

BUSY

DATA

t

1

t

2

t

3

t

7

t

3

t

7

t

CONV

t

5

t

1

t

2

t

CONV

t

5

t

4

NEW DATA DB

11

– DB0

OLD DATA

DB

11

– DB

0

DATA

OUTPUTS

D

11D10D9D8D7D6D5D4D3/11D2/10D1/9D0/8

DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB

0

FIRST READ

(OLD DATA)

SECOND

READ

DB

11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0

t

4

DATA

OUTPUTS

D

7D6D5D4D3/11D2/10D1/9D0/8

FIRST READ

(OLD DATA)

DB

7DB6DB5

DB4DB3DB2DB1DB

0

SECOND READ

LOW

LOW LOW

LOW

DB

11

DB10DB

9DB8

THIRD READ

DB

7DB6DB5

DB4DB3DB2DB1DB

0

t

8

t

1

t

2

t

3

t

7

t

4

t

9

t

5

t

8

t

1

t

3

t

4

t

9

t

10

t

3

t

7

t

2

t

4

t

1

t

5

t

8

t

9

t

7

t

5

CS

RD

BUSY

DATA

HBEN

NEW DATA DB

7

– DB0

NEW DATA

DB

11

– DB8

OLD DATA DB

7

– DB0

t

CONV

1, 2

TIMING CHARACTERISTICS

External f

= 1.25 MHz; –40ⴗC to +85ⴗC applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)

CLK

(VDD = +5 V ⴞ 5%, VSS = –11.4 V to –15.75 V, V

Parameter Symbol Conditions Min Typ Max Unit

CS to RD Setup Time t RD to BUSY Propagation Delay t

Data Access Time after READ t Read Pulsewidth t CS to RD Hold Time t New Data Valid after BUSY t Bus Disconnect Time t HBEN to RD Setup Time t HBEN to RD Hold Time t Delay between Successive Read Operations t

NOTES

1

Guaranteed by design.

2

All input control signals are specified with tR = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

3

t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.

4

t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.

Specifications subject to change without notice.

1

2

3

4

5

3

6

7

8

9

10

CL = 100 pF 65 125 ns

CL = 100 pF –30 0 ns

TIMING DIAGRAMS

CS

t

1

0

RD

BUSY

DATA

OUTPUTS

t

1

t

2

t

CONV

t

3

OLD DATA

DB

DATA

D

11D10D9D8D7D6D5D4D3/11D2/10D1/9D0/8

DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB

READ

t

6

– DB

11

0

NEW DATA

DB

– DB

11

t

5

t

10

t

7

0

= –5 V, Analog Input 0 V to 10 V;

REFIN

0ns

150 ns

90 ns 0ns

20 60 90 ns 20 ns 20 ns 350 250 ns

Figure 5. Parallel Read Timing Diagram, Slow-Memory Mode (HBEN = LOW)

HBEN

t

10

11

8

t

1

DB10DB

t

3

NEW DATA DB

t

8

CS

t

1

DATA

OUTPUTS

t

2

t

3

t

CONV

OLD DATA

– DB0

DB

7

LOW LOW

D

7D6D5D4D3/11D2/10D1/9D0/8

DB7DB6DB5DB4DB3DB2DB1DB

LOW

RD

BUSY

DATA

FIRST READ

SECOND READ

Figure 6. Two-Byte Read Timing Diagram, Slow-Memory Mode

REV. B

t

6

NEW DATA DB7 – DB0

LOW

t

9

t

5

t

7

DB

t

4

– DB8

11

9DB8

Figure 7. Parallel Read Timing Diagram, ROM Mode (HBEN = LOW)

t

9

t

5

t

7

0

Figure 8. Two-Byte Read Timing Diagram, ROM Mode

–3–

ADC912A

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted)

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

V

SS

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to V

REFIN

DD

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V

A

IN

Digital Input Voltage to DGND,

Pins 17, 19–21 . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

Operating Temperature Range

Extended Industrial: ADC912A/F . . . . . . . –40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

max–TA)/θ

J

Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C

Digital Output Voltage to DGND,

Pins 4–11, 13–16, 18, 22 . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

ORDERING GUIDE

Temperature INL Package

Model Range (LSB) Package Description Option

ADC912AFP –40°C to +85°C ±1 24-Lead Narrow-Body Plastic N-24 ADC912AFS –40°C to +85°C ± 1 24-Lead Wide-Body SOIC R-24

Table I. Analog Input to Digital Output Code Conversion

Analog Input Voltage Output Code* 0 V to 10 V –10 V to +10 V DB11 (MSB) DB0 (LSB)

+FS – 1 LSB 9.9976 9.99951 1111 1111 1111 +FS – 1 1/2 LSB 9.9964 9.9927 1111 1111 1111φ

Midscale + 1/2 LSB 5.0012 0.0024 1000 0000 000φ Midscale 5.0000 0.0000 1000 0000 0000

–FS + 1/2 LSB 0.0012 –9.9976 0000 0000 000φ –FS 0.0000 –10.000 0000 0000 0000

*The symbol”φ” indicates a 0 or 1 with equal probability.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

ADC912A

WAFER TEST LIMITS

(@ VDD = +5 V, VSS = –12 V or –15 V, V

= –5 V, AIN = 0 V to 10 V, and TA = 25ⴗC, unless otherwise noted.)

REF

ADC912AG

Parameter Symbol Conditions Limit Unit

Integral Nonlinearity INL ± 1 LSB max Differential Nonlinearity DNL ± 1 LSB max Offset Error V Gain Error G Analog Input Resistance R Logic Input High Voltage V Logic Input Low Voltage V Logic Input Current I Logic Output High Voltage V Logic Output Low Voltage V Positive Supply Current I Negative Supply Current I

ZSE

FSE

AIN

INH

INL

IN

OH

OL

DD

SS

NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

R = 10⍀ C1 = 0.01␮F C2 = 4.7␮F NC = NO CONNECT

POWER SUPPLY SEQUENCE: +5V, –15V, –5V, +10V

Guaranteed by Design ± 8 LSB max

± 8 LSB max 4/6 kΩ min/max

CS, RD, HBEN 2.4 V min CS, RD, HBEN 0.8 V max CS, RD, HBEN ± 1 µA max

I

= 0.2 mA 4 V min

SOURCE

I

= 1.6 mA 0.4 V max

SINK

VDD = +5 V, CS = RD = VDD, AIN = +10 V 7 mA max VSS = –12 V, CS = RD = VDD, AIN = +10 V 5 mA max

10V

–5V

R

+

C1

C2

1

R

2

C2

3

+

4

5

ADC912A

TOP VIEW

6

(Not to Scale)

7

NC

8

9

10

11

12

R

C1

24

R

23

C1

22

NC

21

R

20

R

19

18

NC

R

17

16

NC

15

NC

14

NC

13

NC

+5V

+

C2

–15V

C2

+

REV. B

Figure 9. Burn-In Circuit

–5–