ANALOG DEVICES ADAU1966 Service Manual

16-Channel High Performance

Differential Output, 192 kHz, 24-Bit DAC

FEATURES

118 dB DAC dynamic range and SNR

−98 dB THD + N Differential voltage DAC output

2.5 V digital and 3.3 V or 5 V analog and IO supplies 299 mW total (19 mW/channel) quiescent power at AVDD = 3.3 V PLL generated or direct MCLK master clock Low EMI design Linear regulator driver to generate digital supply Supports 24-bit and 32 kHz to 192 kHz sample rates Low propagation 192 kHz sample rate mode Log volume control with autoramp function Temperature sensor with digital readout ±3°C accuracy SPI and I Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes with up to 16-channel input/output 80-lead LQFP package Qualified for automotive applications

APPLICATIONS

Automotive audio systems Home theater systems Digital audio effects processors

2

C controllable for flexibility

2

S, and TDM modes

ADAU1966

GENERAL DESCRIPTION

The ADAU1966 is a high performance, single-chip DAC that provides 16 digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI/I allowing a microcontroller to adjust volume and many other parameters. The ADAU1966 operates from 2.5 V digital and

3.3 V or 5 V analog supplies. A linear regulator is included to generate the digital supply voltage from the analog supply voltage. The ADAU1966 is available in an 80-lead LQFP package.

The ADAU1966 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock from an external LRCLK, the ADAU1966 can eliminate the need for a separate high frequency master clock and can be used with or without a bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 2.5 V digital supplies, power consumption is minimized, and the digital waveforms are a smaller amplitude, further reducing emissions.

2

C port is included,

FUNCTIONAL BLOCK DIAGRAM

DIGIT AL AUDIO

ADAU1966

DAC

DIFFERENTIAL

ANALOG

AUDIO

OUTPUTS

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DAC

PRECISION

VOLTAGE

REFERENCE

DIGIT AL

FILTER

AND

VOLUME

CONTROL

SERIAL DAT A PORT

SDATA

IN

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PL L)

CONTROL PORT

CONTROL DATA

INPUT/OUTPUT

INPUT

CLOCKS

SPI/I2C

Figure 1.

DAC

SDATA

IN

DIGIT AL

FILTER

AND

VOLUME

CONTROL

DAC

INTERNAL

TEMP

SENSOR

DIFFERENTIAL ANALOG AUDIO OUTPUTS

09434-001

ADAU1966

REVISION HISTORY

9/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

ADAU1966

SPECIFICATIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Master clock = 12.288 MHz (48 kHz f width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input voltage high = 2.0 V, input voltage low = 0.8 V, unless otherwise noted.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V, ambient temperature

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 105 115.5 dB

With A-Weighted Filter (RMS) 108 118 dB Total Harmonic Distortion + Noise 0 dBFS −90 dB Two channels running, −1 dBFS −98 dB 16 channels running, −1 dBFS −98 −85 dB Full-Scale Differential Output Voltage AVDDx = 5.0 V 3.00 (±8.49) V rms (V p-p) Gain Error −10 +10 % Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95.25 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE VOLTAGES

Temperature Sensor Reference Voltage TS_REF pin, AVDDx = 5.0 V 1.50 V Common-Mode Reference Output CM pin, AVDDx = 5.0 V 2.14 2.25 2.29 V External Reference Voltage Source CM pin, AVDDx = 5.0 V 2.25 V

TEMPERATURE SENSOR

Temperature Accuracy −3 +3 °C Temperature Readout Range −60 +140 °C Temperature Readout Step Size 1 °C Temperature Sample Rate 0.25 6 Hz

REGULATOR

Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V Regulated Output Voltage VSENSE pin 2.26 2.50 2.59 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

1

(TA) = 25°C, unless otherwise noted.

, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word

S

Rev. 0 | Page 3 of 52

ADAU1966

Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V, ambient temperature

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 109 113.5 dB

With A-Weighted Filter (RMS) 110.5 116 dB Total Harmonic Distortion + Noise 0 dBFS −85 dB Two channels running −92.5 dB Eight channels running −92.5 −85 dB Full-Scale Differential Output Voltage AVDDx = 5.0 V 3.00 (±8.49) V rms (V p-p) Gain Error −10 +10 % Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95.25 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Temperature Sensor Reference Voltage TS_REF pin, AVDDx = 5.0 V 1.50 V Common-Mode Reference Output CM pin, AVDDx = 5.0 V 2.14 2.25 2.29 V External Reference Voltage Source CM pin, AVDDx = 5.0 V 2.25 V

REGULATOR

Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V Regulated Output Voltage VSENSE pin 2.25 2.50 2.55 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V, ambient temperature

1

(TA) = 105°C, unless otherwise noted.

1

(TA) = 25°C, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 109 111 dB

With A-Weighted Filter (RMS) 111.5 113.5 dB Total Harmonic Distortion + Noise 0 dBFS −90 dB Two channels running −97 dB Eight channels running −97 −85 dB Full-Scale Differential Output Voltage AVDDx = 3.3 V 2.00 (±5.66) V rms (V p-p) Gain Error −10 +10 % Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95.25 dB De-Emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

Rev. 0 | Page 4 of 52

ADAU1966

Parameter Test Conditions/Comments Min Typ Max Unit

REFERENCE

Temperature Sensor Reference Voltage TS_REF pin, AVDDx = 3.3 V 1.50 V Common-Mode Reference Output CM pin, AVDDx = 3.3 V 1.43 1.50 1.56 V External Reference Voltage Source CM pin, AVDDx = 3.3 V 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V Regulated Output Voltage VSENSE pin 2.26 2.50 2.59 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,

ambient temperature

Table 4.

Parameter Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 108 109 dB

With A-Weighted Filter (RMS) 110 112 dB Total Harmonic Distortion + Noise 0 dBFS −85 dB Two channels running −92 dB Eight channels running −92 −83 dB Full-Scale Differential Output Voltage AVDDx = 3.3 V 2.00 (5.66) V rms (V p-p) Gain Error −10 +10 % Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95.25 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Temperature Sensor Reference Voltage TS_REF pin, AVDDx = 3.3 V 1.50 V Common-Mode Reference Output CM pin, AVDDx = 3.3 V 1.43 1.50 1.56 V External Reference Voltage Source CM pin, AVDDx = 3.3 V 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V Regulated Output Voltage VSENSE pin 2.25 2.50 2.55 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

1

(TA) = 105°C, unless otherwise noted.

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit

Transconductance, TA = 25°C 6.4 7 to 10 14 mmhos Transconductance, TA = 105°C 5.2 7.5 to 8.5 12 mmhos

Rev. 0 | Page 5 of 52

ADAU1966

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +105°C, IOVDD = 5.0 V and 3.3 V ± 10%.

Table 6.

Parameter Test Conditions/Comments Min Typ Max Unit

High Level Input Voltage (VIH) IOVDD = 5.0 V 3.7 V IOVDD = 3.3 V 2.5 V Low Level Input Voltage (VIL) IOVDD = 5.0 V 1.3 V IOVDD = 3.3 V 0.8 V Input Leakage IIH at VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA IOVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

POWER SUPPLY SPECIFICATIONS

Table 7.

Parameter Test Conditions/Comments Min Typ Max Unit

SUPPLIES

Voltage AVDD 3.0 5.0 5.5 V DVDD 2.25 2.5 3.6 V PLLVDD 2.25 2.5 3.6 V IOVDD 3.0 5.0 5.5 V VSUPPLY 3.0 5.0 5.5 V Analog Current—AVDD = 5.0 V

Normal Operation 82 mA Power-Down 1 μA

Analog Current—AVDD = 3.3 V

Normal Operation 60 mA Power-Down 1 μA

Digital Current—DVDD = 2.5 V

Normal Operation fS = 48 kHz to 192 kHz 30 mA Power-Down No MCLK or I2S 4 μA

PLL Current—PLLVDD = 2.5 V

Normal Operation fS = 48 kHz to 192 kHz 5 mA Power-Down 1 μA

IO Current—IOVDD = 3.3 V

Normal Operation 4 mA Power-Down 1 μA

QUIESCENT DISSIPATION—DITHER INPUT

Operation MCLK = 256 × fS, 48 kHz

All Supplies AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V 511 mW All Supplies AVDDx = 3.3 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V 299 mW Analog Supply AVDDx = 5.0 V 410 mW Analog Supply AVDDx = 3.3 V 198 mW Digital Supply DVDD = 2.5 V 75 mW PLL Supply PLLVDD= 2.5 V 13 mW I/O Supply IOVDD = 3.3 V 13 mW

Power-Down, All Supplies 0 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 85 dB

20 kHz, 200 mV p-p 85 dB

at VIL = 0.8 V 10 μA

IL

Rev. 0 | Page 6 of 52

ADAU1966

DIGITAL FILTERS

Table 8.

Parameter Mode Factor Min Typ Max Unit

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typical at 48 kHz 0.4535 × fS 22 kHz 96 kHz mode, typical at 96 kHz 0.3646 × fS 35 kHz 192 kHz mode, typical at 192 kHz 0.3646 × fS 70 kHz Pass-Band Ripple 48 kHz mode, typical at 48 kHz ±0.01 dB 96 kHz mode, typical at 96 kHz ±0.05 dB 192 kHz mode, typical at 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical at 48 kHz 0.5 × fS 24 kHz 96 kHz mode, typical at 96 kHz 0.5 × fS 48 kHz 192 kHz mode, typical at 192 kHz 0.5 × fS 96 kHz Stop Band 48 kHz mode, typical at 48 kHz 0.5465 × fS 26 kHz 96 kHz mode, typical at 96 kHz 0.6354 × fS 61 kHz 192 kHz mode, typical at 192 kHz 0.6354 × fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical at 48 kHz 68 dB 96 kHz mode, typical at 96 kHz 68 dB 192 kHz mode, typical at 192 kHz 68 dB Propagation Delay 48 kHz mode, typical at 48 kHz 25/fS 521 μs

96 kHz mode, typical at 96 kHz 11/fS 115 μs 192 kHz mode, typical at 192 kHz 8/fS 42 μs 192 kHz low delay mode, typical at 192 kHz 2/fS 10 μs

TIMING SPECIFICATIONS

−40°C < TA < +105°C, DVDD = 2.5 V ± 10%.

Table 9.

Parameter Description Min Typ Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH

MCLK duty cycle, DAC clock source = PLL clock at

, 384 × fS, 512 × fS, and 768 × fS

256 × f

S

DAC clock source = direct MCLK at 512 × f

(bypass

S

on-chip PLL)

f

MCLKI frequency, PLL mode 6.9 40.5 MHz

MCLK

f

Direct MCLK 512 × fS mode 27.1 MHz

MCLK

f

DBCLK frequency, PLL mode 27.0 MHz

BCLK

t

Low 15 ns

PDR

t

Recovery, reset to active output 300 ms

PDRR

PLL

Lock Time MCLK input 10 ms Lock Time DLRCLK input 50 ms 256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin 40 60 %

SPI PORT See Figure 14

t

CCLK high 35 ns

CCH

t

CCLK low 35 ns

CCL

f

CCLK frequency, f

CCLK

t

CDATA setup, time to CCLK rising 10 ns

CDS

t

CDATA hold, time from CCLK rising 10 ns

CDH

t

CLS

t

CLH

t

CLHIGH

setup, time to CCLK rising

CLATCH

hold, time from CCLK falling

CLATCH

high, not shown in Figure 14

CLATCH

CCLK

= 1/t

CCP

; only t

shown in Figure 14 10 MHz

CCP

40 60 %

10 ns 10 ns 10 ns

Rev. 0 | Page 7 of 52

ADAU1966

Parameter Description Min Typ Max Unit

t

COUT enable from CCLK falling 30 ns

COE

t

COUT delay from CCLK falling 30 ns

COD

t

COUT hold from CCLK falling, not shown in Figure 14 30 ns

COH

t

COUT tristate from CCLK falling 30 ns

COTS

I2C See Figure 2 and Figure 13

f

SCL clock frequency 400 kHz

SCL

t

SCL low 1.3 μs

SCLL

t

SCL high 0.6 μs

SCLH

t

SCS

Setup time (start condition), relevant for repeated start condition

t

SCH

Hold time (start condition), first clock generated after this period

t

Setup time (stop condition) 0.6 μs

SSH

tDS Data setup time 100 ns tSR SDA and SCL rise time 300 ns tSF SDA and SCL fall time 300 ns t

Bus-free time between stop and start 1.3 μs

BFT

DAC SERIAL PORT See Figure 16

t

DBCLK high, slave mode 10 ns

DBH

t

DBCLK low, slave mode 10 ns

DBL

t

DLRCLK setup, time to DBCLK rising, slave mode 10 ns

DLS

t

DLRCLK hold from DBCLK rising, slave mode 5 ns

DLH

t

DLRCLK skew from DBCLK falling, master mode −8 +8 ns

DLS

t

DSDATAx setup to DBCLK rising 10 ns

DDS

t

DSDATAx hold from DBCLK rising 5 ns

DDH

t

SCLH

DS

t

SCH

SDA

t

SCH

t

SR

0.6 μs

SCL

t

SCLL

t

SF

Figure 2. I

2

C Timing Diagram

Rev. 0 | Page 8 of 52

t

SCS

t

BFT

09434-002

ADAU1966

ABSOLUTE MAXIMUM RATINGS

Table 10.

Parameter Rating

Analog (AVDD) −0.3 V to +5.5 V I/O (IOVDD) −0.3 V to +5.5 V Digital (DVDD) −0.3 V to +3.6 V PLL (PLLVDD) −0.3 V to +3.6 V VSUPPLY −0.3 V to +6.0 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents junction-to-ambient thermal resistance; θ sents the junction-to-case thermal resistance. All characteristics are for a 4-layer board with a solid ground plane.

Table 11. Thermal Resistance

Package Type θ

80-Lead LQFP 42.3 10.0 °C/W

JA

θ

JC

Unit

repre-

ESD CAUTION

Rev. 0 | Page 9 of 52

ADAU1966

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND3

DAC12N

DAC12P

DAC11N

DAC11P

DAC10N

DAC10P

DAC9N

DAC9P

DAC8N

DAC8P

DAC7N

DAC7P

DAC6N

DAC6P

DAC5N

DAC5P

TS_REFCMAGND2

6162636465666768697071727374757677787980

DAC_BIAS3

DAC_BIAS4

AVDD3

DAC13P

DAC13N

DAC14P

DAC14N

DAC15P

DAC15N

DAC16P

DAC16N

AVDD4

AGND4

PLLGND

PLLVDD

MCLKI/XTALI

XTALO

MCLKO

DVDD

1

PIN 1 INDICATOR

2

3

4

5

6

7

8

9

10

11

12

13

14

15

LF

16

17

18

19

20

ADAU1966

TOP VIEW

(Not to Scale)

60

DAC_BIAS2

59

DAC_BIAS1

58

AVDD2

57

DAC4N

56

DAC4P

55

DAC3N

54

DAC3P

53

DAC2N

52

DAC2P

51

DAC1N

50

DAC1P

49

AVDD1

48

AGND1

47

PU/RST

46

SA_MODE

45

CLATCH/ADDR0/ SA*

44

CCLK/SCL/SA*

43

COUT/SDA/ SA*

42

CDATA/ADDR1/SA*

41

DVDD

4039383736353433323130292827262524232221

DGND

IOVDD

VDRIVE

VSENSE

VSUPPLY

*SEE TABLE 15 FOR SA_MODE SETTINGS.

DGND

DVDD

DBCLK

DGND

DLRCLK

DSDATA6

DSDATA5

DSDATA4

DSDATA3

DSDATA2

DSDATA8/SA*

DSDATA7/SA*

DGND

IOVDD

DSDATA1

Figure 3. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Type1 Mnemonic Description

1 I DAC_BIAS3 DAC Bias 3. AC couple with 470 nF to AGND3. 2 I DAC_BIAS4 DAC Bias 4. AC couple with 470 nF to AVDD3. 3 PWR AVDD3 Analog Power. 4 O DAC13P DAC13 Positive Output. 5 O DAC13N DAC13 Negative Output. 6 O DAC14P DAC14 Positive Output. 7 O DAC14N DAC14 Negative Output. 8 O DAC15P DAC15 Positive Output. 9 O DAC15N DAC15 Negative Output. 10 O DAC16P DAC16 Positive Output. 11 O DAC16N DAC16 Negative Output. 12 PWR AVDD4 Analog Power. 13 GND AGND4 Analog Ground. 14 GND PLLGND PLL Ground. 15 O LF PLL Loop Filter, Reference to PLLVDD. 16 PWR PLLVDD Apply 2.5 V to power PLL. 17 I MCLKI/XTALI Master Clock Input, Input to Crystal Inverter. 18 O XTALO Output from Crystal Inverter. 19 O MCLKO Master Clock Output. 20, 29, 41 PWR DVDD Digital Power, 2.5 V. 21, 26, 30, 40 GND DGND Digital Ground.

9434-003

Rev. 0 | Page 10 of 52

ADAU1966

Pin No. Type1 Mnemonic Description

22, 39 PWR IOVDD Power for Digital Input and Output Pins, 3.3 V to 5 V. 23 I VSENSE

24 O VDRIVE Drive for Base of Pass Transistor. 25 I VSUPPLY

27 I/O DBCLK Bit Clock for DACs. 28 I/O DLRCLK Frame Clock for DACs. 31 I DSDATA8/SA

32 I DSDATA7/SA

33 I DSDATA6 DAC11 and DAC 12 Serial Data Input. 34 I DSDATA5 DAC9 and DAC 10 Serial Data Input. 35 I DSDATA4 DAC7 and DAC 8 Serial Data Input. 36 I DSDATA3 DAC5 and DAC 6 Serial Data Input. 37 I DSDATA2 DAC3 and DAC 4 Serial Data Input. 38 I DSDATA1 DAC1 and DAC 2 Serial Data Input. 42 I CDATA/ADDR1/SA

43 I/O COUT/SDA/SA

44 I CCLK/SCL/SA

45 I

/ADDR0/SA Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the

CLATCH

46 I SA_MODE

47 I

PU/RST 48 GND AGND1 Analog Ground. 49 PWR AVDD1 Analog Power. 50 O DAC1P DAC1 Positive Output. 51 O DAC1N DAC1 Negative Output. 52 O DAC2P DAC2 Positive Output. 53 O DAC2N DAC2 Negative Output. 54 O DAC3P DAC3 Positive Output. 55 O DAC3N DAC3 Negative Output. 56 O DAC4P DAC4 Positive Output. 57 O DAC4N DAC4 Negative Output. 58 PWR AVDD2 Analog Power. 59 I DAC_BIAS1 DAC Bias 1. AC couple with 470 nF to AVDD2. 60 I DAC_BIAS2 DAC Bias 2. AC couple with 470 nF to AGND2. 61 GND AGND2 Analog Ground. 62 O CM

63 O TS_REF

64 O DAC5P DAC5 Positive Output. 65 O DAC5N DAC5 Negative Output. 66 O DAC6P DAC6 Positive Output. 67 O DAC6N DAC6 Negative Output. 68 O DAC7P DAC7 Positive Output. 69 O DAC7N DAC7 Negative Output. 70 O DAC8P DAC8 Positive Output.

2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel with 100 nF.

5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel with 100 nF.

DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode section, Table 15, and Table 16).

DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode section, Table 15, and Table 16).

2

Control Data Input (SPI)/Address 1 (I

C)/SA_MODE State (see the Standalone Mode

section and Table 15).

2

Control Data Output (SPI)/Control Data Input (I

C)/SA_MODE State (see the

Standalone Mode section and Tabl e 15).

2

Control Clock Input (SPI)/Control Clock Input (I

C)/SA_MODE State (see the Standalone

Mode section and Table 15).

Standalone Mode section and Tabl e 15). Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,

Pin 31, and Pin 32 (high active, see Table 1 5 and Table 1 6). Power-Up/Reset (Low Active).

Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register and the pin can be driven with an outside voltage source.

Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with 100 nF to AGND2.

Rev. 0 | Page 11 of 52

ADAU1966

Pin No. Type1 Mnemonic Description

71 O DAC8N DAC8 Negative Output. 72 O DAC9P DAC9 Positive Output. 73 O DAC9N DAC9 Negative Output. 74 O DAC10P DAC10 Positive Output. 75 O DAC10N DAC10 Negative Output. 76 O DAC11P DAC11 Positive Output. 77 O DAC11N DAC11 Negative Output. 78 O DAC12P DAC12 Positive Output. 79 O DAC12N DAC12 Negative Output. 80 GND AGND3 Analog Ground.

1

I = input, O = output, I/O = input/output, PWR = power, GND = ground.

Rev. 0 | Page 12 of 52

ADAU1966

TYPICAL PERFORMANCE CHARACTERISTICS

0.05

0.04

0.03

0.02

0.01

0

–0.01

MAGNITUDE (dB)

–0.02

–0.03

–0.04

–0.05

0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (FACTORED T O

Figure 4. DAC Pass-Band Filter Response, 48 kHz

0

–10

–20

–30

–40

–50

–60

MAGNITUDE (dB)

–70

–80

–90

–100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

FREQUENCY (FACTORED TO

Figure 5. DAC Stop-Band Filter Response, 48 kHz

f

)

S

f

)

S

09434-004

09434-005

0.20

0.15

0.10

0.05

0

–0.05

MAGNITUDE (dB)

–0.10

–0.15

–0.20

0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

FREQUENCY (FACTORED T O

f

)

S

Figure 6. DAC Pass-Band Filter Response, 96 kHz

0

–10

–20

–30

–40

–50

–60

MAGNITUDE (dB)

–70

–80

–90

–100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

FREQUENCY (F ACTORED TO

f

S

Figure 7. DAC Stop-Band Filter Response, 96 kHz

)

09434-006

09434-007

Rev. 0 | Page 13 of 52

ADAU1966

F

APPLICATION CIRCUITS

Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator circuit is shown in Figure 11.

DLRCLK

LF

39nF

2.2nF

3.32kΩ

PLLVDD

Figure 8. Recommended Loop Filters for DLRCLK or MCLKI/XTALI PLL Reference Modes

2.7nF

10µF

+

10µF

+

49.9kΩ 49.9kΩ

DACP OUTP

DACN OUTN

237Ω

Figure 9. Typical DAC Output Passive Filter Circuit (Differential)

1.1n

MCLKI/XTALI

LF

5.6nF

562Ω

390pF

09434-008

09434-009

AD8672ARZ

5

6

1nF 4.7µF

2

3

422Ω

7

2.49kΩ

1

100Ω

4.7µF +

100kΩ

+

OUTPUT1P

OUTPUT1N

+12V DC

8

V+ V–

4

–12V DC

DAC1P

0.1µF

DAC1N

1.50kΩ 1.54kΩ

+

4.7µF

+

4.7µF

1.50kΩ 1.54kΩ

AD8672ARZ

1.1nF

09434-010

Figure 10. Typical DAC Output Active Filter Circuit (Differential)

100nF

VSUPPLY 5V

1kΩ

VDRIVE

VSENSE 2.5V

100nF

10µF

+

E

B

FZT953

C

+

10µF

09434-011

Figure 11. Recommended 2.5 V Regulator Circuit

Rev. 0 | Page 14 of 52

ADAU1966

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTERS (DACS)

The 16 ADAU1966 digital-to-analog converter (DAC) channels are differential for improved noise and distortion performance and are voltage output for simplified connection. The DACs include on-chip digital interpolation filters with 68 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 256× (48 kHz range), 128× (96 kHz range), or 64× (192 kHz range). Each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 dB. Digital inputs are supplied through eight serial data input pins (two channels on each pin), a common frame clock (DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the TDM modes can be used to access up to 16 channels on a single TDM data line.

The ADAU1966 has a low propagation delay mode; this mode is an option for an f CTRL0[2:1]. By setting these bits to b11, the propagation delay is reduced by the amount shown in Ta bl e 8 . The shorter delay is achieved by reducing the amount of digital filtering; the negative impact of selecting this mode is reduced audio frequency response and increased out-of-band energy.

When AVDD is supplied with 5 V, each analog output pin has a nominal common-mode (CM) dc level of 2.25 V and swings ±8.49 V p-p (3 V rms differential) from a 0 dBFS digital input signal. An AVDD of 3.3 V generates a CM dc voltage of 1.5 V and allows differential audio swings of ±5.66 V p-p (2 V rms) from a 0 dBFS digital input signal. The differential analog outputs require only a single-order passive differential RC filter to provide the specified DNR performance; see Figure 9 for an example filter. The outputs can easily drive differential inputs on a separate PCB through cabling as well as differential inputs on the same PCB.

If more signal level is required or if a more robust filter is needed, a single op amp gain stage designed as a second-order, low-pass Bessel filter can be used to remove the high frequency out-ofband noise present on each pin of the differential outputs. The choice of components and design of this circuit is critical to yield the full DNR of the DACs (see the recommended passive and active circuits in Figure 9 and Figure 10). This filter can be built into an active difference amplifier to provide a single-ended output with gain, if necessary. Note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; exercise care when selecting these components.

of 192 kHz and is enabled in Register DAC_

S

The ADAU1966 offers control over the analog performance of the DACs; it is possible to program the registers to reduce the power consumption with the trade-off of lower SNR and THD + N. The reduced power consumption is the result of changing the internal bias current to the analog output amplifiers.

Register DAC_POWER1 to Register DAC_POWER4 present four basic settings for the DAC power vs. performance in each of the 16 channels: best performance, good performance, low power, and lowest power. Alternatively, in Register PLL_CLK_ CTRL1[7:6], the LOPWR_MODE bits offer global control over the power and performance for all 16 channels. The default setting is b00. This setting allows the channels to be controlled individually using the DAC_POWERx registers. Setting b10 and Setting b11 select the low power and lowest power settings. The data presented in Tabl e 13 shows the result of setting all 16 channels to each of the four settings. The SNR and THD + N specifications are shown in relation to the measured performance of a device at the best performance setting.

The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section).

CLOCK SIGNALS

Upon powering the ADAU1966 and asserting the PU/ high, the part starts in either standalone mode (SA_MODE) or program mode, depending on the state of SA_MODE (Pin 46). The clock functionality of SA_MODE is described in the Standalone Mode ADAU1966 is for the MCLKO pin to feed a buffered output of the MCLKI signal. The default for the DLRCLK and DBCLK ports is slave mode; the DAC must be driven with a coherent set of MCLK, LRCLK, and BCLK signals to function.

The MCLKO pin can be programmed to provide different clock signals using Register Bits PLL_CLK_CTRL1[5:4]. The default, b10, provides a buffered copy of the clock signal that is driving the MCLKI pin. Two modes, b00 and b01, provide low jitter clock signals. The b00 setting yields a clock rate between 4 MHz and 6 MHz, and b01 yields a clock rate between 8 MHz and 12 MHz. Both of these clock frequencies are scaled as ratios of MCLK automatically inside the ADAU1966. As an example, an MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of (8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz and a setting of b01 yield an MCLKO frequency of (36.864/3) =

12.288 MHz. The setting b11 shuts off the MCLKO pin.

section. In program mode, the default for the

RST

Table 13. DAC Power vs. Performance

Register Setting Best Performance Good Performance Low Power Lowest Power

Total AVDD Current 82 mA 73 mA 64 mA 54 mA SNR Reference −0.2 dB −1.5 dB −14.2 dB THD + N (−1 dbFS signal) Reference −1.8 dB −3.0 dB −5.8 dB

Rev. 0 | Page 15 of 52

ADAU1966

After the PU/

RST

pin has been asserted high, the PLL_CLK_ CTRLx registers (0x00 and 0x01) can be programmed. The on-chip phase-locked loop (PLL) can be selected to use the clock appearing at the MCLKI/XTALI pin at a frequency of 256, 384, 512, or 768 times the sample rate (f

), referenced to

S

the 48 kHz mode from the master clock select (MCS) setting, as described in . In 96 kHz mode, the master clock fre-

Tabl e 14 quency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if the ADAU1966 is programmed in 256 × f

mode, the frequency

S

of the master clock input is 256 × 48 kHz = 12.288 MHz. If the ADAU1966 is then switched to 96 kHz operation (by writing to DAC_CTRL0 [2:1]), the frequency of the master clock should remain at 12.288 MHz, which is 128 × f 192 kHz mode, MCS becomes 64 × f

The internal clock for the digital core varies by mode: 512 × f (48 kHz mode), 256 × f

(96 kHz mode), or 128 × fS (192 kHz

S

in this example. In

S

.

S

mode). By default, the on-board PLL generates this internal master clock from an external clock.

The PLL should be powered and stable before the ADAU1966 is used as a source for quality audio. The PLL is enabled by reset and does not require writing to the I

2

C or SPI port for normal

operation.

With the PLL enabled, the performance of the ADAU1966 is not affected by jitter as high as a 300 ps rms time interval error (TIE). If the internal PLL is not used, it is best to use an independent crystal oscillator to generate the master clock.

If the ADAU1966 is to be used in direct MCLK mode, the PLL can be powered down in the PDN_THRMSENS_CTRL_1 register. For direct MCLK mode, a 512 × f

(referenced to 48 kHz

S

mode) master clock must be used as MCLK, and the CLK_SEL bit in the PLL_CLK_CTRL1 register must be set to b1.

The ADAU1966 PLL can also be programmed to run from an external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0 register are set to 01 and the appropriate loop filter is connected to the LF pin (see Figure 8), the ADAU1966 PLL generates all of the necessary internal clocks for operation with no external MCLK. This mode reduces the number of high frequency signals in the design, reducing EMI emissions.

It is possible to further reduce EMI emissions of the circuit by using the internal DBCLK generation setting of the BCLK_GEN

bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966 generate its own DBCLK; this works with the PLL input set to either MCLKI/XTALI or DLRCLK. DLRCLK is the only required clock in DLRCLK PLL mode.

POWER-UP AND RST

Power sequencing for the ADAU1966 should start with AVDD and IOVDD, followed by DVDD. It is very important that AVDD be settled at a regulated voltage and that IOVDD be within 10% of regulated voltage before applying DVDD. When using the ADAU1966 internal regulator, this timing occurs by default.

To guarantee proper startup, the PU/ low by an external resistor and then driven high after the power supplies have stabilized. The PU/ using a simple RC network.

RST

Driving the PU/

pin low puts the part into a very low power

state (<3 μA). All functionality of the ADAU1966 is disabled

RST

until the PU/

pin is asserted high. Once this pin is asserted high, the ADAU1966 requires 300 ms to stabilize. The MMUTE bit in the DAC_CTRL0 register must be toggled for operation.

The PUP bit in the PLL_CLK_CTRL0 register can be used to power down the ADAU1966. Engaging the master power-down puts the ADAU1966 in an idle state while maintaining the settings of all registers. Additionally, the power-down bits in the PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and VREG_PDN) can be used to power down individual sections of the ADAU1966.

The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of the control registers to their default settings while maintaining the internal clocks in default mode. The SOFT_RST bit does not power down the analog outputs; toggling this bit does not cause audible popping sounds at the differential analog outputs.

Proper startup of the ADAU1966 should proceed as follows:

1. Apply power to the ADAU1966 as described previously.

2. Assert the PU/

RST

pin high after power supplies have

stabilized.

3. Set the PUP bit to b1.

4. Program all necessary registers for the desired settings.

5. Set the MMUTE bit to b0 to unmute all channels.

RST

pin should be pulled

RST

can also be pulled high

Rev. 0 | Page 16 of 52

ANALOG DEVICES ADAU1966 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION CIRCUITS

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTERS (DACS)

CLOCK SIGNALS