ANALOG DEVICES ADAU1401A Service Manual
SigmaDSP 28-/56-Bit Audio Processor
A
G
FEATURES
28-/56-bit, 50 MIPS digital audio processor
2 ADCs: SNR of 100 dB, THD + N of −83 dB
4 DACs: SNR of 104 dB, THD + N of −90 dB
Complete standalone operation
Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
GPIOs for digital controls and outputs
Fully programmable with SigmaStudio graphical tool
28-bit × 28-bit multiplier with 56-bit accumulator for full
double-precision processing
Clock oscillator for generating master clock from crystal
PLL for generating master clock from 64 × f
384 × f
, or 512 × fS clocks
S
Flexible serial data input/output ports with I
left-justified, right-justified, and TDM modes
Sampling rates of up to 192 kHz supported
On-chip voltage regulator for compatibility with 3.3 V systems
48-lead, plastic LQFP
Qualified for automotive applications
APPLICATIONS
Multimedia speaker systems
MP3 player speaker docks
Automotive head units
Minicomponent stereos
Digital televisions
Studio monitors
Speaker crossovers
Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
, 256 × fS,
S
2
S-compatible,
with Two ADCs and Four DACs
ADAU1401A
GENERAL DESCRIPTION
The ADAU1401A is a complete, single-chip audio system with
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay
compensation, speaker compensation, and stereo image widening.
This processing can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, providing
dramatic improvements in perceived audio quality.
The signal processing of the ADAU1401A is comparable to that
found in high end studio equipment. Most processing is done in
full 56-bit, double-precision mode, resulting in very good low
level signal performance. The ADAU1401A is a fully programmable DSP. The easy to use SigmaStudio™ software allows the
user to graphically configure a custom signal processing flow
using blocks such as biquad filters, dynamics processors, level
controls, and GPIO interface controls.
The ADAU1401A programs can be loaded on power-up either
from a serial EEPROM through its own self-boot mechanism or
from an external microcontroller. On power-down, the current
state of the parameters can be written back to the EEPROM from
the ADAU1401A to be recalled the next time the program is run.
Two Σ- ADCs and four Σ- DACs provide a 98.5 dB analog
input to analog output dynamic. Each ADC has a THD + N of
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
and output ports allow a glueless connection to additional ADCs
and DACs. The ADAU1401A communicates through an I
or a 4-wire SPI port.
2
C® bus
FUNCTIONAL BLOCK DIAGRAM
DIGITAL VDD DIGITAL GROUNDANALOG VDD
3.3V
3 3 3
1.8V
2-CHANNEL
ANALOG
INPUT
FILTA/
ADC_RES
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
REGULATOR
2
RESET/
MODE
SELECT
RESET SEL F-BOOT DIGITAL IN OR GPIO AUX ADC OR GPIO DIGITAL OUT OR GP IO
STEREO
ADC
CONTROL I NTERFACE
AND SELF-BOOT
2
C/SPI AND WRITEBACK
I
ADAU1401A
AUDIO PROCESSOR CORE, 40ms DELAY MEMORY
NALO
GROUND
28-/56-BIT, 50MIPS
8-CHANNEL
DIGITAL INPUT
Figure 1.
PLL MODE
2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
PLL LOOP
FILTER
3
PLL CLOCK OS CILLATO R
8-BIT AUX
ADC
GPIO
INPUT/OUTPUT MATRIX
CRYSTAL
2
DAC
DAC
8-CHANNEL
DIGITAL OUTPUT
3335
FILTD/CM
2
4-CHANNEL
ANALOG
OUTPUT
08506-001
ADAU1401A
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance .................................................................... 4
Digital Input/Output.................................................................... 5
Power.............................................................................................. 6
Temperature Range ...................................................................... 6
PLL and Oscillator........................................................................ 6
Regulator........................................................................................ 6
Digital Timing Specifications ..................................................... 7
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 14
System Block Diagram................................................................... 15
Theory of Operation ...................................................................... 16
Initialization .................................................................................... 17
Power-Up Sequence ................................................................... 17
Control Registers Setup............................................................. 17
Recommended Program/Parameter Loading Procedure .....17
Power Reduction Modes............................................................ 17
Using the Oscillator.................................................................... 18
Setting Master Clock/PLL Mode.............................................. 18
Voltage Regulator ....................................................................... 19
Audio ADCs.................................................................................... 20
Audio DACs ....................................................................................21
Control Ports................................................................................... 22
I2C Port ........................................................................................ 23
SPI Port........................................................................................ 26
Self-Boot ...................................................................................... 27
Signal Processing ............................................................................ 29
Numeric Formats........................................................................ 29
Programming.............................................................................. 29
RAMs and Registers ....................................................................... 30
Address Maps.............................................................................. 30
Parameter RAM.......................................................................... 30
Data RAM ................................................................................... 30
Read/Write Data Formats ......................................................... 30
Control Register Map..................................................................... 32
Control Register Details ................................................................ 34
Address 2048 to Address 2055 (0x0800 to 0x0807)—Interface
Registers....................................................................................... 34
Address 2056 (0x0808)—GPIO Pin Setting Register............ 35
Address 2057 to Address 2060 (0x0809 to 0x080C)—
Auxiliary ADC Data Registers.................................................. 36
Address 2064 to Address 2068 (0x0810 to 0x0814)—Safeload
Data Registers ............................................................................. 37
Address 2069 to Address 2073 (0x0815 to 0x0819)—Safeload
Address Registers ....................................................................... 37
Address 2074 and Address 2075 (0x081A and 0x081B)—Data
Capture Registers........................................................................ 38
Address 2076 (0x081C)—DSP Core Control Register.......... 39
Address 2078 (0x081E)—Serial Output Control Register.... 40
Address 2079 (0x081F)—Serial Input Control Register ....... 41
Address 2080 and Address 2081 (0x0820 and 0x0821)—
Multipurpose Pin Configuration Registers............................. 42
Address 2082 (0x0822)—Auxiliary ADC and Power Control
Register ........................................................................................ 43
Address 2084 (0x0824)—Auxiliary ADC Enable Register ... 43
Address 2086 (0x0826)—Oscillator Power-Down Register . 43
Address 2087 (0x0827)—DAC Setup Register....................... 43
Multipurpose Pins.......................................................................... 44
Auxiliary ADC............................................................................ 44
General-Purpose Input/Output Pins....................................... 44
Serial Data Input/Output Ports ................................................ 44
Layout Recommendations............................................................. 47
Parts Placement .......................................................................... 47
Grounding................................................................................... 47
Typical Application Schematics.................................................... 48
Self-Boot Mode........................................................................... 48
I2C Control.................................................................................. 49
SPI Control.................................................................................. 50
Outline Dimensions....................................................................... 51
Ordering Guide .......................................................................... 51
Rev. A | Page 2 of 52
ADAU1401A
REVISION HISTORY
11/10—Rev. 0 to Rev. A
Changes to Figure 7 and Table 11 .................................................11
Changes to Figure 37 ......................................................................48
Changes to Figure 38 ......................................................................49
Changes to Figure 39 ......................................................................50
4/10—Revision 0: Initial Version
Rev. A | Page 3 of 52
ADAU1401A
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.
ANALOG PERFORMANCE
Specifications are guaranteed at 25°C (ambient).
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC INPUTS
Number of Channels 2 Stereo input
Resolution 24 Bits
Full-Scale Input 100 (283) µA rms (µA p-p)
Signal-to-Noise Ratio
Dynamic Range −60 dB with respect to full-scale analog input
Total Harmonic Distortion + Noise −83 dB −3 dB with respect to full-scale analog input
Interchannel Gain Mismatch 25 300 mdB
Crosstalk −82 dB Analog channel-to-channel crosstalk
DC Bias 1.4 1.5 1.6 V
Gain Error −11 +11 %
DAC OUTPUTS
Number of Channels 4 Two stereo output channels
Resolution 24 Bits
Full-Scale Analog Output 0.9 (2.5) V rms (V p-p) Sine wave
Signal-to-Noise Ratio
Dynamic Range −60 dB with respect to full-scale analog output
Total Harmonic Distortion + Noise −90 dB −1 dB with respect to full-scale analog output
Crosstalk −100 dB Analog channel-to-channel crosstalk
Interchannel Gain Mismatch 25 250 mdB
Gain Error −10 +10 %
DC Bias 1.4 1.5 1.6 V
VOLTAGE REFERENCE
Absolute Voltage, CM Pin 1.4 1.5 1.6 V
AUXILIARY ADC
Full-Scale Analog Input 2.8 2.95 3.1 V
INL 0.5 LSB
DNL 0.5 LSB
Offset 15 mV
Input Impedance 17.8 30 42 kΩ
Specifications are guaranteed at 130°C (ambient).
A-Weighted 100 dB
A-Weighted 95 100 dB
A-Weighted 104 dB
A-Weighted 99 104 dB
2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ internal)
series resistor
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC INPUTS
Number of Channels 2 Stereo input
Resolution 24 Bits
Full-Scale Input 100 (283) µA rms (µA p-p)
2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ internal)
series resistor
Rev. A | Page 4 of 52
ADAU1401A
Parameter Min Typ Max Unit Test Conditions/Comments
Signal-to-Noise Ratio
A-Weighted 100 dB
Dynamic Range −60 dB with respect to full-scale analog input
A-Weighted 92 100 dB
Total Harmonic Distortion + Noise −83 dB −3 dB with respect to full-scale analog input
Interchannel Gain Mismatch 25 250 mdB
Crosstalk −82 dB Analog channel-to-channel crosstalk
DC Bias 1.4 1.5 1.6 V
Gain Error −11 +11 %
DAC OUTPUTS
Number of Channels 4 Two stereo output channels
Resolution 24 Bits
Full-Scale Analog Output 0.85 (2.4) V rms (V p-p) Sine wave
Signal-to-Noise Ratio
A-Weighted 104 dB
Dynamic Range −60 dB with respect to full-scale analog output
A-Weighted 98 104 dB
Total Harmonic Distortion + Noise −90 dB −1 dB with respect to full-scale analog output
Crosstalk −100 dB Analog channel-to-channel crosstalk
Interchannel Gain Mismatch 25 250 mdB
Gain Error −10 +10 %
DC Bias 1.4 1.5 1.6 V
VOLTAGE REFERENCE
Absolute Voltage, CM Pin 1.4 1.5 1.6 V
AUXILIARY ADC
Full-Scale Analog Input 2.8 2.95 3.1 V
INL 0.5 LSB
DNL 0.5 LSB
Offset 15 mV
Input Impedance 17.8 30 42 kΩ
DIGITAL INPUT/OUTPUT
Table 3.
Parameter Min Typ Max1 Unit Test Conditions/Comments
Input Voltage, High (VIH) 2.0 IOVDD V
Input Voltage, Low (VIL) 0.8 V
Input Leakage, High (IIH) 1 µA Excluding MCLKI
Input Leakage, Low (IIL) 1 µA Excluding MCLKI and bidirectional pins
Bidirectional Pin Pull-Up Current, Low 150 µA
MCLKI Input Leakage, High (IIH) 3 µA
MCLKI Input Leakage, Low (IIL) 3 µA
Output Voltage, High (VOH) 2.0 V IOH = 2 mA
Output Voltage, Low (VOL) 0.8 V IOL = 2 mA
Input Capacitance 5 pF
GPIO Output Drive 2 mA
1
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
Rev. A | Page 5 of 52
ADAU1401A
POWER
Table 4.
Parameter Min Typ Max1 Unit
SUPPLY VOLTAGE
Analog Voltage 3.3 V
Digital Voltage 1.8 V
PLL Voltage 3.3 V
IOVDD Voltage 3.3 V
SUPPLY CURRENT
Analog Current (AVDD and PVDD) 50 85 mA
Digital Current (DVDD) 25 40 mA
Analog Current, Reset 35 55 mA
Digital Current, Reset 1.5 4.5 mA
DISSIPATION
Operation (AVDD, DVDD, PVDD)2 259.5 mW
Reset, All Supplies 118 mW
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV p-p Signal at AVDD 50 dB
1
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
2
Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE
Table 5.
Parameter Min Typ Max Unit
Functionality Guaranteed −40 +105 °C ambient
PLL AND OSCILLATOR
Table 6.
Parameter1 Min Typ Max Unit
PLL Operating Range MCLK_Nom − 20% MCLK_Nom + 20% MHz
PLL Lock Time 20 ms
Crystal Oscillator Transconductance (gm) 78 mmho
1
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
REGULATOR
Table 7.
Parameter1 Min Typ Max Unit
DVDD Voltage 1.7 1.8 1.84 V
1
Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
Rev. A | Page 6 of 52
ADAU1401A
DIGITAL TIMING SPECIFICATIONS
Table 8.
Limit
Parameter1 t
MASTER CLOCK
tMP 36 244 ns MCLKI period, 512 × fS mode.
tMP 48 366 ns MCLKI period, 384 × fS mode.
tMP 73 488 ns MCLKI period, 256 × fS mode.
tMP 291 1953 ns MCLKI period, 64 × fS mode.
SERIAL PORT
t
40 ns INPUT_BCLK low pulse width.
BIL
t
40 ns INPUT_BCLK high pulse width.
BIH
t
10 ns INPUT_LRCLK setup; time to INPUT_BCLK rising.
LIS
t
10 ns INPUT_LRCLK hold; time from INPUT_BCLK rising.
LIH
t
10 ns SDATA_INx setup; time to INPUT_BCLK rising.
SIS
t
10 ns SDATA_INx hold; time from INPUT_BCLK rising.
SIH
t
10 ns OUTPUT_LRCLK setup in slave mode.
LOS
t
10 ns OUTPUT_LRCLK hold in slave mode.
LOH
tTS 5 ns OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.
t
40 ns SDATA_OUTx delay in slave mode; time from OUTPUT_BCLK falling.
SODS
t
40 ns SDATA_OUTx delay in master mode; time from OUTPUT_BCLK falling.
SODM
SPI PORT
f
CCLK
t
80 ns CCLK pulse width low.
CCPL
t
80 ns CCLK pulse width high.
CCPH
t
0 ns CLATCH setup; time to CCLK rising.
CLS
t
100 ns CLATCH hold; time from CCLK rising.
CLH
t
80 ns CLATCH pulse width high.
CLPH
t
0 ns CDATA setup; time to CCLK rising.
CDS
t
80 ns CDATA hold; time from CCLK rising.
CDH
t
101 ns COUT delay; time from CCLK falling.
COD
I2C PORT
f
SCL
t
0.6 µs SCL high.
SCLH
t
1.3 µs SCL low.
SCLL
t
0.6 µs SCL setup time, relevant for repeated start condition.
SCS
t
0.6 µs SCL hold time. After this period, the first clock is generated.
SCH
tDS 100 ns Data setup time.
t
300 ns SCL rise time.
SCR
t
300 ns SCL fall time.
SCF
t
300 ns SDA rise time.
SDR
t
300 ns SDA fall time.
SDF
t
0.6 Bus-free time; time between stop and start.
BFT
MULTIPURPOSE PINS AND RESET
t
50 ns GPIO rise time.
GRT
t
50 ns GPIO fall time.
GFT
t
1.5 × 1/fS µs GPIO input latency; time until high/low value is read by core.
GIL
t
20 ns
RLPW
1
All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 66).
t
MIN
Unit Description
MAX
6.25 MHz CCLK frequency.
400 kHz SCL frequency.
RESET
low pulse width.
Rev. A | Page 7 of 52
ADAU1401A
Digital Timing Diagrams
t
LIH
t
SIS
LSB
t
SIH
8506-002
t
CLPH
INPUT_BCLK
INPUT_LRCLK
SDATA_INx
LEFT-JUSTIFIED
RIGHT-JUSTIFIED
SDATA_INx
SDATA_INx
CLATCH
MODE
I2S MODE
MODE
t
BIH
t
BIL
t
LIS
t
SIS
MSB
t
SIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
MSB – 1
t
SIS
MSB
t
SIH
t
SIS
MSB
t
SIH
Figure 2. Serial Input Port Timing
t
CLS
t
t
CCPH
CCPL
t
CLH
CCLK
CDATA
t
CDH
t
COD
08506-004
COUT
t
CDS
Figure 3. SPI Port Timing
t
t
SCLH
t
SCF
Figure 4. I
DS
2
C Port Timing
t
SCH
t
SCS
t
BFT
08506-005
SDA
SCL
t
SCH
t
SCR
t
SCLL
Rev. A | Page 8 of 52
ADAU1401A
t
TS
OUTPUT_BCLK
t
LOS
OUTPUT_L RCLK
t
SODS
t
SODM
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLO CKS
(20-BIT DATA)
14-BIT CLO CKS
(18-BIT DATA)
16-BIT CLO CKS
(16-BIT DATA)
t
MSB – 1
t
SODS
t
SODM
MSB
t
SODS
t
SODM
MSB
LSB
08506-003
Figure 5. Serial Output Port Timing
MP
SDATA_OUTx
LEFT-JUSTIFIED
RIGHT -JUSTI FIED
MODE
SDATA_OUTx
2
I
S MODE
SDATA_OUTx
MODE
MCLKI
RESET
t
RLPW
Figure 6. Master Clock and
RESET
Timing
08506-006
Rev. A | Page 9 of 52
ADAU1401A
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
DVDD to Ground 0 V to 2.2 V
AVDD to Ground 0 V to 4.0 V
IOVDD to Ground 0 V to 4.0 V
Digital Inputs DGND − 0.3 V, IOVDD + 0.3 V
Maximum Junction Temperature 135°C
Storage Temperature Range −65°C to +150°C
Soldering (10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 10. Thermal Resistance
Package Type θJA θ
48-Lead LQFP 72 19.5 °C/W
Unit
JC
ESD CAUTION
Rev. A | Page 10 of 52
ADAU1401A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD
FILTA
VOUT0
VOUT1
VOUT2
VOUT3
AGND
FILTDCMPLL_MODE1
PLL_MODE0
AGND
36
AVDD
35
PLL_LF
34
PVDD
33
PGND
32
MCLKI
31
OSCO
30
RSVD
29
MP2/SDATA_I N2/AUX_ADC1
28
MP3/SDATA_I N3/AUX_ADC2
27
MP8/SDATA_O UT2/AUX_ADC3
26
MP9/SDATA_O UT3/AUX_ADC0
25
DGND
AGND
ADC0
ADC_RES
ADC1
RESET
SELFBOOT
ADDR0
MP4/INPUT_LRCLK
MP5/INPUT_BCLK
MP1/SDATA_I N1
MP0/SDATA_I N0
DGND
48 47 46 45 44 43 42 41 40 39 38 37
1
PIN 1
INDICATOR
2
3
4
5
6
7
8
9
10
11
12
ADAU1401A
TOP VIEW
(Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
DVDD
MP7/SDATA_OUT1
MP6/SDATA_O UT0/TDM_I N
MP11
IOVDD
VDRIVE
ADDR1/CDATA/WB
MP10/OUTPUT_LRCLK
DVDD
SCL/CCLK
SDA/COUT
CLATCH/WP
08506-007
Figure 7. 48-Lead LQFP Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Typ e1 Description
1, 37, 42 AGND PWR
Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. AGND should be decoupled to an AVDD pin with a 100 nF capacitor.
2 ADC0 A_IN
Analog Audio Input 0. Full-scale 100 A rms input. The current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input.
See the Audio ADCS section for details.
3 ADC_RES A_IN
ADC Reference Current. The full-scale current of the ADCs can be set with an external 18 kΩ
resistor connected between this pin and ground. See the Audio ADCS section for details.
4 ADC1 A_IN
Analog Audio Input 1. Full-scale 100 A rms input. The current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input.
5
RESET
D_IN
Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1401A exits
reset on a low-to-high edge. For more information about initialization, see the Power-Up
Sequence section for details.
6 SELFBOOT D_IN
Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting
this pin high initiates a self-boot operation when the ADAU1401A is brought out of a reset.
This pin can be tied directly to the control voltage or pulled up/down with a resistor. See
the Self-Boot section.
7 ADDR0 D_IN
8 MP4/INPUT_LRCLK D_IO
2
C and SPI Address 0. In combination with ADDR1, this pin allows up to four ADAU1401A
I
devices to be used on the same I
CLATCH signal. See the I
2
2
C bus or up to two ICs to be used with a common SPI
C Port section for details.
Multipurpose GPIO/Serial Input Port LRCLK. See the Multipurpose Pins section for more
details.
9 MP5/INPUT_BCLK D_IO Multipurpose GPIO/Serial Input Port BCLK. See the Multipurpose Pins section for more details.
10 MP1/SDATA_IN1 D_IO
Multipurpose GPIO/Serial Input Port Data 1. See the Multipurpose Pins section for more
details.
11 MP0/SDATA_IN0 D_IO
Multipurpose GPIO/Serial Input Port Data 0. See the Multipurpose Pins section for more
details.
12, 25 DGND PWR
Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. DGND should be decoupled to a DVDD pin with a 100 nF capacitor.
13, 24 DVDD PWR
1.8 V Digital Supply. The input for this pin can be supplied either externally or generated
Rev. A | Page 11 of 52
ADAU1401A
Pin No. Mnemonic Typ e1 Description
from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND
with a 100 nF capacitor.
14 MP7/SDATA_OUT1 D_IO
15
MP6/SDATA_OUT0/
D_IO
TDM_IN
16 MP10/OUTPUT_LRCLK D_IO
17 VDRIVE A_OUT
18 IOVDD PWR
19 MP11 D_IO
20 ADDR1/CDATA/WB D_IN
21 CLATCH/WP D_IO
22 SDA/COUT D_IO
23 SCL/CCLK D_IO
26
MP9/SDATA_OUT3/
D_IO/A_IO
AUX_ADC0
27
MP8/SDATA_OUT2/
D_IO/A_IO
AUX_ADC3
28
MP3/SDATA_IN3/
D_IO/A_IO
AUX_ADC2
29
MP2/SDATA_IN2/
D_IO/A_IO
AUX_ADC1
30 RSVD Reserved. Tie this pin to ground, either directly or through a pull-down resistor.
31 OSCO D_OUT
32 MCLKI D_IN
33 PGND PWR
34 PVDD PWR
35 PLL_LF A_OUT
36, 48 AVDD PWR 3.3 V Analog Supply. This pin should be decoupled to AGND with a 100 nF capacitor.
Multipurpose GPIO/Serial Output Port Data 1. See the Multipurpose Pins section for
more details.
Multipurpose GPIO/Serial Output Port Data 0/TDM Data Input. See the Multipurpose Pins
section for more details.
Multipurpose GPIO/Serial Output Port LRCLK. See the Multipurpose Pins section for
more details.
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is
driven from VDRIVE. See the Voltage Regulator section for details.
Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that
should be seen on the digital input pins. This pin is also the supply for the digital output signals
on the control port and MPx pins. IOVDD should always be set to 3.3 V. The current draw of this
pin is variable because it is dependent on the loads of the digital outputs.
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins
section for more details.
2
C Address 1/SPI Data Input/EEPROM Writeback Trigger. ADDR1 in combination with ADDR0
I
sets the I
bus (see the I
2
C address of the IC so that four ADAU1401A devices can be used on the same I2C
2
C Port section for details). For more information about the CDATA function of this
pin, see the SPI Port section. A rising (default) or falling (if set by EEPROM messages) edge
on the WB pin triggers a writeback of the interface registers to the external EEPROM. This
function can be used to save parameter data on power-down (see the Self-Boot section
for details).
SPI Latch Signal/Self-Boot EEPROM Write Protect. CLATCH must go low at the beginning of an
SPI transaction and high at the end of a transaction. Each SPI transaction can take a different
number of cycles on the CCLK pin to complete, depending on the address and read/write
bit that are sent at the beginning of the SPI transaction (see the SPI Port section for details). The
WP pin is an open-collector output when the device is in self-boot mode. The ADAU1401A
pulls WP low to enable writes to an external EEPROM. This pin should be pulled high to
3.3 V (see the Self-Boot section for details).
2
C Data/SPI Data Output. SDA is a bidirectional open collector. The line connected to SDA
I
should have a 2.2 kΩ pull-up resistor (see the I
2
C Port section for details). COUT is used for
reading back registers and memory locations. It is three-stated when an SPI read is not
active (see the SPI Port section for details).
2
C Clock/SPI Clock. SCL is always an open-collector input when in I2C control mode. In
I
self-boot mode, SCL is an open-collector output (I
should have a 2.2 kΩ pull-up resistor (see the I
2
C master). The line connected to SCL
2
C Port section for details). CCLK can either
run continuously or be gated off between SPI transactions (see the SPI Port section for details).
Multipurpose GPIO/Serial Output Port Data 3/Auxiliary ADC Input 0. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Output Port Data 2/Auxiliary ADC Input 3. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Input Port Data 3/Auxiliary ADC Input 2. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Input Port Data 2/Auxiliary ADC Input 1. See the Multipurpose
Pins section for more details.
Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be connected between
this pin and the crystal. This output should not be used to directly drive a clock to another
IC. If the crystal oscillator is not used, this pin can be left unconnected. See the Using the
Oscillator section for details.
Master Clock Input. This pin can either be connected to a 3.3 V clock signal or be the input
from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details.
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This pin should be
decoupled to PGND with a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor must be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
Rev. A | Page 12 of 52
ADAU1401A
Pin No. Mnemonic Typ e1 Description
38, 39
PLL_MODE0,
PLL_MODE1
40 CM A_OUT
41 FILTD A_OUT
43 VOUT3 A_OUT
44 VOUT2 A_OUT
45 VOUT1 A_OUT
46 VOUT0 A_OUT
47 FILTA A_OUT
1
PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
input/output.
D_IN
PLL Mode Setting. These pins set the output frequency of the master clock PLL. See the
Setting Master Clock/PLL Mode section for more details.
1.5 V Common-Mode Reference. A 47 F decoupling capacitor should be connected
between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of
the capacitors is not critical. This pin can be used to bias external analog circuits, as long as
those circuits are not drawing current from the pin (such as when the CM pin is connected
to the noninverting input of an op amp).
DAC Filter Decoupling Pin. A 10 F capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
VOUT3 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
an active or passive output reconstruction filter. See the Audio DACS section for details.
VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
an active or passive output reconstruction filter. See the Audio DACS section for details.
VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
an active or passive output reconstruction filter. See the Audio DACS section for details.
VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
an active or passive output reconstruction filter. See the Audio DACS section for details.
ADC Filter Decoupling Pin. A 10 F capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
Rev. A | Page 13 of 52
ADAU1401A
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
0.05
0
GAIN (dB)
–0.05
–0.10
–0.15
–0.20
0 2 4 6 8 10 12 14 16 18 20 22
FREQUENCY (kHz)
Figure 8. ADC Pass-Band Filter Response
f
= 48kHz
S
08506-008
0.10
0.08
0.06
0.04
0.02
0
GAIN (dB)
–0.02
–0.04
–0.06
–0.08
–0.10
0 5 10 15 20
FREQUENCY (kHz)
Figure 10. DAC Pass-Band Filter Response
f
= 48kHz
S
8506-010
10
0
–10
–20
–30
–40
–50
GAIN (dB)
–60
–70
–80
–90
–100
0 2530354020151054
FREQUENCY (kHz)
f
= 48kHz
S
5
8506-009
Figure 9. ADC Stop-Band Filter Response
10
0
–10
–20
–30
–40
–50
GAIN (dB)
–60
–70
–80
–90
–100
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)
Figure 11. DAC Stop-Band Filter Response
f
= 48kHz
S
8506-011
Rev. A | Page 14 of 52
ADAU1401A
V
SYSTEM BLOCK DIAGRAM
100nF
3.3
AUDIO ADC
INPUT SIGNALS
10µF
MULTIPURPOSE
PIN INTERF ACES
ADCs DACs
100nF
100nF
10µF
+
IOVDD PVDD AVDD DVDD VDRIVE
18k
18k
18k
+
100nF
ADC0
ADC1
ADC_RES
FILTA
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
ADAU1401A
100nF
10µF
+
3.3V TO 1. 8V
REGULATOR
CIRCUIT
VOUT0
VOUT1
VOUT2
VOUT3
FILTD
CM
ADDR0
ADDR1/CDATA/WB
DAC OUTPUT FILTERS
(ACTIVE OR PASSIVE)
+
+
47µF
100nF10µ F
100nF
EEPROM,
MICROCONTRO LLER,
AND/OR SELF-BOOT
LOGIC
RESET LOGIC
08506-012
22pF
3.3V
PLL
SETTINGS
3MHz TO 25MHz
22pF
100
475
56nF3.3nF
PLL_LF
PLL_MODE0
PLL_MODE1
MCLKI
OSCO
AGND DGND PGND
CLATCH/WP
SDA/COUT
SCL/CCLK
SELFBOOT
RESET
RSVD
Figure 12. System Block Diagram
Rev. A | Page 15 of 52
ADAU1401A
THEORY OF OPERATION
The core of the ADAU1401A is a 28-bit DSP (56-bit with doubleprecision processing) optimized for audio processing. The
program and parameter RAMs can be loaded with a custom
audio processing signal flow built using the SigmaStudio graphical
programming software from Analog Devices, Inc. The values
stored in the parameter RAM control individual signal processing
blocks, such as equalization filters, dynamics processors, audio
delays, and mixer levels. A safeload feature allows transparent
parameter updates and prevents clicks in the output signals.
The program RAM, parameter RAM, and register contents can
be saved in an external EEPROM, from which the ADAU1401A
can self-boot on startup. In this standalone mode, parameters
can be controlled through the on-board multipurpose pins. The
ADAU1401A can accept controls from switches, potentiometers,
rotary encoders, and IR receivers. Parameters such as volume
and tone settings can be saved to the EEPROM on power-down
and recalled again on power-up.
The ADAU1401A can operate with digital or analog inputs and
outputs, or a mix of both. The stereo ADC and four DACs each
have an SNR of at least +100 dB and a THD + N of at least
−83 dB. The 8-channel, flexible serial data input/output ports
allow glueless interconnection to a variety of ADCs, DACs,
general-purpose DSPs, S/PDIF receivers and transmitters, and
sample rate converters. The serial ports of the ADAU1401A can
be configured in I
2
S, left-justified, right-justified, or TDM serial
port compatible modes.
Twelve multipurpose pins (MP0 to MP11) allow the ADAU1401A
to receive external control signals as input and to output flags or
controls to other devices in the system. The MPx pins can be
configured as digital I/Os, inputs to the 4-channel auxiliary
ADC, or serial data I/O ports. As inputs, these pins can be
connected to buttons, switches, rotary encoders, potentiometers,
IR receivers, or other external circuitry to control the internal
signal processing program. When configured as outputs, these
pins can be used to drive LEDs, control other ICs, or connect to
other external circuitry in an application.
The ADAU1401A has a sophisticated control port that supports
complete read/write capability of all memory locations. Control
registers are provided to offer complete control of the configuration and serial modes of the chip. The ADAU1401A can be
configured for either SPI or I
2
C control, or it can self-boot from
an external EEPROM.
An on-board oscillator can be connected to an external crystal
to generate the master clock. In addition, a master clock phase-
locked loop (PLL) allows the ADAU1401A to be clocked from
various clock speeds. The PLL can accept inputs of 64 × f
384 × f
, or 512 × fS to generate the internal master clock of the core.
S
, 256 × fS,
S
The SigmaStudio software is used to program and control the
SigmaDSP® through the control port. Along with designing and
tuning a signal flow, SigmaStudio tools can be used to configure
all of the DSP registers and burn a new program into the external
EEPROM. The SigmaStudio graphical interface allows anyone
with digital or analog audio processing knowledge to easily design
a DSP signal flow and port it to a target application. In addition,
the interface provides enough flexibility and programmability
for an experienced DSP programmer to have in-depth control
of the design. In SigmaStudio, the user can connect graphical
blocks (such as biquad filters, dynamics processors, mixers, and
delays), compile the design, and load the program and parameter
files into the ADAU1401A memory through the control port.
Signal processing blocks available in the provided libraries include
• Single- and double-precision biquad filters
• Processors with peak or rms detection for monochannel
and multichannel dynamics
• Mixers and splitters
• Tone and noise generators
• Fixed and variable gain
• Loudness
• Delay
• Stereo enhancement
• Dynamic bass boost
• Noise and tone sources
• FIR filters
• Level detectors
• GPIO control and conditioning
Additional processing blocks are always being developed.
Analog Devices also provides proprietary and third-party
algorithms for applications such as matrix decoding, bass
enhancement, and surround virtualizers. Contact Analog
Devices for information about licensing these algorithms.
The ADAU1401A operates from a 1.8 V digital power supply
and a 3.3 V analog supply. An on-board voltage regulator can
be used to operate the chip from a single 3.3 V supply. The
ADAU1401A is fabricated on a single monolithic, integrated
circuit and is packaged in a 48-lead LQFP for operation over the
−40°C to +105°C temperature range.
Rev. A | Page 16 of 52
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