ANALOG DEVICES ADAU1328 Service Manual

2 ADC/8 DAC with PLL,

FEATURES

PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Single-ended DAC output Log volume control with autoramp function SPI® controllable for flexibility Software controllable clickless mute Software power-down Right justified, left justified, I Master and slave modes up to 16-channel in/out 48-lead LQFP

APPLICATIONS

Home theater systems Set-top boxes Digital audio effects processors

2

S and TDM modes

192 kHz, 24-Bit Codec

ADAU1328

GENERAL DESCRIPTION

The ADAU1328 is a high performance, single-chip codec that provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc. patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1328 operates from 3.3 V digital and analog supplies. The ADAU1328 is available in a 48-lead (single-ended output) LQFP. Other members of this family include a differential DAC output version.

The ADAU1328 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the ADAU1328 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The digital-to-analog and analog-to-digital converters are designed using the latest ADI continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDI O INPUT/OUTPUT

ADAU1328

SERIAL DATA PORT

SDATA

ADC

PRECISION

VOLTAGE

REFERENCE

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DEC

FILTER

48/96/

192kHz

OUT

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

12.488MHz 6.144MHz

CONTROL DAT A

INPUT/OUTPUT

CLOCKS

CONTROL

PORT

SPI

Figure 1.

DAC

SDATA

IN

DIGITAL

FILTER

AND

VOLUME

CONTROL

DAC DAC DAC DAC DAC DAC DAC

06102-001

ADAU1328

REVISION HISTORY

7/11—Rev. 0 to Rev. A

Deleted References to I

Changes to Table 9, DSDATAx/ASDATAx Pin Descriptions..... 9

Updated Outline Dimensions....................................................... 31

6/06—Revision 0: Initial Version

2

C ............................................. Throughout

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Rev. A | Page 2 of 32

ADAU1328

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range Master Clock 12.288 MHz (48 kHz f Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V

1

Functionally guaranteed at −40°C to +85°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter Conditions Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 102 dB

With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB

With A-Weighted Filter (RMS) 100 106 dB

With A-Weighted Filter (Avg) 108 dB Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 16 mV Gain Drift −30 30 ppm/°C Interchannel Isolation 100 dB

1

As specified in Table 1

, 256 × fS mode)

S

Rev. A | Page 3 of 32

ADAU1328

Parameter Conditions Min Typ Max Unit

Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit

Transconductance 3.5 Mmhos

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +85°C, DVDD = 3.3 V ± 10%.

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

Input Voltage HI (VIH) 2.0 V Input Voltage HI (VIH) MCLKI pin 2.2 V Input Voltage LO (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

@ VIL = 0.8 V 10 μA

IL

Rev. A | Page 4 of 32

ADAU1328

POWER SUPPLY SPECIFICATIONS

Table 4.

Parameter Conditions/Comments Min Typ Max Unit SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 fS

Normal Operation fS = 48 kHz 56 mA

f

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation MCLK = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Rev. A | Page 5 of 32

ADAU1328

DIGITAL FILTERS

Table 5.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER

Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844/fS 479 μs

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typ @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typ @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB 96 kHz mode, typ @ 96 kHz ±0.05 dB 192 kHz mode, typ @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typ @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typ @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typ @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typ @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB 96 kHz mode, typ @ 96 kHz 70 dB 192 kHz mode, typ @ 192 kHz 70 dB

Group Delay 48 kHz mode, typ @ 48 kHz 25/fS 521 μs 96 kHz mode, typ @ 96 kHz 11/fS 115 μs 192 kHz mode, typ @ 192 kHz 8/fS 42 μs

All modes, typ @ 48 kHz

TIMING SPECIFICATIONS

−40°C < TA < +85°C, DVDD = 3.3 V ± 10%.

Table 6.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle

tMH

f

MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

MCLK

f

Direct 512 fS mode 27.6 MHz

MCLK

t

PDR

t

PDRR

PLL

Lock Time MCLK and LRCLK input 10 ms

256 fS VCO Clock, Output Duty Cycle MCLKO pin 40 60 %

40 60 %

MCLK

low

RST

recovery

RST

DAC/ADC clock source = PLL clock @

, 384 fS, 512 fS, 768 fS

256 f

S

DAC/ADC clock source = direct MCLK @

(bypass on-chip PLL)

512 f

S

15 ns Reset to active output 4096 t

Rev. A | Page 6 of 32

ADAU1328

Parameter Condition Comments Min Max Unit

SPI PORT See Figure 11

t

CCLK high 35 ns

CCH

t

CCLK low 35 ns

CCL

f

CCLK frequency f

CCLK

t

CDATA setup To CCLK rising 10 ns

CDS

t

CDATA hold From CCLK rising 10 ns

CDH

t

CLS

t

CLH

t

CLHIGH

t

COUT enable From CCLK falling 30 ns

COE

t

COUT delay From CCLK falling 30 ns

COD

t

COUT hold From CCLK falling, not shown in Figure 11 30 ns

COH

t

COUT tri-state From CCLK falling 30 ns

COTS

CLATCH CLATCH CLATCH

setup hold high

DAC SERIAL PORT See Figure 24

t

DBCLK high Slave mode 10 ns

DBH

t

DBCLK low Slave mode 10 ns

DBL

t

DLRCLK setup To DBCLK rising, slave mode 10 ns

DLS

t

DLRCLK hold From DBCLK rising, slave mode 5 ns

DLH

t

DLRCLK skew From DBCLK falling, master mode −8 +8 ns

DLS

t

DSDATA set up To DBC L K r ising 10 ns

DDS

t

DSDATA hold From DBCLK rising 5 ns

DDH

ADC SERIAL PORT See Figure 25

t

ABCLK high Slave mode 10 ns

ABH

t

ABCLK low Slave mode 10 ns

ABL

t

ALRCLK setup To ABCLK rising, slave mode 10 ns

ALS

t

ALRCLK hold From ABCLK rising, slave mode 5 ns

ALH

t

ALRCLK skew From ABCLK falling, master mode −8 +8 ns

ALS

t

ASDATA delay From ABCLK falling 18 ns

ABDD

AUXILIARY INTERFACE

t

AAUXDATA s etu p To AUXBCLK risi n g 10 ns

AXDS

t

AAUXDATA hold From AUXBCLK rising 5 ns

AXDH

t

DAUXDATA delay From AUXBCLK falling 18 ns

DXDD

t

AUXBCLK high 10 ns

XBH

t

AUXBCLK low 10 ns

XBL

t

AUXLRCLK setup To AUXBCLK rising 10 ns

DLS

t

AUXLRCLK hold From AUXBCLK rising 5 ns

DLH

= 1/t

CCLK

CCP

, only t

shown in Figure 11 10 MHz

CCP

To CCLK rising 10 ns From CCLK falling 10 ns Not shown in Figure 11 10 ns

Rev. A | Page 7 of 32

ADAU1328

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +85°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient; θ represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board.

Table 8. Thermal Resistance

Package Type θJA θ

48-Lead LQFP 50.1 17 °C/W

Unit

JC

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 32

ADAU1328

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

MCLKI/XI

MCLKO/XO

AGND

AVDD

OL3

OR3

OL4

OR4

PD/RST

DSDATA4

DGND

AVDD48LF47ADC2RN46ADC2RP45ADC2LN44ADC2LP43ADC1RN42ADC1RP41ADC1LN40ADC1LP39CM38AVDD

1

2

3

4

5

6

7

8

9

10

11

12

13

DVDD

DSDATA314DSDATA215DSDATA1

ADAU1328

TOP VIEW

(Not to Scale)

SINGLE- ENDED

OUTPUT

16

17

18

DBCLK

20

DLRCLK

ASDATA219ASDATA1

21

ABCLK

37

36

AGND

35

FILTR

34

AGND

33

AVDD

32

AGND

31

OR2

30

OL2

29

OR1

28

OL1

27

CLATCH/ADR1

26

CCLK/SCL

25

DGND

22

23

24

ALRCLK

CIN/ADR0

COUT/SD

06102-020

Figure 2. Pin Configuration

Table 9. Pin Function Description

Pin No. In/Out Mnemonic Description

1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3 DAC 3 Left Output. 7 O OR3 DAC 3 Right Output. 8 O OL4 DAC 4 Left Output. 9 O OR4 DAC 4 Right Output. 10 I

PD

/RST

11 I/O DSDATA4

Power-Down Reset (Active Low). DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX

DAC2 data out (to external DAC2). 12 I DGND Digital Ground. 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 14 I/O DSDATA3

DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX ADC2

data in (from external ADC2). 15 I/O DSDATA2

DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in (from

external ADC1). 16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in. 17 I/O DBCLK Bit Clock for DACs. 18 I/O DLRCLK LR Clock for DACs. 19 I/O ASDATA2

ADC Serial Data Output 2. Data output from ADC2/TDM ADC data in/AUX DAC1 data out (to

external DAC1). 20 O ASDATA1 ADC Serial Data Output 1. Data output from ADC1/TDM ADC data out/TDM data out. 21 I/O ABCLK Bit Clock for ADCs. 22 I/O ALRCLK LR Clock for ADCs.

Rev. A | Page 9 of 32

ADAU1328

Pin No. In/Out Mnemonic Description

23 I CIN/ADR0 Control Data Input (SPI). 24 I/O COUT/SDA Control Data Output (SPI). 25 I DGND Digital Ground. 26 I CCLK/SCL Control Clock Input (SPI). 27 I 28 O OL1 DAC 1 Left Output. 29 O OR1 DAC 1 Right Output. 30 O OL2 DAC 2 Left Output. 31 O OR2 DAC 2 Right Output. 32 I AGND Analog Ground. 33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 34 I AGND Analog Ground. 35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 36 I AGND Analog Ground. 37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. 39 I ADC1LP ADC1 Left Positive Input. 40 I ADC1LN ADC1 Left Negative Input. 41 I ADC1RP ADC1 Right Positive Input. 42 I ADC1RN ADC1 Right Negative Input. 43 I ADC2LP ADC2 Left Positive Input. 44 I ADC2LN ADC2 Left Negative Input. 45 I ADC2RP ADC2 Right Positive Input. 46 I ADC2RN ADC2 Right Negative Input. 47 O LF PLL Loop Filter. Return to AVDD. 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

CLATCH

/ADR1

Latch Input for Control Data (SPI).

Rev. A | Page 10 of 32

ANALOG DEVICES ADAU1328 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS