ANALOG DEVICES ADATE205 Service Manual

V

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250 MHz Dual DCL

FEATURES

Driver, comparator, and active load 250 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: −1.5 V to +6.5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead thin quad flat package, exposed pad Low per channel power

1.15 W with load off

1.50 W with load programmed at 20 mA nominal Low leakage (<10 nA) in High-Z mode Driver

50 Ω output resistance

1.6 ns minimum pulse width for a 3 V step Load: −35 mA to +35 mA maximum current range

APPLICATIONS

Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment

GENERAL DESCRIPTION

The ADATE205 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications. The active load can be powered down if not used.

The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state.

The driver has low leakage (<10 nA) in High-Z mode. The output voltage range is −1.5 V to +6.5 V to accommodate a wide variety of test devices.

The ADATE205 supports four programmable Tr/Tf times for applications where slower edge rates are required. The edge rate selection is done via two static digital CMOS select bits. The input data to the driver can be inverted using a single CMOS logic bit. This feature can be used for system calibration or applications where complement input data is needed.

DR_INV

DR_DATA_P

DR_DATA_P_T

DR_DATA_N_T

DR_DATA_N

DR_EN_P

DR_EN_P_T

DR_EN_N_T

DR_EN_N

VTEN

LDEN

COMP_H_P

COMP_H_N

CLLM

COMP_L_P

COMP_L_N

VCOM

VIOL

VIOH

GNDREF

FUNCTIONAL BLOCK DIAGRAM

(18, 19, 57, 58 , 77, 78, 89, 98, 99)

7

VIT

69

8

VIL

68

9

VIH

67

6

70

22

54

23

53

24

52

25

51

26

50

27

49

28

48

29

47

15

61

14

62

91

CVH

85

31

45

32

44

13

63

34

42

35

41

90

CVL

86

1

75

4

72

3

73

2

74

VEE

(16, 17, 33, 43 , 59, 60, 84, 87, 92)

CC

LOGIC

LOAD

LOGIC

NC

(30, 46)

DRIVER

COMP_H

COMP_L

1x

(5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100)

Figure 1.

ADATE205

SHIELDS

(80, 82, 94, 96)

ADATE205

10

CLAMPL

65

11

CLAMPH

66

81

DUT

95

IOL

IOH

TEMP SENSOR

(5 DIODES)

GND

TEMP

88

05737-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

10/08—Rev. 0 to Rev. A

Changes to VCOM Buffer Offset Parameter, Table 1 .................. 7

1/06—Revision 0: Initial Version

ESD Caution...................................................................................8

Pin Configuration and Function Descriptions ..............................9

Typical Performace Characteristics ............................................. 12

Theory of Operation ...................................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. A | Page 2 of 16

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VCC = 10 V, VEE = −5 V, TJ = 75°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Single-Ended Logic Input Characteristics (VTEN, DRV_INV)

Threshold Voltage CMOS_VDD/2 V Voltage Range 0 5.5 V Bias Current −10 +10 μA VIN = 0 V, 3.3 V

Single-Ended Logic Input Characteristics (SLEW0, SLEW1)

Threshold Voltage CMOS_VDD/2 V Voltage Range 0 5.5 V Bias Current −10 +600 (@ 3.3 V) +800 μA VIN = 0 V, 3.3 V Bias Current 1 mA VIN = 5.5 V

Differential Logic Input Characteristics (DR_DATA_N, DR_DATA_P, DR_EN_N, DR_EN_P)

Voltage Range −2.0 +3.5 V Differential Voltage with LVPECL Levels ±250 ±300 mV Bias Current −10 +2 +10 μA VIN = 3.24 V, 3.495 V

VIH, VIL Reference Inputs

Input Bias Current −10 −2 +10 μA

VIT Reference Inputs

Input Bias Current −25 +12 +25 μA

DC Output Characteristics

Logic Range, VIL, VIH, VIT −1.5 +6.5 V Amplitude [VH to VL] 8 V Output Resistance 47.5 52.5 Ω PSRR, Drive or Term Mode 10 mV/V VCC, VEE ±1% Static Current Limit −125 ±110 +125 mA

Absolute Accuracy—VIH, VIL, VIT

VIH Offset −100 +30 +100 mV

VIH Gain Error 0.98 1.02 V/V

VIH Linearity Error −15 +5 +15 mV

VIL Offset −100 +30 +100 mV VIL Gain Error 0.98 1.02 V/V

VIL Linearity Error −15 +5 +15 mV

VIT Offset −100 +30 +100 mV

VIT Gain Error 0.98 1.02 V/V

Maximum value bias of reference sweep

Output to −1.5 V, VH = 6.5 V, VT = 0 V

Data = H, VH = 0 V, VL = −1.5 V, VT = 3 V

Data = H, VH = 0 V to 5 V, VL = −1.5 V, VT = 3 V

Data = VH relative to line between 0 V to 5 V; full range of VIH = −1.4 V to +6.5 V

Data = L, VL = 0 V to 5 V, VH = 6.5 V, VT = 3 V

Data = VH relative to line between 0 V to 5 V; full range of VIH = −1.4 V to +6.5 V

Data = VT, VT = 0 V, VL = 0 V, VH = 3 V

Data = VT, VT = 0 V to 5 V, VL = 0 V, VH = 3 V

Rev. A | Page 3 of 16

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Parameter Min Typ Max Unit Test Conditions/Comments

VIT Linearity Error −15 +5 +15 mV

Offset Tempco 80 μV/°C 65°C to 105°C

Driver Interaction

VH Interaction to VL −2 +2 mV

VH Interaction to VT −2 +2 mV

VL Interaction to VH −2 +2 mV

VL Interaction to VT −2 +2 mV

VT Interaction to VH −2 +2 mV

VT Interaction to VL −2 +2 mV

Rise/Fall Times at Device Under Testing (DUT)

0.2 V Swing: Rise/Fall Time 300 ps

0.5 V Swing: Rise/Fall Time 500 ps

1 V Swing: Rise/Fall Time 800 ps

3 V Swing: Rise/Fall Time 1.1 ns

3 V Swing: Rise/Fall Time 700 800 920 ps

5 V Swing: Rise/Fall Time 1.8 ns

Minimum Pulse Width at DUT

500 mV Swing

1.5 V Swing

1

500 ps

1

800 ps

Toggle Rate @ 3 V 250 MHz

Dynamic Performance, Drive (VH and VL)

Propagation Delay Time

Propagation Delay Tempco

2

1.4 ns

2

2.0 ps/°C

Delay Matching, Edge-to-Edge 20 ps Delay Change vs. Pulse Width

Delay Change vs. Duty Cycle

2

30 ps

2

5 ps

Rev. A | Page 4 of 16

Data = VH relative to line between 0 V to 5 V; full range of VIH = −1.4 V to +6.5 V

VIH = 5.0 V; VIL = −1.5 V, +4.7 V, +4.8 V, +4.9 V

VIH = 3.0 V; VIT = −1.5 V, +2.9 V, +3.1 V, +6.5 V

VIL = 0.0 V; VIH = 0.1 V, 0.2 V,

0.3 V, 6.5 V VIL = 0.0 V; VIT = −1.5 V, −0.1 V,

+0.1 V, +6.5 V VIT = 1.5 V, VIL = −1.0 V;

VIH = −0.8 V, +1.4 V, +1.6 V, +6.5 V

VIT = 1.5 V, VIH = 6.0 V; IL = −1.5 V, +1.4 V, +1.6 V, +5.8 V

Terminated 20% to 80%, VIH = 400 mV, VIL = 0 V, VIT = 0 V

Terminated 10% to 90%, VIH = 1.0 V, VIL = 0 V, VIT = 0 V

Terminated 10% to 90%, VIH = 2.0 V, VIL = 0 V, VIT = 0 V

Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V

Terminated 20% to 80%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V using DUT comparator

Unterminated 10% to 90%; VIH = 5.0 V, VIL = 0 V, VIT = 0 V

Terminated, VIH = 1.0 V, VIL = 0 V, VIT = 0 V

Terminated, VIH = 3.0 V, VIL = 0 V, VIT = 0 V

Unterminated, 50/50 dc measured frequency when amplitude drops 10%

Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V

Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65°C to 85°C

Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1μs period, pulse width = 50 ns to 1 ns

Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1 μs period; 10%, 50%, and 90% duty cycle

ADATE205

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Parameter Min Typ Max Unit Test Conditions/Comments

Settling Time to 15 mV 8 ns

Settling Time to 4 mV 32 ns

Rise and Fall Time Temperature Coefficient

500 mV Swing 2 ps/°C

1 V Swing 2 ps/°C

3 V Swing 2 ps/°C

5 V Swing 2 ps/°C

Overshoot and Preshoot 200 mV swing 1 % Terminated, VIH = 400 mV Overshoot and Preshoot 1 V swing 1 % Terminated, VIH = 2 V Overshoot and Preshoot 3 V swing 2 % Unterminated Overshoot and Preshoot 5 V swing 2 % Unterminated

Dynamic Performance, Inhibit

Delay Time, Active High to Inhibit

Delay Time, Active Low to Inhibit

Delay Time, Inhibit to Active High

Delay Time, Inhibit to Active Low

3

3.1 ns

3

2.1 ns

3

2.5 ns

3

3.9 ns

I/O Spike 350 mV

CLAMPS

VCPH, VCPL Clamp Inputs

VCPH Voltage Range CLAMPL 6.8 V VCPL Voltage Range −1.8 CLAMPH V Input Bias Current −50 −2 +50 μA

Absolute Accuracy VCPH, VCPL

VCPH Offset −100 +55 +100 mV Driver = INH, VCPH = 0 V VCPH Gain Error 1 V/V VCPH Linearity Error +10 mV

VCPL Offset −100 +55 +100 mV Driver = INH, VCPL = 0 V VCPL Gain Error 1 V/V VCPL Linearity Error +10 mV

COMPARATOR DC SPECIFICATIONS

4

DC Input Characteristics (VOH, VOL)

Bias Current −10 +5 +10 μA VOH and VOL = −1.5 V to +6.5 V Voltage Range −1.5 +6.5 V Differential Voltage −8.0 +8.0 V

Rev. A | Page 5 of 16

Terminated, VIH = 3 V, VIL = 0.0 V, VIT = 0.0 V

Terminated 10% to 90%, VIH = 1.0 V, VIL = 0.0 V, VIT = 0.0 V, 65°C to 85°C

Terminated 10% to 90%, VIH = 2.0 V, VIL = 0.0 V, VIT = 0.0 V, 65°C to 85°C

Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65°C to 85°C

Unterminated 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, VIT = 0.0 V, 65°C to 85°C

Terminated, VIH = 3.0 V, VIL = −1.0 V

VH = 3.0 V, VL = −1.0 V, terminated 50 Ω

Terminated, VIH = 3.0 V, VIL = −1.0 V

Terminated, VIH = 0.0 V, VIL = 0.0 V, VIT = 0.0 V

Maximum value bias of reference sweep = −1.8 V to +6.8 V

Driver = INH, relative to line between 0 V to 4.5 V, VCPH = −1.5 V to +6.5 V, VCPL = −1.8 V

Driver = INH, relative to line between 0 V to 4.5 V, VCPL = −1.5 V to +6.5 V, VCPH = 6.5 V

ANALOG DEVICES ADATE205 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS