Analog Devices AD9834 Datasheet

20 mW Power, 2.3 V to 5.5 V,

a

FEATURES
Narrow-band SFDR >72 dB

2.3 V to 5.5 V Power Supply
50 MHz Ref Clock, 0 MHz to 25 MHz Output
Sine Output/Triangular Output
On-Board Comparator
3-Wire SPI
Extended Temperature Range: –40ⴗC to +105ⴗC
Power-Down Option
20 mW Power Consumption at 3 V
20-Lead TSSOP Package

APPLICATIONS
Frequency Stimulus/Waveform Generation
Frequency Phase Tuning and Modulation
Low Power RF/Communications Systems
Liquid and Gas Flow Measurement
Sensory Applications—Proximity, Motion, and

Defect Detection

Test and Medical Equipment

GENERAL DESCRIPTION

The AD9834 is a 50 MHz low power DDS device capable of
producing high performance sine and triangular outputs. It also
has an on-board comparator that allows a square wave to be
produced for clock generation. Consuming only 20 mW of

®

Interface

50 MHz Complete DDS

AD9834

power at 3 V makes the AD9834 an ideal candidate for power­sensitive applications.

Capability for phase modulation and frequency modulation is
provided. The Frequency registers are 28 bits; with a 50 MHz
clock rate, resolution of 0.2 Hz can be achieved. Similarly,
with a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz
resolution. Frequency and phase modulation are affected by
loading registers through the serial interface and toggling the
registers using software or the FSELECT/PSELECT pins,
respectively.

The AD9834 is written to via a 3-wire serial interface. This
serial interface operates at clock rates up to 40 MHz and is
compatible with DSP and microcontroller standards.

The device operates with a power supply from 2.3 V to 5.5 V.
The analog and digital sections are independent and can be run
from different power supplies, e.g., AVDD can equal 5 V with
DVDD equal to 3 V.

The AD9834 has a power-down pin (SLEEP) that allows exter­nal control of the power-down mode. Sections of the device that
are not being used can be powered down to minimize the current
consumption, e.g., the DAC can be powered down when a
clock output is being generated.

The part is available in a 20-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

CAP/2.5VDVDDAGNDAVDD

S

MUX

MCLK

FSELECT

28-BIT FREQ0

REG

28-BIT FREQ1

REG

SERIAL INTERFACE

FSYNC SCLK SDATA

MUX

12-BIT PHASE0 REG

12-BIT PHASE1 REG

AND

CONTROL LOGIC

DGND

REGULATOR

PHASE

ACCUMULATOR

(28-BIT)

16-BIT CONTROL

REGISTER

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

REFOUT FS ADJUST

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

SIN

ROM

MUX

MUX

SLEEP

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

DIVIDED

BY 2

RESETPSELECT

MUX

MSB

10-BIT

DAC

COMPARATOR

AD9834

COMP

IOUT

IOUTB

SIGN BIT OUT

VIN

12

VCC

2.5V

AD9834–SPECIFICATIONS

(VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = T

1

R

= 200 ⍀ for IOUT and IOUTB, unless otherwise noted.)

LOAD

MIN

to T

MAX

, R

SET

= 6.8 k⍀,

Parameter Min Typ Max Unit Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution 10 Bits
Update Rate 50 MSPS

Full Scale

I

OUT

Max 0.6 V

V

OUT

Min 30 mV

V

OUT

Output Compliance

2

3

3.0 mA

0.8 V

DC Accuracy

Integral Nonlinearity ± 1 LSB
Differential Nonlinearity ± 0.5 LSB

DDS SPECIFICATIONS

Dynamic Specifications

Signal-to-Noise Ratio 55 60 dB f

Total Harmonic Distortion –66 –56 dBc f

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

OUT

OUT

= f
= f

MCLK

MCLK

Spurious-Free Dynamic Range (SFDR)

Wideband (0 to Nyquist) –60 –56 dBc f
Narrow Band (± 200 kHz) –78 –67 dBc f

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

OUT

OUT

= f
= f

MCLK

MCLK

Clock Feedthrough –50 dBc

Wake-Up Time 1 ms

COMPARATOR

Input Voltage Range 1 V p-p AC-Coupled Internally
Input Capacitance 10 pF
Input High-Pass Cutoff Frequency 4 MHz
Input DC Resistance 5 MW
Input Leakage Current 10 mA

OUTPUT BUFFER

Output Rise/Fall Time 12 ns Using a 15 pF Load
Output Jitter 120 ps rms 3 MHz Sine Wave 0.6 V p-p

VOLTAGE REFERENCE

Internal Reference 1.12 1.18 1.24 V
REFOUT Output Impedance

4

1kW

Reference TC 100 ppm/∞C

LOGIC INPUTS

V

, Input High Voltage 1.7 V 2.3 V to 2.7 V Power Supply

INH

2.0 V 2.7 V to 3.6 V Power Supply

2.8 V 4.5 V to 5.5 V Power Supply

, Input Low Voltage 0.6 V 2.3 V to 2.7 V Power Supply

V

INL

0.7 V 2.7 V to 3.6 V Power Supply

0.8 V 4.5 V to 5.5 V Power Supply

I

, Input Current 10 mA

INH/IINL

CIN, Input Capacitance 3 pF

POWER SUPPLIES f

= 50 MHz, f

MCLK

OUT

= f

MCLK

AVDD 2.3 5.5 V
DVDD 2.3 5.5 V

5

I

AA

5

I

DD

IAA + I

DD

5

3.8 5 mA

2.0 3 mA

5.8 8 mA

IDD Code Dependent. See TPC 2.

Low Power Sleep Mode 0.5 mA DAC Powered Down,

MCLK Running

NOTES

1

Operating temperature range is as follows: B Version: –40∞C to +105∞C, typical specifications are at 25∞ C.

2

For compliance, with specified load 200 W, I

3

Guaranteed by design.

4

Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.

5

Measured with the digital inputs static and equal to 0 V or DVDD.

Specifications subject to change without notice.

full scale should not exceed 4 mA.

OUT

/4096
/4096

/50
/50

/4096

REV. 0–2–

100nF

10nF

R

SET

6.8k⍀

AD9834

Figure 1. Test Circuit Used to Test the Specifications

TIMING CHARACTERISTICS

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8 min

t

8 max

t

9

t

10

t

11

t

11A

t

12

1

Guaranteed by design, not production tested.

20 ns min MCLK Period
8 ns min MCLK High Duration
8 ns min MCLK Low Duration
25 ns min SCLK Period
10 ns min SCLK High Duration
10 ns min SCLK Low Duration
5 ns min FSYNC to SCLK Falling Edge Setup Time
10 ns min FSYNC to SCLK Hold Time
t4–5 ns max
5 ns min Data Setup Time
3 ns min Data Hold Time
8 ns min FSELECT, PSELECT Setup Time before MCLK Rising Edge
8 ns min FSELECT, PSELECT Setup Time after MCLK Rising Edge
5 ns min SCLK High to FSYNC Falling Edge Setup Time

MIN

to T

COMP

IOUT

AVDD

R

LOAD

200⍀

10nF

20pF

CAP/2.5V

REGULATOR

AD9834

1

(DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

ON-BOARD

REFERENCE

12

SIN

ROM

REFOUT

FS ADJUST

FULL-SCALE

CONTROL

10-BIT DAC

SCLK

FSYNC

SDATA

t

12

t

1

MCLK

t

2

t

3

Figure 2. Master Clock

MCLK

t

11A

VALID DATA

FSELECT,

PSELECT

VALID DATA

t

11

VALID DATA

Figure 3. Control Timing

t

5

t

7

D15 D14 D2 D1 D0 D15 D14

t

6

t

4

t

8

t

10

t

9

Figure 4. Serial Timing

REV. 0

–3–

AD9834

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

(TA = 25∞C, unless otherwise noted.)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40∞C to +105∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150∞C

FS ADJUST

REFOUT

CAP/2.5V

FSELECT

PSELECT

COMP

AVDD

DVDD

DGND

MCLK

1

2

3

4

AD9834

5

TOP VIEW

(Not to Scale)

6

7

8

9

10

20

IOUTB

19

IOUT

18

AGND

17

VIN

16

SIGN BIT OUT

15

FSYNC

14

SCLK

13

SDATA

12

SLEEP

11

RESET

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 143∞C/W

␪

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 45∞C/W

␪

JC

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300∞C

IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . 220∞C

* Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9834BRU –40∞C to +105∞C 20-Lead TSSOP (Thin Shrink Small Outline Package) RU-20
EVAL-AD9834EB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD9834
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.

REV. 0–4–

PIN FUNCTIONS DESCRIPTIONS

Pin Number Mnemonic Function

Analog Signal and Reference

1FS ADJUST Full-Scale Adjust Control. A resistor (R

SET

determines the magnitude of the full-scale DAC current. The relationship between R
full-scale current is as follows:

AD9834

) is connected between this pin and AGND. This

and the

SET

IOUT V /R

FULL SCALE REFOUT SET

VVnominal, R typical

REFOUT SET

==120 68..kW

=¥18

2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is made available at

this pin.
3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
17 VIN Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal

DAC output. The DAC output should be filtered appropriately before being applied to the

comparator to improve jitter. When bits OPBITEN and SIGNPIB in the control register are set

to “1,” the comparator input is connected to VIN.
19, 20 IOUT, IOUTB Current Output. This is a high impedance current source. A load resistor of nominally 200 W

should be connected between IOUT and AGND. IOUTB should preferably be tied through an

external load resistor of 200 W to AGND, but can be tied directly to AGND. A 20 pF capacitor to

AGND is also recommended to prevent clock feedthrough.

Power Supply

4 AVDD Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V.

A 0.1 mF decoupling capacitor should be connected between AVDD and AGND.
5 DVDD Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V.

A 0.1 mF decoupling capacitor should be connected between DVDD and DGND.
6 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD

using an on-board regulator (when DVDD exceeds 2.7 V). The regulator requires a decoupling

capacitor of typically 100 nF that is connected from CAP/2.5V to DGND. If DVDD is equal to

or less than 2.7 V, CAP/2.5V should be shorted to DVDD.
7 DGND Digital Ground.
18 AGND Analog Ground.

Digital Interface and Control

8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency

of MCLK. The output frequency accuracy and phase noise are determined by this clock.
9 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used

in the phase accumulator. The frequency register to be used can be selected using the pin FSELECT

or the bit FSEL. When the bit FSEL is being used to select the frequency register, this pin,

FSELECT, should be tied to CMOS high or low.
10 PSELECT Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to

the phase accumulator output. The phase register to be used can be selected using the pin

PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL, this

pin, PSELECT, should be tied to CMOS high or low.
11 RESET Active High Digital Input. RESET resets appropriate internal registers to zero, which corresponds

to an analog output of midscale. RESET does not affect any of the addressable registers.
12 SLEEP Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the

same function as control bit SLEEP12.
13 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
14 SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.
15 FSYNC Active Low Control Input. This is the frame synchronization signal for the input data. When

FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
16 SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the

NCO can be output on this pin. Setting bit OPBITEN in the control register to “1” enables this

output pin. Bit SIGNPIB determines whether the comparator output or the MSB from the NCO

is output on the pin.

REV. 0

–5–

AD9834–Typical Performance Characteristics

2.5

2.0

1.5

– mA

1.0

DD

I

0.5

0

TA = 25ⴗC

15

5

MCLK FREQUENCY – MHz

25

5V

3V

35

45

TPC 1. Typical Current Consumption
vs. MCLK Frequency

–60

AVD D = DVDD = 3V
T

= 25ⴗC

A

–65

–70

–75

SFDR dB MCLK/7

SFDR – dBc

–80

–85

–90

051015 20 25 30 35 40 45 50

MCLK Frequency MHz

SFDR dB MCLK/50

TPC 4. Wideband SFDR vs.
MCLK Frequency

4.0
TA = 25ⴗC

3.5

3.0

2.5

2.0

– mA

DD

1.5

I

1.0

0.5

0

1k 10k 100k 1M 10M 100M

100

f

OUT

TPC 2. Typical IDD vs. f

= 50 MHz

f

MCLK

0

AV DD = DVDD = 3V

= 25ⴗC

T

–10

A

–20

–30

–40

–50

SFDR – dBc

–60

–70

–80

0.001 0.01 1000.1 1.0 10

30 MHz CLOCK

f

OUT

TPC 5. Wideband SFDR vs. f

5V

– Hz

50 MHz CLOCK

/

f

MCLK

OUT

OUT/fMCLK

for Various MCLK Frequencies

3V

for

–60

AVDD = DVDD = 3V
T

= 25ⴗC

A

–65

–70

–75

SFDR dB MCLK/7

SFDR – dBc

–80

–85

–90

05010 20 30 40

MCLK Frequency – MHz

SFDR dB MCLK/50

TPC 3. Narrow-Band SFDR
vs. MCLK Frequency

–40

TA = 25ⴗC
AVD D = DVDD = 3V

–45

–50

–55

SNR – dB

–60

–65

–70

= MCLK/4096

F

OUT

1.0 5.0 10 12.5

MCLK Frequency – MHz

25

TPC 6. SNR vs. MCLK Frequency

50

1000

950

900

850

800

750

700

650

WAKE-UP TIME – ␮ s

600

550

500

–40 25 105

5.5V

TEMPERATURE – ⴗC

2.3V

TPC 7. Wake-Up Time vs.
Temperature

1.250

1.225

1.200

– V

)

1.175

REFOUT

(

1.150

V

1.125

1.100
–40 105

TPC 8. V

TEMPERATURE – ⴗC

REFOUT

UPPER RANGE

LOWER RANGE

25

vs. Temperature

–100

AVDD = DVDD = 5V

–110

–120

–130

dBc/Hz

–140

–150

–160

100 100K1k 10k 200K

T

FREQUENCY – Hz

= 25ⴗC

A

TPC 9. Output Phase Noise,
f

= 2 MHz, MCLK = 50 MHz

OUT

REV. 0–6–