Analog Devices AD9833 a Datasheet
Low Power 20 mW 2.3 V to 5.5 V
a
FEATURES
Digitally Programmable Frequency and Phase
20 mW Power Consumption at 3 V
0 MHz to 12.5 MHz Output Frequency Range
28-Bit Resolution (0.1 Hz @ 25 MHz Ref Clock)
Sinusoidal/Triangular/Square Wave Outputs
2.3 V to 5.5 V Power Supply
No External Components Required
3-Wire SPI
Extended Temperature Range: –40ⴗC to +105ⴗC
Power-Down Option
10-Lead MSOP Package
APPLICATIONS
Frequency Stimulus/Waveform Generation
Liquid and Gas Flow Measurement
Sensory Applications—Proximity, Motion, and Defect
Detection
Line Loss/Attenuation
Test and Medical Equipment
Sweep/Clock Generators
TDR
®
Interface
Programmable Waveform Generator
AD9833
GENERAL DESCRIPTION
The AD9833 is a low power programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry applications. The output
frequency and phase are software programmable, allowing easy
tuning. No external components are needed. The frequency registers are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz
can be achieved. Similarly, with a 1 MHz clock rate, the AD9833
can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This allows
sections of the device that are not being used to be powered down,
thus minimizing the current consumption of the part, e.g., the DAC
can be powered down when a clock output is being generated.
The AD9833 is available in a 10-lead MSOP package.
MCLK
AGND
FREQ0 REG
FREQ1 REG
SERIAL INTERFACE
FSYNC
DGND
AVD D/
DVDD
MUX
AND
CONTROL LOGIC
SCLK
VDD
REGULATOR
ACCUMULATOR
PHASE0 REG
PHASE1 REG
CONTROL REGISTER
SDATA
FUNCTIONAL BLOCK DIAGRAM
CAP/2.5V
2.5V
PHASE
(28-BIT)
MUX
12
⌺
DIVIDE
BY 2
SIN
ROM
MUX
AD9833
ON-BOARD
REFERENCE
MUX
MSB
FULL-SCALE
CONTROL
10-BIT DAC
200⍀
COMP
VOUT
R
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9833–SPECIFICATIONS
(VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = T
*
VOUT, unless otherwise noted.)
MIN
to T
MAX
, R
= 6.8 k⍀ for
SET
Parameter Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate 25 MSPS
Max 0.65 V
V
OUT
Min 38 mV
V
OUT
TC 200 ppm/∞C
V
OUT
DC Accuracy
Integral Nonlinearity ± 1.0 LSB
Differential Nonlinearity ± 0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio 55 60 dB
Total Harmonic Distortion –66 –56 dBc f
f
= 25 MHz, f
MCLK
= 25 MHz, f
MCLK
OUT
OUT
= f
=
MCLK
f
MCLK
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist) –60 dBc f
Narrow Band (± 200 kHz) –78 dBc f
= 25 MHz, f
MCLK
= 25 MHz, f
MCLK
OUT
OUT
= f
= f
MCLK
MCLK
Clock Feedthrough –60 dBc
Wake-Up Time 1 ms
LOGIC INPUTS
V
, Input High Voltage 1.7 V 2.3 V to 2.7 V Power Supply
INH
2.0 V 2.7 V to 3.6 V Power Supply
2.8 V 4.5 V to 5.5 V Power Supply
, Input Low Voltage 0.5 V 2.3 V to 2.7 V Power Supply
V
INL
0.7 V 2.7 V to 3.6 V Power Supply
0.8 V 4.5 V to 5.5 V Power Supply
I
, Input Current 10 mA
INH/IINL
CIN, Input Capacitance 3 pF
POWER SUPPLIES
f
= 25 MHz, f
MCLK
OUT
= f
MCLK
VDD 2.3 5.5 V
I
DD
4.5 5.5 mA
IDD Code Dependent. See TPC 2.
Low Power Sleep Mode 0.5 mA DAC Powered Down,
MCLK Running
*Operating temperature range is as follows: B Version: –40∞C to +105∞C; typical specifications are at 25∞ C.
Specifications subject to change without notice.
/4096
/4096
/50
/50
/4096
100nF
10nF
CAP/2.5V
REGULATOR
AD9833
12
SIN
ROM
COMP
10-BIT DAC
Figure 1. Test Circuit Used to Test Specifications
VDD
VOUT
20pF
REV. A–2–
AD9833
TIMING CHARACTERISTICS
Parameter Limit at T
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8 min
t
8 max
t
9
t
10
t
11
*Guaranteed by design, not production tested.
Specifications subject to change without notice.
40 ns min MCLK Period
16 ns min MCLK High Duration
16 ns min MCLK Low Duration
25 ns min SCLK Period
10 ns min SCLK High Duration
10 ns min SCLK Low Duration
5 ns min FSYNC to SCLK Falling Edge Setup Time
10 ns min FSYNC to SCLK Hold Time
t4 – 5 ns max
5 ns min Data Setup Time
3 ns min Data Hold Time
5 ns min SCLK High to FSYNC Falling Edge Setup Time
MIN
to T
*
(VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.)
MAX
Unit Test Conditions/Comments
t
1
MCLK
t
2
t
3
Figure 2. Master Clock
SCLK
FSYNC
SDATA
t
11
t
7
D15 D14 D2 D1 D0 D15 D14
t
5
t
6
t
4
t
8
t
10
t
9
Figure 3. Serial Timing
–3–REV. A
AD9833
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
CAP/2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V
Digital I/O Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40∞C to +105∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150∞C
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD9833BRM –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
EVAL-AD9833EB Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD9833
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
MSOP Package
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206∞C/W
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44∞C/W
JC
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300∞C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
REV. A–4–
PIN CONFIGURATION
AD9833
COMP
VDD
CAP/2.5V
DGND
MCLK
1
2
AD9833
3
TOP VIEW
(Not to Scale)
4
5
10
9
8
7
6
VOUT
AGND
FSYNC
SCLK
SDATA
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Function
Power Supply
2 VDD Positive Power Supply for the Analog and the Digital Interface Sections. The
on-board 2.5 V regulator is also supplied from VDD. VDD can have a value
from 2.3 V to 5.5 V. A 0.1 mF and a 10 mF decoupling capacitor should be
connected between VDD and AGND.
3 CAP/2.5 V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated
from VDD using an on-board regulator (when VDD exceeds 2.7 V). The
regulator requires a decoupling capacitor of typically 100 nF, which is connected
from CAP/2.5 V to DGND. If VDD is equal to or less than 2.7 V, CAP/2.5 V
should be tied directly to VDD.
4 DGND Digital Ground.
9 AGND Analog Ground.
Analog Signal and Reference
1 COMP A DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
10 VOUT Voltage Output. The analog and digital output from the AD9833 is available at
this pin. An external load resistor is not required because the device has a
200 W resistor on board.
Digital Interface and Control
5 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction
of the frequency of MCLK. The output frequency accuracy and phase noise
are determined by this clock.
6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
7 SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.
8 FSYNC Active Low Control Input. This is the frame synchronization signal for the input
data. When FSYNC is taken low, the internal logic is informed that a new word is
being loaded into the device.
REV. A
–5–
AD9833–Typical Performance Characteristics
5.5
TA = 25ⴗC
5.0
4.5
(mA)
DD
I
4.0
3.5
3.0
051015 20 25
5V
3V
MCLK (MHz)
TPC 1. Typical Current Consumption
vs. MCLK Frequency
–40
VDD = 3V
T
= 25ⴗC
A
–45
–50
SFDR dB MCLK/7
–55
SFDR (dBc)
–60
–65
–70
5791113151719212325
SFDR dB MCLK/50
MCLK FREQUENCY (MHz)
TPC 4. Wideband SFDR vs.
MCLK Frequency
5.5
TA = 25ⴗC
f
f
OUT
OUT
/
5V
3V
(Hz)
OUT
MCLK 18MHz
MCLK 25MHz
f
MCLK
5.0
4.5
(mA)
DD
I
4.0
3.5
3.0
110100 1k 10k 100k 1M
TPC 2. Typical IDD vs. f
f
= 25 MHz
MCLK
0
VDD = 3V
= 25ⴗC
T
–10
A
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0.001 0.01 0.1 1
MCLK 10MHz
MCLK 1MHz
TPC 5. Wideband SFDR vs.
f
OUT/fMCLK
for Various MCLK
Frequencies
for
10 100
–60
AVDD = 3V
T
= 25ⴗC
A
–65
–70
–75
SFDR dB MCLK/7
–80
SFDR (dBc)
–85
–90
0 25 5101520
MCLK FREQUENCY (MHz)
SFDR dB MCLK/50
TPC 3. Narrow-Band SFDR
vs. MCLK Frequency
–40
= 25ⴗC
T
A
VDD = 3V
–45
–50
–55
SNR (dB)
–60
–65
–70
f
= MCLK/4096
OUT
1.0 5.0 10 12.5
MCLK FREQUENCY (MHz)
TPC 6. SNR vs. MCLK Frequency
25
1000
950
900
850
800
750
700
650
WAKE-UP TIME (s)
600
550
500
–40 25 105
5.5V
TEMPERATURE (ⴗC)
2.3V
TPC 7. Wake-Up Time vs.
Temperature
1.250
1.225
1.200
(V)
1.175
REFOUT
1.150
V
1.125
1.100
–40 105
TPC 8. V
TEMPERATURE (ⴗC)
REFOUT
UPPER RANGE
LOWER RANGE
25
vs. Temperature
REV. A–6–
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