Analog Devices AD9831 Datasheet
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
CMOS
Complete DDS
AD9831
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
3 V/5 V Power Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
Powerdown Option
72 dB SFDR
125 mW (5 V) Power Consumption
40 mW (3 V) Power Consumption
48-Pin TQFP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
This DDS device is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the parallel microprocessor
interface.
A powerdown pin allows external control of a powerdown
mode. The part is available in a 48-pin TQFP package.
FUNCTIONAL BLOCK DIAGRAM
RESET
SLEEP
IOUT
COMP
REFINFS ADJUST
REFOUT
AGND
AVDDDGND
DVDD
MCLK
D0
FSELECT
D15 WR A0 A1 A2
PSEL0
PSEL1
12
Σ
AD9831
ON-BOARD
REFERENCE
10-BIT DAC
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
TRANSFER CONTROL
MPU INTERFACE
FULL-SCALE
CONTROL
SIN
ROM
PHASE
ACCUMULATOR
(32-BIT)
MUX
FREQ0 REG
FREQ1 REG
MUX
PARALLEL REGISTER
REV. A
–2–
AD9831–SPECIFICA TIONS
1
Parameter AD9831A Units Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate (f
MAX
) 25 MSPS nom
I
OUT
Full Scale 4 mA nom
5 mA max
Output Compliance 1.5 V max
DC Accuracy
Integral Nonlinearity ± 1 LSB typ
Differential Nonlinearity ± 0.5 LSB typ
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal to Noise Ratio 50 dB min f
MCLK
= 25 MHz, f
OUT
= 1 MHz
Total Harmonic Distortion –53 dBc max f
MCLK
= 25 MHz, f
OUT
= 1 MHz
Spurious Free Dynamic Range (SFDR)
3
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
Narrow Band (±50 kHz) –72 dBc min 5 V Power Supply
–70 dBc min 3 V Power Supply
Wide Band (±2 MHz) –50 dBc min
Clock Feedthrough –60 dBc typ
Wake-Up Time
4
1 ms typ
Powerdown Option Yes
VOLTAGE REFERENCE
Internal Reference @ +25°C 1.21 Volts typ
T
MIN
to T
MAX
1.21 ± 7% Volts min/max
REFIN Input Impedance 10 MΩ typ
Reference TC 100 ppm/°C typ
REFOUT Output Impedance 300 Ω typ
LOGIC INPUTS
V
INH
, Input High Voltage VDD – 0.9 V min
V
INL
, Input Low Voltage 0.9 V max
I
INH
, Input Current 10 µA max
CIN, Input Capacitance 10 pF max
POWER SUPPLIES
AVDD 2.97/5.5 V
min/V max
DVDD 2.97/5.5 V
min/V max
I
AA
12 mA max 5 V Power Supply
I
DD
2.5 + 0.33/MHz mA typ 5 V Power Supply
I
AA
+ I
DD
5
15 mA max 3 V Power Supply
24 mA
max 5 V Power Supply
Low Power Sleep Mode
6
1 mA max 1 MΩ Resistor Tied Between REFOUT and AGND
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85 °C.
2
100% production tested.
3
f
MCLK
= 6.25 MHz, Frequency Word = 5671C71C HEX, f
OUT
= 2.11 MHz.
4
See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
6
The Low Power Sleep Mode current is typically 2 mA when a 1 M Ω resistor is not tied between REFOUT and AGND.
The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
(VDD = +3.3 V 6 10%; +5 V 6 10%; AGND = DGND = 0 V; TA = T
MIN
to T
MAX
; REFIN =
REFOUT; R
SET
= 3.9 kV; R
LOAD
= 300 V for IOUT unless otherwise noted)
IOUT
COMP
REFIN
FS
ADJUST
REFOUT
12
AD9831
ON-BOARD
REFERENCE
10-BIT DAC
SIN
ROM
FULL-SCALE
CONTROL
300Ω 50pF
R
SET
3.9kΩ
10nF
10nF
AVDD
Figure 1. Test Circuit with Which Specifications Are Tested
AD9831
–3–
REV. A
TIMING CHARACTERISTICS
(VDD = +3.3 V 6 10%, +5 V 6 10%; AGND = DGND = 0 V, unless otherwise noted)
Limit at
T
MIN
to T
MAX
Parameter (A Version) Units Test Conditions/Comments
t
1
40 ns min MCLK Period
t
2
16 ns min MCLK High Duration
t
3
16 ns min MCLK Low Duration
t
4
* 8 ns min WR Rising Edge to MCLK Rising Edge
t
4A
* 8 ns min WR Rising Edge After MCLK Rising Edge
t
5
8 ns min WR Pulse Width
t
6
t
1
ns min Duration between Consecutive WR Pulses
t
7
5 ns min Data/Address Setup Time
t
8
3 ns min Data/Address Hold Time
t
9
* 8 ns min FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
t
9A
* 8 ns min FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
t
10
t
1
ns min RESET Pulse Duration
*See Pin Description section.
Guaranteed by design but not production tested.
t
1
t
4
MCLK
WR
t
2
t
3
t
4A
t
6
t
5
Figure 2. Clock Synchronization Timing
A0, A1, A2
DATA
WR
t
8
t
5
t
7
t
6
VALID DATA
VALID DATA
Figure 3. Parallel Timing
VALID DATA VALID DATA VALID DATA
MCLK
FSELECT
PSEL0, PSEL1
RESET
t
9
t
10
t
9A
Figure 4. Control Timing
AD9831
–4–
REV. A
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
AD9831AST –40°C to +85°C 48-Pin TQFP ST-48
EVAL-AD9831EB Evaluation Board
*ST = Thin Quad Flatpack (TQFP).
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
TQFP θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
48 47 46 45 44 39 38 3743 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
AVDD
FS ADJUST
IOUT
NC
AGND
NC
COMP
AVDD
NC
AVDD
REFIN
AGND
RESET
A0
A1
A2
DB0
DB1
DGND
DB2
DB3
DB4
DVDD
AGND
REFOUT
SLEEP
DVDD
DVDD
DGND
MCLK
WR
DVDD
FSELECT
PSEL0
PSEL1
NC = NO CONNECT
DB9
DB11
DGND
DB15
DB14
DB13
DB12
DB10
DB8
DB7
DB6
DB5
AD9831
AD9831
–5–
REV. A
PIN DESCRIPTION
Mnemonic Function
POWER SUPPLY
AVDD Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
AGND Analog Ground.
DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
DGND Digital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUST Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
= 12.5 × V
REFIN/RSET
V
REFIN
= 1.21 V nominal, R
SET
= 3.9 kΩ typical
REFIN Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831
accepts a reference of 1.21 V nominal.
REFOUT Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one
MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change
on FSELECT should not coincide with an MCLK rising edge.
WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded
into the AD9831 on the rising edge of the
WR pulse. This data is then loaded into the destination register on the
MCLK rising edge. The
WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The
WR rising
edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the
MCLK rising edge. Alternatively, the
WR rising edge can occur after the MCLK rising edge and the destination
register will be loaded on the next MCLK rising edge.
D0–D15 Data Bus, Digital Inputs for destination registers.
A0–A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being
input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the
inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising
edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase
register.
SLEEP Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by taking
SLEEP high.
RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
Loading...