ANALOG DEVICES AD9826 Service Manual
Complete 16-Bit Imaging
a
FEATURES
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
1~6ⴛ Programmable Gain
ⴞ300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
Signal Processor
AD9826
PRODUCT DESCRIPTION
The AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
The AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
The CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single byte output mode. The internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
The AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
VINR
VING
VINB
OFFSET
AVDD AVSS
CDS
CDS
CDS
INPUT
CLAMP
BIAS
CML
9-BIT
9-BIT
9-BIT
DAC
DAC
DAC
CAPT
PGA
PGA
PGA
CAPB
6
RED
9
GREEN
BLUE
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
AVSS
AVDD
BANDGAP
REFERENCE
3:1
MUX
CONFIGURATION
REGISTER
MUX
REGISTER
RED
GREEN
GAIN
BLUE
REGISTERS
OFFSET
REGISTERS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
16-BIT
ADC
ADCCLKCDSCLK2CDSCLK1
DRVDD DRVSS
AD9826
16
16:8
MUX
DIGITAL
CONTROL
INTERFACE
OEB
8
DOUT
SCLK
SLOAD
SDATA
AD9826–SPECIFICA TIONS
(T
to T
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
MAX
ANALOG SPECIFICATIONS
MIN
Gain = 1, Input range = 4 V p-p, unless otherwise noted.)
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS 30 MSPS
2-Channel Mode with CDS 30 MSPS
1-Channel Mode with CDS 18 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 16 Bits
Integral Nonlinearity (INL) ±16 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
No Missing Codes Guaranteed
ANALOG INPUTS
Input Signal Range (Programmable)
Allowable Reset Transient
Input Limits
2
1
1
2.0/4.0 V p-p
1.0 V
AVSS – 0.3 AVDD + 0.3 V
Input Capacitance 10 pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain 1 6 V/V
PGA Gain Resolution
2
64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset –300 +300 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity Guaranteed
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum 3.0 LSB rms
Total Output Noise @ PGA Maximum 9.0 LSB rms
Channel-to-Channel Crosstalk
@ 15 MSPS 70 dB
@ 6 MSPS 90 dB
POWER SUPPLY REJECTION
AVDD = 5 V 0.25 V 0.1 % FSR
DIFFERENTIAL VREF (at 25°C)
CAPT–CAPB 2.0 V
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –65 +150 °C
POWER SUPPLIES
AVDD 4.75 5.0 5.25 V
DRVDD 3.0 5.0 5.25 V
OPERATING CURRENT
AVDD 75 mA
DRVDD 5 mA
Power-Down Mode 200 µA
POWER DISSIPATION
3-Channel Mode 400 mW
1-Channel Mode 300 mW
NOTES
1
Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.
4V SET BY INPUT CLAMP
1V TYP
RESET TRANSIENT
2
The PGA Gain is approximately “linear in dB” and follows the equation:
Specifications subject to change without notice.
(3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
ain=
1+5.0
6.0
where G is the register value.
63 – G
63
G
ADCCLK
= 15 MHz, f
CDSCLK1
= f
= 5 MHz, PGA
CDSCLK2
–2–
REV. A
AD9826
(T
to T
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
MAX
DIGITAL SPECIFICATIONS
MIN
CL = 10 pF, unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Input Capacitance C
IH
IL
IH
IL
IN
2.0 V
LOGIC OUTPUTS
High Level Output Voltage V
Low Level Output Voltage V
High Level Output Current I
Low Level Output Current I
OH
OL
OH
OL
4.5 V
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (I
= 50 µA) V
OH
Low Level Output Voltage (IOL = 50 µA) V
Specifications subject to change without notice.
(T
to T
TIMING SPECIFICATIONS
MIN
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
MAX
OH
OL
2.95 V
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
3-Channel Pixel Rate t
1-Channel Pixel Rate t
ADCCLK Pulsewidth t
CDSCLK1 Pulsewidth t
CDSCLK2 Pulsewidth t
CDSCLK1 Falling to CDSCLK2 Rising t
ADCCLK Falling to CDSCLK2 Rising t
CDSCLK2 Rising to ADCCLK Rising t
CDSCLK2 Falling to ADCCLK Falling t
CDSCLK2 Falling to CDSCLK1 Rising t
Aperture Delay for CDS Clocks t
PRA
PRB
ADCLK
C1
C2
C1C2
ADC2
C2ADR
C2ADF
C2C1
AD
200 ns
80 ns
30 ns
8ns
8ns
0ns
0ns
5ns
30 ns
5ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SLOAD to SCLK Set-Up Time t
SCLK to SLOAD Hold Time t
SDATA to SCLK Rising Set-Up Time t
SCLK Rising to SDATA Hold Time t
SCLK Falling to SDATA Valid t
SCLK
LS
LH
DS
DH
RDV
10 MHz
10 ns
10 ns
10 ns
10 ns
10 ns
DATA OUTPUTS
Output Delay t
3-State to Data Valid t
Output Enable High to 3-State t
OD
DV
HZ
Latency (Pipeline Delay) 3 (Fixed) Cycles
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
0.8 V
10 µA
10 µA
10 pF
0.1 V
50 µA
50 µA
0.05 V
2ns
6ns
10 ns
10 ns
REV. A
–3–
AD9826
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V
DRVDD DRVSS –0.5 +6.5 V
AVSS DRVSS –0.3 +0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature 300 °C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Model Range Description Option
AD9826KRS –40°C to +85°C 5.3 mm SSOP RS-28
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θ
= 109°C/W
JA
θ
= 39°C/W
JC
ORDERING GUIDE
Temperature Package Package
–4–
REV. A
PIN CONFIGURATION
AD9826
OEB
DRVDD
DRVSS
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
AD9826
7
TOP VIEW
8
(Not to Scale)
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVD D
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVD D
SLOAD
SCLK
SDATA
CDSCLK1
CDSCLK2
ADCCLK
(MSB) D7
(LSB) D0
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 CDSCLK1 DI CDS Reference Level Sampling Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
8 D6 DO Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
9 D5 DO Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
10 D4 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
11 D3 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
12 D2 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
13 D1 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
14 D0 DO Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18, 28 AVDD P 5 V Analog Supply
19, 27 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage Decoupling
21 CAPT AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. A
–5–
AD9826
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a level
1 1/ 2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed
to 16-bit resolution indicates that all 65536 codes, respectively, must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the
ideal level.
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation o f the actual difference between first and last
code transitions and the ideal difference between the first and
last code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and can be converted to an equivalent voltage, using the
relationship 1 LSB = 4 V/65536 = 61 µV. The noise may then
be referred to the input of the AD9826 by dividing by the
PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-tochannel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9826, one channel is grounded and the other two channels are exercised with full scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
–6–
REV. A
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