Analog Devices AD9814 Datasheet

Complete 14-Bit

FEATURES 14-Bit 10 MSPS A/D Converter No Missing Codes Guaranteed 3-Channel Operation Up to 10 MSPS 1-Channel Operation Up to 7 MSPS Correlated Double Sampling 1-6x Programmable Gain ⴞ300 mV Programmable Offset Input Clamp Circuitry Internal Voltage Reference Multiplexed Byte-Wide Output (8+6 Format) 3-Wire Serial Digital Interface +3/+5 V Digital I/O Compatibility 28-Lead SOIC Package Low Power CMOS: 330 mW (Typ) Power-Down Mode: <1 mW

APPLICATIONS Flatbed Document Scanners Film Scanners Digital Color Copiers Multifunction Peripherals

CCD/CIS Signal Processor

AD9814

PRODUCT DESCRIPTION

The AD9814 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 14bit A/D converter.

The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS.

The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode.

The AD9814 operates from a single +5 V power supply, typically consumes 330 mW of power, and is packaged in a 28-lead SOIC.

VINR

VING

VINB

OFFSET

CDS

INPUT

CLAMP

BIAS

FUNCTIONAL BLOCK DIAGRAM

PGACDS

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

PGA

PGACDS

3:1

MUX

RED

GREEN

BLUE

RED

GREEN

BLUE

BANDGAP

REFERENCE

14-BIT

ADC

CONFIGURATION

MUX

GAIN REGISTERS

OFFSET REGISTERS

DRVDD DRVSSAVDD AVSSCAPT CAPBAVDD AVSS CML

ADCCLKCDSCLK2CDSCLK1

AD9814

14:8 MUX

DIGITAL

CONTROL

INTERFACE

OEB

DOUT

SCLK

SLOAD

SDATA

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

AD9814–SPECIFICATIONS

to T

ANALOG SPECIFICATIONS

MIN

, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f

MAX

2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)

J-Grade K-Grade

Parameter Min Typ Max Min Typ Max Units

CONVERSION RATE

3-Channel Mode with CDS 6 10 6 10 MSPS 1-Channel Mode with CDS 6 7 6 7 MSPS

ACCURACY (Entire Signal Path)

ADC Resolution 14 14 Bits Integral Nonlinearity

INL @ 10 MHz +4.0/–7.0 +4.0/–7.0 LSB

Differential Nonlinearity (DNL) +0.6/–0.5 +0.6/–0.5 ±1.0 LSB

DNL @ 10 MHz +0.8/–0.6 +0.8/–0.6 LSB

No Missing Codes Guaranteed 13 14 Bits

Offset Error –12 –12 ±104 mV

Gain Error

ANALOG INPUTS

Input Signal Range Allowable Reset Transient Input Limits Input Capacitance 10 10 pF Input Bias Current 10 10 nA

AMPLIFIERS

PGA Gain at Minimum 1 1 V/V PGA Gain at Maximum 5.8 5.8 V/V PGA Resolution 64 64 Steps PGA Monotonicity Guaranteed Guaranteed Programmable Offset at Minimum –300 –300 mV Programmable Offset at Maximum +300 +300 mV Programmable Offset Resolution 512 512 Steps Programmable Offset Monotonicity Guaranteed Guaranteed

NOISE AND CROSSTALK

Input Referred Noise @ PGA Min 130 130 µV rms

Total Output Noise @ PGA Min 0.55 0.55 LSB rms

Input Referred Noise @ PGA Max 84 84 µV rms

Total Output Noise @ PGA Max 2.0 2.0 LSB rms Channel-Channel Crosstalk <1 <1 LSB

POWER SUPPLY REJECTION

AVDD = +5 V ± 0.25 V 0.07 0.07 0.3 % FSR

Differential VREF (@ +25°C)

CAPT-CAPB (4 V Input Range) 2.0 1.9 2.0 2.1 V CAPT-CAPB (2 V Input Range) 1.0 0.94 1.0 1.06 V

TEMPERATURE RANGE

Operating 0 +70 0 +70 °C Storage –65 +150 –65 +150 °C

POWER SUPPLIES

AVDD +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V DRVDD +3.0 +5.0 +5.25 +3.0 +5.0 +5.25 V Total Operating Current

AVDD 64 64 80 mA DRVDD 1.8 1.8 10 mA

Power-Down Mode Current 150 150 µA

Power Dissipation 330 330 450 mW Power Dissipation @ 10 MHz 355 355 mW Power Dissipation (1-Channel Mode) 220 220 265 mW

(INL) +2.5/–6.0 +2.5/–6.0 ±11.0 LSB

2.2 2.2 ±5.3 % FSR

AVSS – 0.3 AVDD + 0.3 AVSS – 0.3 AVDD + 0.3 V

4.0 4.0 V p-p

1.0 1.0 V

ADCCLK

= 6 MHz, f

CDSCLK1

= f

CDSCLK2

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AD9814

NOTES

The Integral Nonlinearity in measured using the “fixed endpoint” method, NOT using a “best-fit” calculation. See Definitions of Specifications.

The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.

Linear input signal range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9814’s input clamp. A larger reset transient can be tolerated by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.

The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device. Signals beyond the input limits will turn on the overvoltage protection diodes.

The PGA Gain is approximately “linear in dB” and follows the equation:

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

1V TYP

RESET TRANSIENT

to T

MIN

CL = 10 pF, unless otherwise noted.)

4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)

4V p-p MAX INPUT SIGNAL RANGE

GND

148

.[ ]

63 –G

Gain =

[

, AVDD = +5 V, DRVDD = +5 V, CDS Mode, f

MAX

where G is the register value. See Figure 13.

]

ADCCLK

= 6 MHz, f

CDSCLK1

= f

CDSCLK2

= 2 MHz,

Parameter Symbol Min Typ Max Units

LOGIC INPUTS

High Level Input Voltage V Low Level Input Voltage V High Level Input Current I Low Level Input Current I Input Capacitance C

2.6 V

0.8 V

10 µA 10 µA

10 pF

LOGIC OUTPUTS

High Level Output Voltage V Low Level Output Voltage V High Level Output Current I Low Level Output Current I

Specifications subject to change without notice.

4.5 V

0.1 V

50 µA 50 µA

TIMING SPECIFICATIONS

to T

MIN

, AVDD = +5 V, DRVDD = +5 V)

MAX

Parameter Symbol Min Typ Max Units

CLOCK PARAMETERS

3-Channel Pixel Rate t 1-Channel Pixel Rate t ADCCLK Pulsewidth t CDSCLK1 Pulsewidth t CDSCLK2 Pulsewidth t CDSCLK1 Falling to CDSCLK2 Rising t ADCCLK Falling to CDSCLK2 Rising t CDSCLK2 Rising to ADCCLK Rising t CDSCLK2 Falling to ADCCLK Falling t CDSCLK2 Falling to CDSCLK1 Rising t ADCCLK Falling to CDSCLK1 Rising t Aperture Delay for CDS Clocks t

PRA

PRB

ADCLK

C1C2

ADC2

C2ADR

C2ADF

C2C1

ADC1

300 500 ns 140 ns 45 ns 20 ns 40 ns 0ns 10 ns 10 ns 50 ns 50 ns 0ns

3ns

SERIAL INTERFACE

Maximum SCLK Frequency f SLOAD to SCLK Set-Up Time t SCLK to SLOAD Hold Time t SDATA to SCLK Rising Set-Up Time t SCLK Rising to SDATA Hold Time t SCLK Falling to SDATA Valid t

SCLK

RDV

10 MHz 10 ns 10 ns 10 ns 10 ns 10 ns

DATA OUTPUT

Output Delay t 3-State to Data Valid t Output Enable High to 3-State t

6ns 16 ns 5ns

Latency (Pipeline Delay) 3 (Fixed) Cycles

Specifications subject to change without notice.

REV. 0 –3–

AD9814

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With Respect

Parameter To Min Max Units

VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V Digital Inputs AVSS –0.3 AVDD + 0.3 V AVDD AVSS –0.5 +6.5 V DRVDD DRVSS –0.5 +6.5 V AVSS DRVSS –0.3 +0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V

Junction Temperature +150 Storage Temperature –65 +150

Lead Temperature

(10 sec) +300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

°C

ORDERING GUIDE

Temperature Package

Model Range Description

AD9814JR 0°C to +70°C 28-Lead 300 Mil SOIC AD9814KR 0°C to +70°C 28-Lead 300 Mil SOIC

THERMAL CHARACTERISTICS

Thermal Resistance

28-Lead 300 Mil SOIC

= 71.4°C/W

= 23°C/W

PIN CONFIGURATION

CDSCLK1 AVDD CDSCLK2 AVSS

ADCCLK VINR

(MSB) D7 VINB

(LSB) D0 SDATA

1 2 3 4

OEB OFFSET

DRVDD VING

DRVSS CML

AD9814

TOP VIEW

(Not to Scale)

D6 CAPT

D5 CAPB

D4 AVSS

D3 AVDD

D2 SLOAD

D1 SCLK

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PIN FUNCTION DESCRIPTIONS

Pin N

o. Name Type Description

1 CDSCLK1 DI CDS Reference Level Sampling

Clock 2 CDSCLK2 DI CDS Data Level Sampling Clock 3 ADCCLK DI A/D Converter Sampling Clock 4 OEB DI Output Enable, Active Low 5 DRVDD P Digital Output Driver Supply 6 DRVSS P Digital Output Driver Ground 7 D7 DO Data Output MSB. ADC DB13

High Byte, ADC DB5 Low Byte 8 D6 DO Data Output. ADC DB12 High

Byte, ADC DB4 Low Byte 9 D5 DO Data Output. ADC DB11 High

Byte, ADC DB3 Low Byte 10 D4 DO Data Output. ADC DB10 High

Byte, ADC DB2 Low Byte 11 D3 DO Data Output. ADC DB9 High

Byte, ADC DB1 Low Byte 12 D2 DO Data Output. ADC DB8 High

Byte, ADC DB0 Low Byte 13 D1 DO Data Output. ADC DB7 High

Byte, Don’t Care Low Byte 14 D0 DO Data Output LSB. ADC DB6

High Byte, Don’t Care Low Byte 15 SDATA DI/DO Serial Interface Data Input/Output 16 SCLK DI Serial Interface Clock Input 17 SLOAD DI Serial Interface Load Pulse 18 AVDD P +5 V Analog Supply 19 AVSS P Analog Ground 20 CAPB AO ADC Bottom Reference Voltage

Decoupling 21 CAPT AO ADC Top Reference Voltage

Decoupling 22 VINB AI Analog Input, Blue Channel 23 CML AO Internal Bias Level Decoupling 24 VING AI Analog Input, Green Channel 25 OFFSET AO Clamp Bias Level Decoupling 26 VINR AI Analog Input, Red Channel 27 AVSS P Analog Ground 28 AVDD P +5 V Analog Supply

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9814 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD9814

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity error refers to the deviation of each individual code from a line drawn from “zero scale” through “positive full scale.” The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges.

OFFSET ERROR

The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level.

GAIN ERROR

The last code transition should occur for an analog value 1 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions.

INPUT REFERRED NOISE

The rms output noise is measured using histogram techniques. The ADC output codes’ standard deviation is calculated in LSB, and converted to an equivalent voltage, using the relationship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the input of the AD9814 by dividing by the PGA gain.

CHANNEL-TO-CHANNEL CROSSTALK

In an ideal three channel system, the signal in one channel will not influence the signal level of another channel. The channelto-channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD9814, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB.

APERTURE DELAY

The aperture delay is the time delay that occurs from when a sampling edge is applied to the AD9814 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clock’s falling edge to the instant the actual internal sample is taken.

POWER SUPPLY REJECTION

Power Supply Rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.

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