Analog Devices AD9801 Datasheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

a

AD9801

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

CCD Signal Processor

For Electronic Cameras

FUNCTIONAL BLOCK DIAGRAM

SHP

AD9801

PGA

PGACONT1 PGACONT2

CLAMP

CLPDM

CDS

PBLK

PIN

DIN

SHD ADCCLK

TIMING

GENERATOR

23 29 3019 21 22

16

27

26

37

48 47

18

CMLEVEL VRT VRB STBY

REFERENCE

S/H

20

CLPOB

CLAMP

A/D

2

11

DOUT

33

ACVDD43ADVDD17DVDD

12

DRVDD

10

FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full-Speed CDS
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Pin TQFP Package

PRODUCT DESCRIPTION

The AD9801 is a complete CCD signal processor developed for
electronic cameras. It is well suited for both video conferencing
and consumer level still camera applications.

The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping
circuitry and an onboard voltage reference are also provided.
The AD9801 operates from a single +3 V supply with a typical
power consumption of 185 mW.

The AD9801 is packaged in a space saving 48-pin thin-quad
flatpack (TQFP) and is specified over an operating temperature
range of 0°C to +70°C.

PRODUCT HIGHLIGHTS

1. On-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac coupling to interface a CCD sensor at full
18 MSPS conversion rate.

2. On-Chip PGA
The AD9801 includes a low noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).

3. 10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. (Typical DNL is ±0.5 LSB
and no missing code performance is guaranteed.)

4. Low Power
At 185 mW, the AD9801 consumes a fraction of the power of
presently available multichip solutions. The part’s power­down mode (15 mW) further enhances its desirability in low
power, battery operated applications.

5. Digital I/O Functionality
The AD9801 offers three-state digital output control.

6. Small Package
Packaged in a 48-pin, surface-mount thin-quad flatpack, the
AD9801 is well suited to very tight, low headroom designs.

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AD9801–SPECIFICATIONS

(T

MIN

to T

MAX

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless

otherwise noted)

Parameter Min Typ Max Units

TEMPERATURE RANGE

Operating 0 70 °C
Storage –65 150 °C

POWER SUPPLY VOLTAGE

(For Functional Operation)

ACVDD 3.00 3.15 3.50 V
ADVDD 3.00 3.15 3.50 V
DVDD 3.00 3.15 3.50 V
DRVDD 3.00 3.15 3.50 V

POWER SUPPLY CURRENT

ACVDD 39.5 mA
ADVDD 14.6 mA
DVDD 4.7 mA
DRVDD 0.07 mA

POWER CONSUMPTION

Normal Operation 185 mW

Power-Down Mode 15 mW
MAXIMUM SHP, SHD, ADCCLK RATE 18 MHz
ADC

Resolution 10 Bits

Differential Nonlinearity ± 0.5 LSB

No Missing Codes GUARANTEED

ADCCLK Rate 18 MHz

Reference Top Voltage 1.75 V

Reference Bottom Voltage 1.25 V

Input Range 1.0 V p-p
CDS

Maximum Input Signal 500 mV p-p

Pixel Rate 18 MHz
PGA

1

Maximum Gain 31.5 dB

High Gain 15 19 23 dB

Medium Gain 0.5 3.5 6.5 dB

Minimum Gain –5 –1 +3 dB
CLAMP

Average Black Level (During CLPOB. Only

Stable Over PGA Range 0.3 V to 2.7 V) 32 LSB

1

PGA test conditions: max gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain

PGACONT1 =

0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Parameter Symbol Min Typ Max Units

LOGIC INPUTS

High Level Input Voltage V

IH

2.4 V

Low Level Input Voltage V

IL

0.6 V

High Level Input Current I

IH

10 µA

Low Level Input Current I

IL

10 µA

Input Capacitance C

IN

10 pF

LOGIC OUTPUTS

High Level Output Voltage V

OH

2.4 V

Low Level Output Voltage V

OL

0.6 V

I

OH

50 µA

I

OL

50 µA

Specifications subject to change without notice.

(T

MIN

to T

MAX

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)

AD9801

–3–

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TIMING SPECIFICATIONS

Parameter Min Typ Max Units

ADCCLK CLOCK PERIOD 55.6 ns

ADCCLK High Level Period 24.8 27.8 ns
ADCCLK Low Level Period 24.8 27.8 ns
SHP, SHD Clock Period 55.6 ns
Digital Output Delay 20 ns

Digital Output Data Control

Mode1 Mode2 Digital Output Data (D9–D0)

0 0 Normal Operation
0 1 1 0 1 0 1 0 1 0 1 0
1 0 0 1 0 1 0 1 0 1 0 1
1 1 High Impedance

(T

MIN

to T

MAX

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect To Min Max Units

ADVDD ADVSS, SUBST –0.3 6.5 V
ACVDD ACVSS, SUBST –0.3 6.5 V
DVDD DVSS, DSUBST –0.3 6.5 V
DRVDD DRVSS, DSUBST –0.3 6.5 V
SHP, SHD DSUBST –0.3 DVDD + 2.0 V
ADCCLK, CLOB, CLPDM DSUBST –0.3 DVDD + 0.3 V
PGACONT1, PGACONT2 SUBST –0.3 ACVDD + 0.3 V
PIN, DIN SUBST –0.3 ACVDD + 0.3 V
DOUT DSUBST –0.3 DRVDD + 0.3 V
VRT, VRB SUBST –0.3 ADVDD + 0.3 V
CLAMP_BIAS SUBST –0.3 ACVDD + 0.3 V
CCDBYP1, CCDBYP2 SUBST –0.3 ACVDD + 0.3 V
STBY DSUBST –0.3 DVDD + 0.3 V
MODE1, MODE2 SUBST –0.3 ADVDD + 0.3 V
DRVSS, DVSS, ACVSS, ADVSS SUBST, DSUBST –0.3 +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only; functional operation of the device at these or other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Package Description Package Option*

AD9801 0°C to +70°C 48-Pin TQFP ST-48

*ST = Thin Quad Flatpack Package.

AD9801

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Pin No. Pin Name Type Description

1 ADVSS P Analog Ground
2–11 D0–D9 DO Digital Data Outputs
12 DRVDD P +3 V Digital Driver Supply
13 DRVSS P Digital Driver Ground
14 DSUBST P Digital Substrate
15 DVSS P Digital Ground
16 ADCCLK DI ADC Sample Clock Input
17 DVDD P +3 V Digital Supply
18 STBY DI Power down (Active HIGH)
19 PBLK DI Pixel Blanking (Active LOW)
20 CLPOB DI Black Level Restore Clamp (Active LOW)
21 SHP DI Reference Sample Clock Input
22 SHD DI Data Sample Clock Input
23 CLPDM DI Input Clamp (Active Low)
24 DVSS DI Digital Ground
25 CCDBYP2 AO CCD Bypass (Decouple to Analog Ground Through 0.1 µF)
26 DIN AI CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1 µF)
27 PIN AI CDS Input (See Above)
28 CCDBYP1 AO CCD Bypass (Decouple to Analog Ground Through 0.1 µF)
29 PGACONT1 AI Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF)
30 PGACONT2 AI Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF)
31 ACVSS P Analog Ground
32 CLAMP_BIAS AO Clamp Bias Level (Decouple to Analog Ground Through 0.1 µF)
33 ACVDD P +3 V Analog Supply
34 ACVDD AI +3 V Analog Supply
35 ACVDD AI +3 V Analog Supply
36 INT_BIAS1 AO Internal Bias Level (Decouple to Analog Ground Through 0.1 µF)
37 CMLEVEL AO Common-Mode Level (Decouple to Analog Ground Through 0.1 µF)
38 INT_BIAS2 AO Internal Bias Level (Decouple to Analog Ground Through 0.1 µF)
39 MODE2 DI ADC Test Mode Control (See Digital Output Data Control)
40 MODE1 DI ADC Test Mode Control (See Digital Output Data Control)
41 ADVSS P Analog Ground
42 ADVDD P +3 V Analog Supply
43 ADVDD P +3 V Analog Supply
44 ADVSS P Analog Ground
45 ADVSS P Analog Ground
46 SUBST P Substrate (Connect to Analog Ground)
47 VRB AO Bottom Reference Bypass (Decouple to Analog Ground Through 0.1 µF)
48 VRT AO Top Reference Bypass (Decouple to Analog Ground Through 0.1 µF)

PIN CONFIGURATION

24
23
22
21
20
19
18
17
16
15
14
13

37
38
39
40
41
42
43
44
45
46
47
48

1 2 3 4 5 6 7 8 9 101112

36 35 34 33 32 27 26 2531 30 29 28

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD9801

VRT

VRB

SUBST

ADVSS

ADVSS

ADVDD

ADVDD

ADVSS

MODE1

MODE2

INT_BIAS2

CMLEVEL

DRVSS

DSUBST

DVSS

ADCCLK

INT_BIAS1

DVDD

STBY

PBLK

CLPOB

SHP

SHD

CLPDM

DVSS

ACVDD

ACVDD

ACVDD

CLAMP_BIAS

ACVSS

PGACONT2

PGACONT1

CCDBYP1

PIN

DIN

CCDBYP2

ADVSS

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D9

DRVDD