Analog Devices AD9777EB, AD9777BSV Datasheet

a

16-Bit, 160 MSPS 2/4/8

®

Interpolating Dual TxDAC+

D/A Converter

FEATURES
16-Bit Resolution, 160/400 MSPS Input/Output Data Rate
Selectable 2/4/8 Interpolating Filter
Programmable Channel Gain and Offset Adjustment

/4, fS/8 Digital Quadrature Modulation

f

S

Capability
Direct IF Transmission Mode for 70 MHz + IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance

SFDR –73 dBc @ 2 MHz–35 MHz

WCDMA ACPR 71 dB @ IF = 71 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input

Differential/Single-Ended Sine Wave or

TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface

Two’s Complement/Straight Binary Data Coding

Dual-Port or Single-Port Interleaved Input Data
Single 3.3 V Supply Operation
Power Dissipation: Typical 1.2 W @ 3.3 V
On-Chip 1.2 V Reference
80-Lead Thermally Enhanced TQFP Package

AD9777

*

APPLICATIONS
Communications

Analog Quadrature Modulation Architectures
3G, Multicarrier GSM, TDMA, CDMA Systems
Broadband Wireless, Point-to-Point Microwave Radios
Instrumentation/ATE

GENERAL DESCRIPTION

The AD9777 is the 16-bit member of the AD977x pin compatible,
high performance, programmable 2×/4×/8× interpolating TxDAC+
family. The AD977x family features a serial port interface (SPI)
providing a high level of programmability, thus allowing for
enhanced system level options. These options include: selectable
2×/4×/8× interpolation filters; f

/2, fS/4, or fS/8 digital quadrature

S

modulation with image rejection; a direct IF mode; programmable
channel gain and offset control; programmable internal clock
divider; straight binary or two’s complement data interface; and
a single-port or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the require­ments of the reconstruction filters while simultaneously enhancing
the TxDAC+ family’s pass-band noise/distortion performance.
The independent channel gain and offset adjust registers allow
the user to calibrate LO feedthrough and sideband suppression

(continued on page 2)

FUNCTIONAL BLOCK DIAGRAM

AD9777

HALF-

HALF­BAND

***

FILTER 2

1616

16

/2

I

LATCH

Q

LATCH

FILTER 1

16

/2

DATA

ASSEMBLER

16

I AND Q

NONINTERLEAVED

OR

INTERLEAVED

DATA

16

WRITE

SELECT

TxDAC+ is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patent Numbers, 5568145, 5689257, and 5703519. Other patents pending.

MUX

CONTROL

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

*

HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR "ZERO STUFFING ONLY"

BAND

/2

FILTER 3

16

16

HALF­BAND

16

16

FILTER

BYPASS

MUX

/2

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

COS

SIN

f

/2, 4, 8

DAC

SIN

COS

(

f

)

DAC

PRESCALER

PHASE DETECTOR

AND VCO

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

GAIN
DAC

VREF

IDAC

GAIN/OFFSET

REGISTERS

IDAC

OFFSET

I/Q DAC

DIFFERENTIAL
CLK

DAC

I

OUT

IOFFSET

AD9777

(continued from page 1)

errors associated with analog quadrature modulators. The 6 dB
of gain adjustment range can also be used to control the output
power level of each DAC.

The AD9777 features the ability to perform f
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9777 accepts
I and Q complex data (representing a single or multicarrier wave­form), generates a quadrature modulated IF signal along with its
orthogonal representation via its dual DACs, and presents these
two reconstructed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion process.
Another digital modulation mode (i.e., the Direct IF Mode)
allows the original baseband signal representation to be frequency
translated such that pairs of images fall at multiples of one-half
the DAC update rate.

The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs. An
internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source. An
internal programmable divider simplifies clock generation in the
converter when using an external clock source. A flexible data
input interface allows for straight binary or two’s complement
formats and supports single-port interleaved or dual-port data.

Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9777 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard
systems, the superb baseband performance of the AD9777 is
ideal for wideband CDMA, multicarrier CDMA, multicarrier
TDMA, multicarrier GSM, and high performance systems
employing high order QAM modulation schemes. The image
rejection feature simplifies and can help to reduce the number
of signal band filters needed in a transmit signal chain. The
direct IF mode helps to eliminate a costly mixer stage for a
variety of communications systems.

/2, fS/4, and fS/8

S

PRODUCT HIGHLIGHTS

1. The AD9777 is the 16-bit member of the AD977x pin-

compatible, high performance, programmable 2× /4×/8×
interpolating TxDAC+ family.

2. Direct IF transmission is possible for 70 MHz + IFs through
a novel digital mixing process.

3. f

/2, fS/4, and fS/8 digital quadrature modulation and

S

user-selectable image rejection simplify/remove cascaded
SAW filter stages.

4. A 2×/4×/8× user-selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.

5. User-selectable two’s complement/straight binary data
coding.

6. User programmable channel gain control over 1 dB range
in 0.01 dB increments.

7. User-programmable channel offset control ±10% over
the FSR.

8. Ultra high speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy
interfacing.

10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W
from a 3.1 V to 3.5 V single supply. The 20 mA full-scale
current can be reduced for lower power operation, and
several sleep functions are provided to reduce power during
idle periods.

12. On-chip voltage reference: The AD9777 includes a 1.20 V
temperature compensated band gap voltage reference.

13. 80-lead thermally enhanced TQFP.

REV. 0–2–

AD9777

AD9777–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

otherwise noted.)

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

Parameter Min Typ Max Unit

RESOLUTION 16 Bits
DC Accuracy

1

Integral Nonlinearity ±6 LSB
Differential Nonlinearity –6.5 ± 3 +6.5 LSB

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error –0.025 ±0.01 +0.025 % of FSR

Gain Error (with Internal Reference) –1.0 +1.0 % of FSR
Gain Matching –1 ±0.1 +1 % of FSR
Full-Scale Output Current

2

220mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 200 kΩ
Output Resistance 3 pF
Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (REFLO = 3 V) 10 MΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift (With Internal Reference) 50 ppm of FSR/°C
Reference Voltage Drift ppm/°C

POWER SUPPLY

AVDD

Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I

in SLEEP Mode 23.3 26 mA

I

AVDD

AVDD

4

)

72.5 76 mA

CLKVDD (PLL OFF)

Voltage Range 3.1 3.3 3.5 V
Clock Supply Current (I

CLKVDD

4

)

8.5 mA

CLKVDD (PLL ON)

Clock Supply Current (I

)23.5mA

CLKVDD

DVDD

Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I
Nominal Power Dissipation

5

P

DIS

P

in PWDN 6.0 mW

DIS

DVDD

4

4

)

34 41 mA
380 410 mW

1.75 W

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

100 MSPS f

5

400 MSPS f

Specifications subject to change without notice.

driving a virtual ground.

DAC

DAC

OUTA

with f
, f

DATA

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

OUT

= 50 MSPS, fS/2 modulation, PLL enabled.

, is 32× the I

current.

REF

= 20 mA, unless

OUTFS

REV. 0

–3–

AD9777

(T

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

Interpolation = 2, Differential Transformer Coupled Output, 50  Doubly Terminated,

DYNAMIC SPECIFICATIONS

unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f
Output Settling Time (t

) (to 0.025%) 11 ns

ST

) 400 MSPS

DAC

Output Rise Time (10% to 90%)* 0.8 ns
Output Fall Time (10% to 90%)* 0.8 ns
Output Noise (I

= 20 mA) 50 pA√Hz

OUTFS

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

= 100 MSPS, f

f

DATA

f

= 65 MSPS, f

DATA

= 65 MSPS, f

f

DATA

= 78 MSPS, f

f

DATA

f

= 78 MSPS, f

DATA

= 160 MSPS, f

f

DATA

f

= 160 MSPS, f

DATA

= 1 MHz 71 85 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 84 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 83 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 83 dBc

OUT

= 0 dBFS)

OUT

Spurious-Free Dynamic Range within a 1 MHz Window

(f

= 0 dBFS, f

OUT

Two-Tone Intermodulation (IMD) to Nyquist (f

= 65 MSPS, f

f

DATA

= 65 MSPS, f

f

DATA

f

= 78 MSPS, f

DATA

= 78 MSPS, f

f

DATA

= 160 MSPS, f

f

DATA

f

= 160 MSPS, f

DATA

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz) 73 99.1

OUT

= 11 MHz 85 dBc

OUT2

= 21 MHz 78 dBc

OUT2

= 11 MHz 85 dBc

OUT2

= 21 MHz 78 dBc

OUT2

OUT2

OUT2

OUT1

= f

= –6 dBFS)

OUT2

= 11 MHz 85 dBc
= 21 MHz 84 dBc

Total Harmonic Distortion (THD)

= 100 MSPS, f

f

DATA

= 1 MHz; 0 dBFS –71 –83 dB

OUT

Signal-to-Noise Ratio (SNR)

= 78 MSPS, f

f

DATA

= 160 MSPS, f

f

DATA

= 5 MHz; 0 dBFS 79 dB

OUT

= 5 MHz; 0 dBFS 75 dB

OUT

Adjacent Channel Power Ratio (ACLR)

WCDMA with MHz BW, MHz Channel Spacing
IF = Baseband, f
IF = 19.2 MHz, f

= 76.8 MSPS 77 dBc

DATA

= 76.8 MSPS 73 dBc

DATA

Four-Tone Intermodulation

21 MHz, 22 MHz, 23 MHz, and 24 MHz at –12 dBFS 76 dBFS
(f

= MSPS, Missing Center)

DATA

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

201 MHz, 202 MHz, 203 MHz, and 204 MHz at –12 dBFS 72 dBFS
(f

= 160 MSPS, f

DATA

*Measured single ended into 50 Ω load.

Specifications subject to change without notice.

= 320 MHz)

DAC

OUTFS

= 20 mA,

REV. 0–4–

AD9777

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL SPECIFICATIONS

MIN

otherwise noted.)

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic “1” Voltage 2.1 3 V
Logic “0” Voltage 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect to Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND –0.3 +4.0 V
AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD –4.0 +4.0 V
AGND, DGND, CLKGND AGND, DGND, CLKGND –0.3 +0.3 V
REFIO, REFLO, FSADJ1/2 AGND –0.3 AVDD + 0.3 V
I

OUTA

, I

OUTB

AGND –1.0 AVDD + 0.3 V
P1B15–P1B0, P2B15–P2B0 DGND –0.3 DVDD + 0.3 V
DATACLK, PLL_LOCK DGND –0.3 DVDD + 0.3 V
CLK+, CLK–, RESET CLKGND –0.3 CLKVDD + 0.3 V
LPF CLKGND –0.3 CLKVDD + 0.3 V
SPI_CSB, SPI_CLK, DGND –0.3 DVDD + 0.3 V
SPI_SDIO, SPI_SDO
Junction Temperature +125 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

= 20 mA, unless

OUTFS

*Stresses above those listed under the ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9777BSV –40°C to +85°C 80-Lead TQFP SV-80

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced
TQFP Package ␪

*With thermal pad soldered to PCB.

= 23.5 °C/W*

JA

AD9777EB Evaluation Board

*SV = Thin Plastic Quad Flatpack

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9777 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD9777

CLKVDD

LPF

CLKVDD

CLKGND

CLK+

CLK–

CLKGND

DATACLK/PLL_LOCK

DGND

DVDD

P1B15 (MSB)

P1B14

P1B13

P1B12

P1B11

P1B10

DGND

DVDD

P1B9

P1B8

PIN CONFIGURATION

OUTA2

I

AGND

AGND

P1B0 (LSB)

OUTB2

I

AGND

P2B12

P2B13

AGND

AVDD

DVDD

DGND

AVDD

AGND

AVDD

AGND

AVDD

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P1B7

P1B6

P1B5

P1B4

DGND

AGND

AGND

P1B3

DVDD

I

I

AD9777

TxDAC+

TOP VIEW

(Not to Scale)

P1B2

P1B1

OUTB1

OUTA1

AGND

AVDD

P2B11

P2B10

AGND

P2B9

AVDD

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P2B8

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

P2B0 (LSB)

P2B1

P2B2

P2B3

P2B4

P2B5

DGND

DVDD

P2B6

P2B7

IQSEL/P2B15 (MSB)

ONEPORTCLK/P2B14

REV. 0–6–

AD9777

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage
2 LPF PLL Loop Filter
4, 7 CLKGND Clock Supply Common
5 CLK+ Differential Clock Input
6 CLK– Differential Clock Input
8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a

Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the
PLL has not achieved lock. This pin may also be programmed to act as
either an input or output (Address 02h, Bit 3) DATACLK signal running at

the input data rate.
9, 17, 25, 35, 44, 52 DGND Digital Common
10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage
11–16, 19–24, 27–30 P1B15 (MSB) to P1B0 (LSB) Port “1” Data Inputs
31 IQSEL/P2B15 (MSB) In “1” port mode, IQSEL = 1 followed by a rising edge of the differential

input clock will latch the data into the I channel input register. IQSEL = 0

will latch the data into the Q channel input register. In “2” port mode, this

pin becomes the port “2” MSB.
32 ONEPORTCLK/P2B14 With the PLL disabled and the AD9777 in “1” port mode, this pin becomes

a clock output that runs at twice the input data rate of the I and Q channels.

This allows the AD9777 to accept and demux interleaved I and Q data to

the I and Q input registers.
33, 34, 37–42, 45–50 P2B13 to P2B0 (LSB) Port “2” Data Inputs
53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO

becomes an output, SDO enters a High-Z state.
54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register

Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.
55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK.

Data output on the SPI port is registered on the falling edge.
56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets

SPI port logic and initializes instruction cycle.
57 RESET Logic “1” resets all of the SPI port registers, including Address 00h, to their

default values. A software reset can also be done by writing a Logic “1” to

SPI Register 00h, Bit 5. However, the software reset has no effect on the bits

in Address 00h.
58 REFIO Reference Output, 1.2 V Nominal
59 FSADJ2 Full-Scale Current Adjust, Q Channel
60 FSADJ1 Full-Scale Current Adjust, I Channel
61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage
62, 64, 66, 67, 70, 71, AGND Analog Common

74, 75, 77, 79
68, 69 I
72, 73 I

OUTA2

OUTA1

, I
, I

OUTB2

OUTB1

Differential DAC Current Outputs, Q Channel

Differential DAC Current Outputs, I Channel

REV. 0

–7–

AD9777

DIGITAL FILTER SPECIFICATIONS

Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8
2, 42 0
3, 41 –29
4, 40 0
5, 39 67
6, 38 0
7, 37 –134
8, 36 0
9, 35 244
10, 34 0
11, 33 –414
12, 32 0
13, 31 673
14, 30 0
15, 29 –1079
16, 28 0
17, 27 1772
18, 26 0
19, 25 –3280
20, 24 0
21, 23 10364
22 16384

20

0

–20

–40

–60

–80

ATTENUATION – dBFS

–100

–120

0 0.5

f

– Normalized to Input Data Rate

OUT

1.0 1.5 2.0

Figure 1a. 2 Interpolating Filter Response

20

0

–20

–40

–60

–80

ATTENUATION – dBFS

Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19
2, 18 0
3, 17 –120
4, 16 0
5, 15 438
6, 14 0
7, 13 –1288
8, 12 0
9, 11 5047
10 8192

Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7
2, 10 0
3, 9 –53
4, 8 0
5, 7 302
6 512

–100

–120

0 0.5

f

– Normalized to Input Data Rate

OUT

1.0 1.5 2.0

Figure 1b. 4 Interpolating Filter Response

20

0

–20

–40

–60

–80

ATTENUATION – dBFS

–100

–120

02

f

– Normalized to Input Data Rate

OUT

468

Figure 1c. 8 Interpolating Filter Response

REV. 0–8–

AD9777

DEFINITIONS OF SPECIFICATIONS
Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex modu­lator in series with the first complex modulator, either the upper
or lower frequency image near the second IF can be rejected.

Complex Modulation

The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e

j␻t

=

cos␻t + jsin␻t) and realizing real and imaginary components on
the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to “1,” minus the output when all inputs are set to “0.”

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV–S.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed that has a

f

DATA

sharp transition band near f
appear around f

Linearity Error (Also Called Integral Nonlinearity or INL)

(output data rate) can be greatly suppressed.

DAC

/2. Images that would typically

DATA

Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of “0” is
called offset error. For I
inputs are all “0.” For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to “1.”

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).

REV. 0

–9–

AD9777

–Typical Performance Characteristics

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I
Doubly Terminated, unless otherwise noted.)

10

0

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

0

65 130

FREQUENCY – MHz

TPC 1. Single-Tone Spec­trum @ f
f

= f

OUT

10

0

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

0

= 65 MSPS with

DATA

/3

DATA

50 150

FREQUENCY – MHz

100

TPC 4. Single-Tone Spec­trum @ f

= f

f

OUT

= 78 MSPS with

DATA

/3

DATA

90

85

80

75

70

SFDR – dBc

65

60

55

50

90

85

80

75

70

SFDR – dBc

65

60

55

50

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

0dBFS

–6dBFS

–12dBFS

0

10

FREQUENCY – MHz

15 255

20 30

TPC 2. In-Band SFDR vs. f
@ f

0

DATA

–12dBFS

= 65 MSPS

0dBFS

–6dBFS

10

FREQUENCY – MHz

15 255

20 30

TPC 5. In-Band SFDR vs. f
@ f

= 78 MSPS

DATA

OUT

OUT

90

0dBFS

85

80

75

70

SFDR – dBc

65

60

55

50

–6dBFS

0

–12dBFS

10

15 255

FREQUENCY – MHz

TPC 3. Out-of-Band SFDR vs.
f

OUT

90

85

80

75

70

–6dBFS

SFDR – dBc

65

60

55

50

0

@ f

0dBFS

= 65 MSPS

DATA

–12dBFS

10

15 255

FREQUENCY – MHz

TPC 6. Out-of-Band SFDR vs.
f

OUT

@ f

= 78 MSPS

DATA

20 30

20 30

10

0

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

0

100 300
FREQUENCY – MHz

200

TPC 7. Single-Tone Spec­trum @ f
with f

OUT

= 160 MSPS

DATA

= f

DATA

/3

90

85

80

75

70

–12dBFS

SFDR – dBc

65

60

55

50

0

0dBFS

–6dBFS

10

20 30

FREQUENCY – MHz

TPC 8. In-Band SFDR vs. f
@ f

= 160 MSPS

DATA

40 50

OUT

90

85

80

75

70

SFDR – dBc

65

60

55

50

0

–12dBFS

0dBFS

10

–6dBFS

20 30

FREQUENCY – MHz

TPC 9. Out-of-Band SFDR vs.
f

OUT

@ f

= 160 MSPS

DATA

40 50

REV. 0–10–

AD9777

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I
Doubly Terminated, unless otherwise noted.)

90

85

80

75

70

IMD – dBc

65

60

55

50

0

–3dBFS

0dBFS

–6dBFS

10

15 255

FREQUENCY – MHz

20 30

TPC 10. Third Order IMD Products
vs. Two-Tone f

90

85

80

75

70

IMD – dBc

65

60

55

50

0

@ f

OUT

DATA

4

8

1

2

20

30 5010

FREQUENCY – MHz

= 65 MSPS

40 60

TPC 13. Third Order IMD Products
vs. Two-Tone f

and Interpola-

OUT

tion Rate

⫻

f

f

DATA

DATA

DATA

DATA

= 160 MSPS,
= 160 MSPS,
= 80 MSPS,
= 50 MSPS

1
2⫻ f
4⫻ f

⫻

8

90

85

80

75

70

IMD – dBc

65

60

55

50

TPC 11. Third Order IMD Products
vs. Two-Tone f

90

85

80

75

70

IMD – dBc

65

60

55

50

TPC 14. Third Order IMD Products vs.
Two-Tone A
f

DATA

1⫻ f

DAC

⫻

f

2

DAC

4⫻ f

DAC

8⫻ f

DAC

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

90

85

80

75

70

IMD – dBc

65

60

55

50

0

–3dBFS

–6dBFS

0dBFS

20

30 5010

FREQUENCY – MHz

–3dBFS

0

0dBFS

–6dBFS

10

15 255

FREQUENCY – MHz

20 30

TPC 12. Third Order IMD Products

–15

2

OUT

–10

A

@ f

OUT

DATA

– dBFS

= 78 MSPS

8

4

1

–5 0

vs. Two-Tone f

90

85

80

75

70

65

SFDR – dBc

60

55

50

OUT

@ f

DATA

0dBFS

–6dBFS

–12dBFS

AVDD – V

TPC 15. SFDR vs. AVDD @

and Interpolation Rate

OUT

= 50 MSPS for All Cases

= 10 MHz, f

OUT

f

= 160 MSPS

DATA

= 320 MSPS,

DAC

f

= 50 MSPS,
= 100 MSPS,
= 200 MSPS,
= 400 MSPS

40 60

= 160 MSPS

3.43.33.23.1

3.5

90

85

80

75

70

IMD – dBc

65

60

55

50

0dBFS

–3dBFS

–6dBFS

3.43.33.23.1

AVDD – V

TPC 16. Third Order IMD Products
vs. AVDD @ f
f

= 320 MSPS, f

DAC

= 10 MHz,

OUT

DATA

= 160 MSPS

REV. 0

3.5

90

85

80

75

70

SNR – dB

65

60

55

50

050 150100

PLL OFF

PLL ON

INPUT DATA RATE – MSPS

TPC 17. SNR vs. Data Rate for

= 5 MHz

f

OUT

–11–

90

85

80

75

70

65

SFDR – dBc

60

55

50

–50 0 100

78MSPS

FDATA = 65MSPS

TEMPERATURE – C

160MSPS

50

TPC 18. SFDR vs. Temperature @

= f

DATA

/11

f

OUT

AD9777

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I
Doubly Terminated, unless otherwise noted.)

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

050 150100

FREQUENCY – MHz

TPC 19. Single-Tone Spurious
Performance, f
f

= 150 MSPS, No Interpolation

DATA

0

–20

–40

–60

AMPLITUDE – dBm

–80

–100

515

010

= 10 MHz,

OUT

25 35

20 30

FREQUENCY – MHz

45

40

TPC 22. Two-Tone IMD Performance,
f

= 90 MSPS, Interpolation = 4

DATA

⫻

–20

–40

–60

AMPLITUDE – dBm

–80

–100

TPC 20. Two-Tone IMD
Performance, f
No Interpolation

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

TPC 23. Single-Tone Spurious
Performance, f
f

DATA

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

0

050

FREQUENCY – MHz

40302010

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

0 100 250150

FREQUENCY – MHz

TPC 21. Single-Tone Spurious

0

0

DATA

50 150

100 300200

FREQUENCY – MHz

= 150 MSPS,

250

Performance, f
f

= 150 MSPS, Interpolation = 2

DATA

0

–20

–40

–60

AMPLITUDE – dBm

–80

–100

01525

= 10 MHz,

OUT

5

10 20

FREQUENCY – MHz

TPC 24. Two-Tone IMD Performance,

= 10 MHz,

OUT

= 80 MSPS, Interpolation = 4

⫻

f

= 10 MHz, f

OUT

Interpolation = 8

= 50 MSPS,

DATA

⫻

200

30050



0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

0 100 400200

FREQUENCY – MHz

300

TPC 25. Single-Tone Spurious
Performance, f
f

= 50 MSPS, Interpolation = 8

DATA

= 10 MHz,

OUT

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

020 8040

FREQUENCY – MHz

60

TPC 26. Eight-Tone IMD Performance,
f

= 160 MSPS, Interpolation = 8

DATA

⫻

⫻

REV. 0–12–

AD9777

MODE CONTROL (VIA SPI PORT)

Table I. Mode Control via SPI Port

(Default Values Are Highlighted)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h SDIO LSB, MSB First Software Reset on Sleep Mode Power-Down Mode 1R/2R Mode PLL_LOCK

01h Filter Filter Modulation Modulation Mode 0 = No Zero Stuffing 1 = Real Mix Mode 0 = e

02h 0 = Signed Input 0 = Two Port Mode DATACLK Driver DATACLK Invert ONEPORTCLK Invert IQSEL Invert Q First

03h PLL Divide PLL Divide

04h 0 = PLL OFF 0 = Automatic PLL Charge Pump PLL Charge Pump PLL Charge Pump

05h IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain

06h IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain

07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset

08h IDAC I

09h QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain

0Ah QDAC Coarse QDAC Coarse QDAC Coarse QDAC Coarse

0Bh QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset

0Ch QDAC I

0Dh Version Register Version Register Version Register Version Register

Bidirectional 0 = MSB Logic “1” Logic “1” shuts down Logic “1” shuts down DAC output current set Indicator
0 = Input 1 = LSB the DAC output all digital and analog by one or two external
1 = I/O currents. functions. resistors.

Interpolation Interpolation Mode (None, f
Rate Rate (None, f
(1×, 2×, 4×, 8×)(1×, 2×, 4×, 8×)f

Data 1 = One Port Mode Strength 0 = No Invert 0 = No Invert 0 = No Invert 0 = I First
1 = Unsigned 1 = Invert 1 = Invert 1 = Invert 1 = Q First

/2, Filters, Logic “1” Mix Mode Select

S

/4, fS/8) enables zero stuffing. 0 = PLLLOCK

S

/2, fS/4, fS/8) on Interpolation 0 = Complex 1 = e

S

0 = 2R, 1 = 1R

–j

+j␻

DATACLK/
PLL_LOCK

1 = DATACLK

(Prescaler) Ratio (Prescaler) Ratio

1 = PLL ON Charge Pump Control Control Control Control

1 = Programmable

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

Adjustment Adjustment Adjustment Adjustment

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

OFFSET

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

on

OFFSET

I

OUTB

IDAC Offset IDAC Offset

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

Gain Adjustment Gain Adjustment Gain Adjustment Gain Adjustment

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

OFFSET

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

OFFSET

on I

OUTB

QDAC Offset QDAC Offset

REV. 0

–13–

AD9777

REGISTER DESCRIPTION
Address 00h

Bit 7 Logic “0” (default) causes the SDIO pin to act as

an input during the data transfer (Phase 2) of the
communications cycle. When set to “1,” SDIO
can act as an input or output, depending on Bit 7 of
the instruction byte.

Bit 6 Logic “0” (default). Determines the direction

(LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the section
MSB/LSB Transfers for a detailed description.

Bit 5 Writing a “1” to this bit resets the registers to their

default values and restarts the chip. The RESET bit
always reads back “0.” Register Address 00h bits
are not cleared by this software reset. However, a
high level at the RESET pin forces all registers,
including those in Address 00h, to their default state.

Bit 4 Sleep mode. A Logic “1” to this bit shuts down the

DAC output currents.

Bit 3 Power-Down. Logic “1” shuts down all analog

and digital functions except for the SPI port.

Bit 2 1R/2R Mode. The default (“0”) places the AD9777

in two resistor mode. In this mode, the I

REF

currents
for the I and Q DAC references are set separately
by the R

resistors on FSADJ1 and FSADJ2 (Pins

SET

60 and 59). In the 2R mode, assuming the coarse
gain setting is full scale and the fine gain setting
is “0,” I
I

FULLSCALE1

FULLSCALE2

= 32 × V

= 32 × V

/FSADJ2. With this bit set

REF

/FSADJ1 and

REF

to “1,” the reference currents for both I and Q
DACs are controlled by a single resistor on Pin 60.
I

FULLSCALE

in one resistor mode for both the I and
Q DACs is half of what it would be in the 2R mode,
assuming all other conditions (R

, register settings)

SET

remain unchanged. The full-scale current of each DAC
can still be set to 20 mA by choosing a resistor of half
the value of the R

value used in the 2R mode.

SET

Bit 1 PLL_LOCK Indicator. When the PLL is enabled,

reading this bit will give the status of the PLL. A
Logic “1” indicates the PLL is locked. A Logic “0”
indicates an unlocked state.

Address 01h

Bits 7, 6 Filter interpolation rate according to the follow-

ing table:
00 1×

01 2×
10 4×
11 8×

Bits 5, 4 Modulation mode according to the following table:

00 none
01 f

/2

S

/4

10 f

S

/8

11 f

S

Bit 3 Logic “1” enables zero stuffing mode for interpola-

tion filters.

Bit 2 Default (“1”) enables the real mix mode. The I and

Q data channels are individually modulated by f

/4, or fS/8 after the interpolation filters. However,

f

S

/2,

S

no complex modulation is done. In the complex mix
mode (Logic “0”), the digital modulators on the I and
Q data channels are coupled to create a digital com­plex modulator. When the AD9777 is applied in
conjunction with an external quadrature modulator,
rejection can be achieved of either the higher or lower
frequency image around the second IF frequency (i.e.,
the second IF frequency is the LO of the analog
quadrature modulator external to the AD9777)
according to the bit value of Register 01h, Bit 1.

Bit 1 Logic “0” (default) causes the complex modulation to

be of the form e

–j␻t

, resulting in the rejection of the
higher frequency image when the AD9777 is used
with an external quadrature modulator. A Logic “1”
causes the modulation to be of the form e

+j␻t

, which

causes rejection of the lower frequency image.

Bit 0 In two port mode, a Logic “0” (default) causes Pin 8

to act as a lock indicator for the internal PLL. A
Logic “1” in this register causes Pin 8 to act as a
DATACLK, either generating or acting as an input
clock (see Register 02h, Bit 3) at the input data rate
of the AD9777.

Address 02h

Bit 7 Logic “0” (default) causes data to be accepted on

the inputs as two’s complement binary. Logic “1”
causes data to be accepted as straight binary.

Bit 6 Logic “0” (default) places the AD9777 in two port

mode. I and Q data enters the AD9777 via Ports 1
and 2, respectively. A Logic “1” places the AD9777
in one port mode in which interleaved I and Q
data is applied to Port 1. See the Pin Function
Descriptions for DATACLK/PLL_LOCK, IQSEL,
and ONEPORTCLK for detailed information on
how to use these modes.

Bit 5 DATACLK Driver Strength. With the internal PLL

disabled and this bit set to Logic “0,” it is recom­mended that DATACLK be buffered. When this bit
is set to Logic “1,” DATACLK acts as a stronger
driver capable of driving small capacitive loads.

Bit 4 Default Logic “0.” A value of “1” inverts

DATACLK at Pin 8.

Bit 2 Default Logic “0.” A value of “1” inverts

ONEPORTCLK at Pin 32.

Bit 1 The default of Logic “0” causes IQSEL = 1 to

direct input data to the I channel, while IQSEL = 0
directs input data to the Q channel. A Logic “1” in
this register inverts the sense of IQSEL.

Bit 0 The default of Logic “0” defines IQ pairing as IQ,

IQ... while programming a Logic “1” causes the
pair ordering to be QI, QI...

REV. 0–14–

AD9777

Address 03h

Bits 1, 0 Setting this divide ratio to a higher number allows

the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output
clocks run substantially slower. The divider ratio is
set according to the following table:

00 ⫼1
01 ⫼2
10 ⫼4
11 ⫼8

Address 04h

Bit 7 Logic “0” (default) disables the internal PLL.

Logic “1” enables the PLL.

Bit 6 Logic “0” (default) sets the charge pump control to

automatic. In this mode, the charge pump bias
current is controlled by the divider ratio defined in
Address 03h, Bits 1 and 0. Logic “1” allows the
user to manually define the charge pump bias cur­rent using Address 04h, Bits 2, 1, and 0. Adjusting
the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.

Bits 2, 1, 0 With the charge pump control set to manual, these

bits define the charge pump bias current according
to the following table:

000 50 µA
001 100 µA
010 200 µA
011 400 µA
100 800 µA

Address 05h, 09h

Bits 7–0 These bits represent an 8-bit binary number (Bit 7

MSB) that defines the fine gain adjustment of the I
(05h) and Q (09h) DAC according to the equation
given below.

Address 06h, 0Ah

Bits 3–0 These bits represent a 4-bit binary number (Bit 3

MSB) that defines the coarse gain adjustment of the
I (06h) and Q (0Ah) DACs according to the equa­tion below.

Address 07h, 0Bh

Bits 7–0

Address 08h, 0Ch

Bits 1, 0 The 10 bits from these two address pairs (07h, 08h

and 0Bh, 0Ch) represent a 10-bit binary number that
defines the offset adjustment of the I and Q DACs
according to the equation below
(07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB).

Address 08h, 0Ch

Bit 7 This bit determines the direction of the offset of the

I (08h) and Q (0Ch) DACs. A Logic “0” will apply
a positive offset current to I
will apply a positive offset current to I

, while a Logic “1”

OUTA

OUTB

. The
magnitude of the offset current is defined by the
bits in Addresses 07h, 0Bh, 08h, 0Ch according to
the formulas given below.





6

I

×

I

=

OUTA

=

I

OUTB

II

OFFSET REF

Equation 1 shows I
mode, the current I

REF REF





8








6

×

I

REF REF





8





=×

4

OUTA

REF





COARSE













COARSE











OFFSET




1024

and I

OUTB



3



1

+

–





16

16







3



1

+

–













as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R



×

I








32 256





×

I








32 256



is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a













FINE DATA

FINE

1024

×



























×





















16





24

10242421










2

16

––DATA


















16

2








scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.

(1)

REV. 0

–15–