ANALOG DEVICES AD9777 Service Manual
16-Bit, 160 MSPS 2x/4x/8x
Interpolating Dual TxDAC+
FEATURES
16-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
f
/4, fS/8 digital quadrature modulation capability
S
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR −73 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
®
D/A Converter
AD9777
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
AD9777
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
WRITE
SELECT
CLOCK OUT
SPI INTERFACE AND
CONTROL REGISTERS
HALFBAND
DATA
ASSEMBLER
16
16
LATCH
LATCH
MUX
CONTROL
HALF-BAND FILTERS ALSO CAN BE
*
CONFIGURED FOR ZERO STUFFING ONLY
FILTER1*
I
16
Q
/2
16
/2
FUNCTIONAL BLOCK DIAGRAM
HALFBAND
FILTER2*
HALFBAND
FILTER3*
161616
16
/2 /2
16
16
FILTER
BYPASS
MUX
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
f
/2, 4, 8
DAC
f
(
DAC
PRESCALER
PHASE DETECTOR
AND VCO
Figure 1.
)
COS
SIN
SIN
COS
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
GAIN
DAC
VREF
IDAC
IDAC
I/Q DAC
GAIN/OFFSET
REGISTERS
DIFFERENTIAL
CLK
OFFSET
DAC
I
OUT
IOFFSET
02706-001
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9777
TABLE OF CONTENTS
Features .............................................................................................. 1
Sleep/Power-Down Modes........................................................ 29
Applications....................................................................................... 1
General Description......................................................................... 4
Product Highlights....................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Digital Filter Specifications ......................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Te r mi n ol o g y .................................................................................... 12
Typical Performance Characteristics ........................................... 13
Mode Control (via SPI Port)..................................................... 18
Register Description................................................................... 20
Two Po r t Data Input Mode ....................................................... 29
PLL Enabled, Two-Port Mode .................................................. 30
DATACLK Inversion.................................................................. 30
DATACLK Driver Strength ....................................................... 30
PLL Enabled, One-Port Mode.................................................. 30
ONEPORTCLK Inversion......................................................... 31
ONEPORTCLK Driver Strength.............................................. 31
IQ Pairing.................................................................................... 31
PLL Disabled, Two-Port Mode................................................. 31
PLL Disabled, One-Port Mode................................................. 32
Digital Filter Modes ................................................................... 32
Amplitude Modulation.............................................................. 32
Modulation, No Interpolation.................................................. 34
Modulation, Interpolation = 2×............................................... 35
Modulation, Intermodulation = 4× ......................................... 36
Modulation, Intermodulation = 8× ......................................... 37
Functional Description ..................................................................22
Serial Interface for Register Control........................................ 22
General Operation of the Serial Interface............................... 22
Instruction Byte .......................................................................... 23
R/W ..............................................................................................23
N1, N0.......................................................................................... 23
A4, A3, A2, A1, A0..................................................................... 23
Serial Interface Port Pin Descriptions..................................... 23
MSB/LSB Transfers.....................................................................23
Notes on Serial Port Operation ................................................ 25
DAC Operation ........................................................................... 25
1R/2R Mode ................................................................................26
CLOCK Input Configuration ................................................... 26
Programmable PLL .................................................................... 27
Power Dissipation....................................................................... 29
Zero Stuffing ............................................................................... 38
Interpolating (Complex Mix Mode) ........................................ 38
Operations on Complex Signals............................................... 38
Complex Modulation and Image Rejection of Baseband
Signals
.......................................................................................... 39
Image Rejection and Sideband Suppressions of Modulated
Carriers
Applying the Output Configurations........................................... 46
Unbuffered Differential Output, Equivalent Circuit............. 46
Differential Coupling Using a Transformer............................ 46
Differential Coupling Using an Op Amp................................ 47
Interfacing with the AD8345 Quadrature Modulator........... 47
Evaluation Board ............................................................................ 48
Outline Dimensions ....................................................................... 58
Ordering Guide .......................................................................... 58
........................................................................................ 41
Rev. C | Page 2 of 60
AD9777
REVISION HISTORY
1/06—Rev. B to Rev. C
Updated Formatting .........................................................Universal
Changes to Figure 32 ....................................................................22
Changes to Figure 108 .................................................................. 54
Updated Outline Dimensions ..................................................... 58
Changes to Ordering Guide......................................................... 58
6/04—Data Sheet Changed from Rev. A to Rev. B.
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 8
Changes to DAC Operation Section........................................... 25
Changes to Figure 49, Figure 50, and Figure 51........................ 29
Changes to the PLL Enabled, One-Port Mode Section............ 30
Changes to the PLL Disabled, One-Port Mode Section........... 32
Changes to the Ordering Guide .................................................. 57
Updated the Outline Dimensions............................................... 57
3/03—Data Sheet Changed from Rev. 0 to Rev. A.
Edits to Features .............................................................................. 1
Edits to DC Specifications ............................................................. 3
Edits to Dynamic Specifications.................................................... 4
Edits to Pin Function Descriptions............................................... 7
Edits to Table I............................................................................... 14
Edits to Register Description—Address 02h Section ............... 15
Edits to Register Description—Address 03h Section ............... 16
Edits to Register Description—Address 07h, 0Bh Section...... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers Section........................................... 18
Changes to Figure 8 ...................................................................... 20
Edits to Programmable PLL Section........................................... 21
Added new Figure 14.................................................................... 22
Renumbered Figures 15 to 69...................................................... 22
Added Two-Port Data Input Mode Section............................... 23
Edits to PLL Enabled, Two-Port Mode Section ........................ 24
Edits to Figure 19 ......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode Section ....................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Changes to Figures 53 and 54...................................................... 38
Edits to Evaluation Board Section .............................................. 39
Changes to Figures 56 to 59......................................................... 40
Replaced Figures 60 to 69 ............................................................ 42
Updated Outline Dimensions...................................................... 49
7/02—Revision 0: Initial Version
Rev. C | Page 3 of 60
AD9777
GENERAL DESCRIPTION
The AD97771 is the 16-bit member of the AD977x pin
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family. The AD977x family features a
serial port interface (SPI) that provides a high level of
programmability, thus allowing for enhanced system level
options. These options include selectable 2×/4×/8× interpolation filters; f
/2, fS/4, or fS/8 digital quadrature modulation with
S
image rejection; a direct IF mode; programmable channel gain
and offset control; programmable internal clock divider;
straight binary or twos complement data interface; and a singleport or dual-port data interface.
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simultaneously
enhancing the TxDAC+ family’s pass-band noise/distortion
performance. The independent channel gain and offset adjust
registers allow the user to calibrate LO feedthrough and sideband
suppression errors associated with analog quadrature modulators.
The 6 dB of gain adjustment range can also be used to control the
output power level of each DAC.
The AD9777 features the ability to perform f
/2, fS/4, and fS/8
S
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9777 accepts I
and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its
orthogonal representation via its dual DACs, and presents these
two reconstructed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion process.
Another digital modulation mode (that is, the direct IF mode)
allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of
one-half the DAC update rate.
The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs. An
internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source.
An internal programmable divider simplifies clock generation
in the converter when using an external clock source. A flexible
data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port
data.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9777 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single-supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.
Targeted at wide dynamic range, multicarrier, and
multistandard systems, the superb baseband performance of the
AD9777 is ideal for wideband CDMA, multicarrier CDMA,
multicarrier TDMA, multicarrier GSM, and high performance
systems employing high-order QAM modulation schemes. The
image rejection feature simplifies and can help to reduce the
number of signal band filters needed in a transmit signal chain.
The direct IF mode helps to eliminate a costly mixer stage for a
variety of communications systems.
PRODUCT HIGHLIGHTS
1. The AD9777 is the 16-bit member of the AD977x pin
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.
2. Direct IF transmission is possible for 70 MHz + IFs
through a novel digital mixing process.
/2, fS/4, and fS/8 digital quadrature modulation and user
3. f
S
selectable image rejection simplify/remove cascaded SAW
filter stages.
4. A 2×/4×/8× user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary data
coding.
6. User programmable channel gain control over 1 dB range
in 0.01 dB increments.
7. User programmable channel offset control ±10% over the
FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for easy
interfacing.
10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W
from a 3.1 V to 3.5 V single supply. The 20 mA full-scale
current can be reduced for lower power operation, and
several sleep functions are provided to reduce power
during idle periods.
12. On-chip voltage reference: The AD9777 includes a 1.20 V
temperature compensated band gap voltage reference.
13. An 80-lead thin quad flat package, exposed pad
(TQFP_EP).
1
Protected by U.S. Patent Numbers, 5,568,145; 5,689,257; and 5,703,519.
Other patents pending.
Rev. C | Page 4 of 60
AD9777
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 16 Bits
DC Accuracy
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error −0.025 ±0.01 +0.025 % of FSR
Gain Error (with Internal Reference) −1.0 +1.0 % of FSR
Gain Matching −1 ±0.1 +1 % of FSR
Full-Scale Output Current
Output Compliance Range −1.0 +1.25 V
Output Resistance 200 kΩ
Output Capacitance 3 pF
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (with Internal Reference) 50 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
AVDD
CLKVDD (PLL OFF)
CLKVDD (PLL ON)
DVDD
Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V
OPERATING RANGE −40 +85 °C
1
Measured at I
2
Nominal full-scale current, I
3
Use an external amplifier to drive any external load.
4
100 MSPS f
5
400 MSPS f
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
MAX
1
= 20 mA, unless otherwise noted.
OUTFS
Integral Nonlinearity ±6 LSB
Differential Nonlinearity −6.5 ±3 +6.5 LSB
2
3
2 20 mA
100 nA
Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I
I
in SLEEP Mode 23.3 26 mA
AVDD
AVDD
4
)
72.5 76 mA
Voltage Range 3.1 3.3 3.5 V
Clock Supply Current (I
Clock Supply Current (I
)4 8.5 10.0 mA
CLKVDD
) 23.5 mA
CLKVDD
Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I
)4 34 41 mA
DVDD
Nominal Power Dissipation4 380 410 mW
5
P
DIS
P
in PWDN 6.0 mW
DIS
driving a virtual ground.
OUTA
with f
DAC
OUT
, f
= 50 MSPS, fS/2 modulation, PLL enabled.
DAC
DATA
, is 32× the I
OUTFS
= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
current.
REF
1.75 W
Rev. C | Page 5 of 60
AD9777
DYNAMIC SPECIFICATIONS
T
to T
MIN
transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (f
Output Settling Time (tST) (to 0.025%) 11 ns
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)1 0.8 ns
Output Noise (I
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (f
Spurious-Free Dynamic Range within a 1 MHz Window
Two-Tone Intermodulation (IMD) to Nyquist (f
Total Harmonic Distortion (THD)
Signal-to-Noise Ratio (SNR)
Adjacent Channel Power Ratio (ACPR)
Four-Tone Intermodulation
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = 200 MHz
1
Measured single-ended into 50 Ω load.
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I
MAX
) 400 MSPS
DAC
1
= 20 mA) 50 pA/√Hz
OUTFS
= 0 dBFS)
OUT
f
= 100 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 0 dBFS, f
OUT
f
= 65 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 100 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
= 1 MHz 71 85 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 84 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 83 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 83 dBc
OUT
= 100 MSPS, f
DATA
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 1 MHz; 0 dBFS −71 −83 dB
OUT
= 5 MHz; 0 dBFS 79 dB
OUT
= 5 MHz; 0 dBFS 75 dB
OUT
= 1 MHz 73 99.1 dBc
OUT
= f
OUT1
= 11 MHz 85 dBc
OUT2
= 21 MHz 78 dBc
OUT2
= 11 MHz 85 dBc
OUT2
= 21 MHz 78 dBc
OUT2
= 11 MHz 85 dBc
OUT2
= 21 MHz 84 dBc
OUT2
= −6 dBFS)
OUT2
= 20 mA, Interpolation = 2×, differential
OUTFS
0.8 ns
WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing
IF = Baseband, f
IF = 19.2 MHz, f
21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f
201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f
= 76.8 MSPS 73 dBc
DATA
= 76.8 MSPS 73 dBc
DATA
= MSPS, Missing Center) 76 dBFS
DATA
= 160 MSPS, f
DATA
= 320 MHz) 72 dBFS
DAC
Rev. C | Page 6 of 60
AD9777
DIGITAL SPECIFICATIONS
T
to T
MIN
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
MAX
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF
CLOCK INPUTS
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
SERIAL CONTROL BUS
Maximum SCLK Frequency (f
Mimimum Clock Pulse Width High (t
Mimimum Clock Pulse Width Low (t
) 15 MHz
SLCK
) 30 ns
PWH
) 30 ns
PWL
Maximum Clock Rise/Fall Time 1 ms
Minimum Data/Chip Select Setup Time (tDS) 25 ns
Minimum Data Hold Time (tDH) 0 ns
Maximum Data Valid Time (tDV) 30 ns
RESET Pulse Width 1.5 ns
Inputs (SDI, SDIO, SCLK, CSB)
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF
SDIO Output
Logic 1 Voltage DRVDD − 0.6 V
Logic 0 Voltage 0.4 V
Logic 1 Current 30 50 mA
Logic 0 Current 30 50 mA
= 20 mA, unless otherwise noted.
OUTFS
Rev. C | Page 7 of 60
AD9777
DIGITAL FILTER SPECIFICATIONS
ATTENUATION (dBFS)
ATTENUATION (dBFS)
ATTENUATION (dBFS)
–20
–40
–60
–80
–100
–120
–20
–40
–60
–80
–100
–120
–20
–40
–60
–80
–100
–120
20
0
0.50 1.0 1.5 2.0
f
(NORMALIZED TO INPUT DATA RATE)
OUT
02706-003
Figure 2. 2× Interpolating Filter Response
20
0
0.50 1.0 1.5 2.0
f
(NORMALIZED TO INPUT DATA RATE)
OUT
02706-004
Figure 3. 4× Interpolating Filter Response
20
0
2046
f
(NORMALIZED TO INPUT DATA RATE)
OUT
8
02706-005
Figure 4. 8× Interpolating Filter Response
Table 4. Half-Band Filter No. 1 (43 Coefficients)
Tap Coefficient
1, 43 8
2, 42 0
3, 41 −29
4, 40 0
5, 39 67
6, 38 0
7, 37 −134
8, 36 0
9, 35 244
10, 34 0
11, 33 −414
12, 32 0
13, 31 673
14, 30 0
15, 29 −1,079
16, 28 0
17, 27 1,772
18, 26 0
19, 25 −3,280
20, 24 0
21, 23 10,364
22 16,384
Table 5. Half-Band Filter No. 2 (19 Coefficients)
Tap Coefficient
1, 19 19
2, 18 0
3, 17 −120
4, 16 0
5, 15 438
6, 14 0
7, 13 −1,288
8, 12 0
9, 11 5,047
10 8,192
Table 6. Half-Band Filter No. 3 (11 Coefficients)
Tap Coefficient
1, 11 7
2, 10 0
3, 9 −53
4, 8 0
5, 7 302
6 512
Rev. C | Page 8 of 60
AD9777
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter With Respect To Min Max Unit
AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V
AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V
AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V
REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V
I
, I
OUTA
OUTB
P1B15 to P1B0, P2B15 to P2B0, RESET DGND −0.3 DVDD + 0.3 V
DATACLK/PLL_LOCK DGND −0.3 DVDD + 0.3 V
CLK+, CLK− CLKGND −0.3 CLKVDD + 0.3 V
LPF CLKGND −0.3 CLKVDD + 0.3 V
SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V
Junction Temperature 125 °C
Storage Temperature −65 +150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
AGND −1.0 AVDD + 0.3 V
THERMAL CHARACTERISTICS
Thermal Resistance
80-lead thin quad flat package, exposed pad [TQFP_EP]
= 23.5°C/W (With thermal pad soldered to PCB)
θ
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 9 of 60
AD9777
2
2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLKVDD
LPF
CLKVDD
CLKGND
CLK+
CLK–
CLKGND
DATACLK/PLL_LOCK
DGND
DVDD
P1B15 (MSB)
P1B14
P1B13
P1B12
P1B11
P1B10
DGND
DVDD
P1B9
P1B8
NC = NO CONNECT
OUTA1
AVDD
AVDD
AGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
PIN 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1B7
P1B6
AVDD
AGND
AGND
P1B5
P1B4
DVDD
DGND
AGND
I
(Not to Scale)
P1B3
P1B2
OUTB1
I
AD9777
TxDAC+
TOP VIEW
P1B1
AGND
AGND
OUTA
I
OUTB
I
P2B13
AGND
AGND
P2B12
DGND
P1B0 (LSB)
AVDD
DVDD
AGND
P2B11
AVDD
P2B10
AGND
P2B9
AVDD
P2B8
60
FSADJ1
59
FSADJ2
58
REFIO
57
RESET
56
SPI_CSB
55
SPI_CLK
54
SPI_SDIO
53
SPI_SDO
52
DGND
51
DVDD
50
P2B0 (LSB)
49
P2B1
48
P2B2
47
P2B3
46
P2B4
45
P2B5
44
DGND
43
DVDD
42
P2B6
41
P2B7
IQSEL/P2B15 (MSB)
ONEPORTCLK/P2B14
Figure 5. Pin Configuration
02706-002
Rev. C | Page 10 of 60
AD9777
Table 8. Pin Function Description
Pin No. Mnemonic Description
1, 3 CLKVDD Clock Supply Voltage.
2 LPF PLL Loop Filter.
4, 7 CLKGND Clock Supply Common.
5 CLK+ Differential Clock Input.
6 CLK− Differential Clock Input.
8 DATACLK/PLL_LOCK
9, 17, 25,
DGND Digital Common.
35, 44, 52
10, 18, 26,
DVDD Digital Supply Voltage.
36, 43, 51
11 to 16, 19
P1B15 (MSB) to P1B0 (LSB) Port 1 Data Inputs.
to 24, 27 to
30
31 IQSEL/P2B15 (MSB)
32 ONEPORTCLK/P2B14
33, 34, 37 to
P2B13 to P2B0 (LSB) Port 2 Data Inputs.
42, 45 to 50
53 SPI_SDO
54 SPI_SDIO
55 SPI_CLK
56 SPI_CSB
57 RESET
58 REFIO Reference Output, 1.2 V Nominal.
59 FSADJ2 Full-Scale Current Adjust, Q Channel.
60 FSADJ1 Full-Scale Current Adjust, I Channel.
61, 63, 65,
AVDD Analog Supply Voltage.
76, 78, 80
62, 64, 66, 67,
AGND Analog Common.
70, 71, 74,
75, 77, 79
68, 69 I
72, 73 I
OUTB2
OUTB1
, I
, I
OUTA2
OUTA1
With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the
PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be
programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running
at the input data rate.
In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches
the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input
register. In two-port mode, this pin becomes the Port 2 MSB.
With the PLL disabled and the AD9777 in one-port mode, this pin becomes a clock output
that runs at twice the input data rate of the I and Q channels. This allows the AD9777 to
accept and demux interleaved I and Q data to the I and Q input registers.
In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output,
SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For
more information, see the Two Port Data Input Mode section.
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The
default setting for this bit is 0, which sets SDIO as an input.
Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI
port is registered on the falling edge.
Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and
initializes instruction cycle.
Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A
software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the
software reset has no effect on the bits in Address 00h.
Differential DAC Current Outputs, Q Channel.
Differential DAC Current Outputs, I Channel.
Rev. C | Page 11 of 60
AD9777
TERMINOLOGY
Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant and
have the effect of wasting transmitter power and system bandwidth.
By placing the real part of a second complex modulator in series
with the first complex modulator, either the upper or lower
frequency image near the second IF can be rejected.
Complex Modulation
The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e
jωt
=
cosωt + jsinωt) and realizing real and imaginary components
on the modulator output.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Group Delay
Number of input clocks between an impulse applied at the
device input and the peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range.
Impulse Response
Response of the device to an impulse applied to the input.
Offset Error
The deviation of the output current from the ideal of 0 is called
offset error. For I
are all 0. For I
, 0 mA output is expected when the inputs
OUTA
, 0 mA output is expected when all inputs are
OUTB
set to 1.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Pass Band
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the
output signal and the peak spurious signal over the specified
bandwidth.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
(interpolation rate), a digital filter can be constructed that
f
DATA
has a sharp transition band near f
typically appear around f
(output data rate) can be greatly
DAC
/2. Images that would
DATA
suppressed.
Linearity Error
(Also called integral nonlinearity or INL) Linearity error is
defined as the maximum deviation of the actual analog output
from the ideal output, determined by a straight line drawn from
zero to full scale.
Rev. C | Page 12 of 60
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
Tem p er at u re Dr i ft
It is specified as the maximum change from the ambient (25°C)
value to the value at either T
MIN
or T
. For offset and gain
MAX
drift, the drift is reported in ppm of full-scale range (FSR) per
°C. For reference drift, the drift is reported in ppm per °C.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
AD9777
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I
50 Ω doubly terminated, unless otherwise noted.
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 65 130
FREQUENCY (MHz)
Figure 6. Single-Tone Spectrum @ f
90
85
80
0dBFS
–6dBFS
= 65 MSPS with f
DATA
OUT
= f
DATA
= 20 mA, Interpolation = 2×, differential transformer-coupled output,
OUTFS
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 10050 150
0dBFS
FREQUENCY (MHz)
= 78 MSPS with f
DATA
/3
02706-006
Figure 9. Single-Tone Spectrum @ f
90
85
80
OUT
= f
DATA
/3
02706-009
75
70
SFDR (dBc)
65
60
55
50
–12dBFS
Figure 7. In-Band SFDR vs. f
90
85
–12dBFS
80
75
70
–6dBFS
SFDR (dBc)
65
60
55
50
0dBFS
Figure 8. Out-of-Band SFDR vs. f
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
OUT
@ f
DATA
DATA
= 65 MSPS
= 65 MSPS
OUT
10 150 5 20 25 30
FREQUENCY (MHz)
02706-007
02706-008
75
70
SFDR (dBc)
65
60
55
50
–12dBFS
Figure 10. In-Band SFDR vs. f
90
85
80
75
70
SFDR (dBc)
65
60
55
50
0dBFS
–6dBFS
Figure 11. Out-of-Band SFDR vs. f
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
OUT
@ f
DATA
DATA
= 78 MSPS
= 78 MSPS
OUT
–12dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
02706-010
02706-011
Rev. C | Page 13 of 60
AD9777
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 200100 300
FREQUENCY (MHz)
Figure 12. Single-Tone Spectrum @ f
90
0dBFS
85
= 160 MSPS with f
DATA
OUT
= f
DATA
/3
02706-012
90
85
80
–3dBFS
75
70
IMD (dBc)
65
60
55
50
0dBFS
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
Figure 15. Third-Order IMD Products vs. Two-Tone f
90
85
0dBFS
OUT
@ f
= 65 MSPS
DATA
02706-015
80
75
70
SFDR (dBc)
65
60
55
50
01020304050
90
85
80
75
70
SFDR (dBc)
65
0dBFS
60
55
–12dBFS–6dBFS
FREQUENCY (MHz)
Figure 13. In-Band SFDR vs. f
–6dBFS
–12dBFS
OUT
@ f
= 160 MSPS
DATA
02706-013
80
75
–3dBFS
70
IMD (dBc)
65
60
55
50
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
Figure 16. Third-Order IMD Products vs. Two-Tone f
90
85
80
–3dBFS
75
70
IMD (dBc)
65
60
55
–6dBFS
0dBFS
OUT
@ f
= 78 MSPS
DATA
02706-016
50
01020304050
FREQUENCY (MHz)
Figure 14. Out-of-Band SFDR vs. f
OUT
@ f
= 160 MSPS
DATA
02706-014
Figure 17. Third-Order IMD Products vs. Two-Tone f
Rev. C | Page 14 of 60
50
20 300 10 405060
FREQUENCY (MHz)
@ f
OUT
= 160 MSPS
DATA
02706-017
AD9777
IMD (dBc)
90
85
80
75
70
65
4
×
8
×
1
×
2
×
90
85
80
75
70
IMD (dBc)
65
0dBFS
–3dBFS
–6dBFS
60
55
50
20 300 10 405060
FREQUENCY (MHz)
Figure 18. Third-Order IMD Products vs. Two-Tone f
Rate, 1× f
90
85
80
75
70
IMD (dBc)
2×
65
60
55
50
–15 –5–10 0
4× f
DATA
DATA
= 160 MSPS, 2× f
= 80 MSPS, 8× f
A
(dBFS)
OUT
DATA
= 50 MSPS
DATA
= 160 MSPS,
1×
Figure 19. Third-Order IMD Products vs. Two-Tone A
Rate, f
= 50 MSPS in All Cases, 1× f
DATA
90
85
4× f
DAC
= 200 MSPS, 8× f
DAC
= 50 MSPS, 2× f
= 400 MSPS
DAC
0dBFS
and Interpolation
OUT
8×
4×
and Interpolation
OUT
= 100 MSPS,
DAC
02706-018
02706-019
60
55
50
3.23.1 3.3 3.4 3.5
AVDD (V)
Figure 21. Third-Order IMD Products vs. AVDD @ f
f
= 320 MSPS, f
DAC
90
85
80
75
70
SNR (dB)
65
60
55
50
0 10050 150
PLL OFF
PLL ON
INPUT DATA RATE (MSPS)
Figure 22. SNR vs. Data Rate for f
90
85
78MSPS
= 160 MSPS
DATA
OUT
OUT
= 5 MHz
= 10 MHz,
02706-021
02706-022
80
75
70
SFDR (dBc)
65
60
55
50
3.23.1 3.3 3.4 3.5
Figure 20. SFDR vs. AVDD f
AVDD (V)
= 10 MHz, f
OUT
–6dBFS
–12dBFS
= 320 MSPS, f
DAC
= 160 MSPS
DATA
02706-020
Rev. C | Page 15 of 60
80
75
70
SFDR (dBc)
65
60
55
50
f
= 65MSPS
DATA
–50 500 100
TEMPERATURE (°C)
Figure 23. SFDR vs. Temperature @ f
OUT
160MSPS
= f
DATA
/11
02706-023
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
0 10050 150
FREQUENCY (MHz)
Figure 24. Single-Tone Spurious Performance, f
f
= 150 MSPS, No Interpolation
DATA
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
01020304050
FREQUENCY (MHz)
= 10 MHz,
OUT
Figure 25. Two-Tone IMD Performance,
f
= 150 MSPS, No Interpolation
DATA
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
Figure 26. Single-Tone Spurious Performance, f
100 1500 50 200 250 300
FREQUENCY (MHz)
f
= 150 MSPS, Interpolation = 2×
DATA
= 10 MHz,
OUT
02706-024
02706-025
02706-026
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
0 5 10 15 20 25 30 35 40 45
FREQUENCY (MHz)
Figure 27. Two-Tone IMD Performance, f
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
100 1500 50 200 250 300
FREQUENCY (MHz)
= 90 MSPS, Interpolation = 4×
DATA
Figure 28. Single-Tone Spurious Performance, f
f
= 80 MSPS, Interpolation = 4×
DATA
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
Figure 29. Two-Tone IMD Performance, f
f
= 50 MSPS, Interpolation = 8×
DATA
OUT
= 10 MHz,
OUT
02706-027
02706-028
= 10 MHz,
02706-029
Rev. C | Page 16 of 60
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
1000 200 300 400
FREQUENCY (MHz)
Figure 30. Single-Tone Spurious Performance, f
f
= 50 MSPS, Interpolation = 8×
DATA
= 10 MHz,
OUT
02706-030
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
2004060
FREQUENCY (MHz)
Figure 31. Eight-Tone IMD Performance, f
80
= 160 MSPS, Interpolation = 8x
DATA
02706-031
Rev. C | Page 17 of 60
AD9777
MODE CONTROL (VIA SPI PORT)
1
Table 9. Mode Control via SPI Port
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h
SDIO
Bidirectional
0 = Input
LSB, MSB First
0 = MSB
1 = LSB
1 = I/O
01h
02h
03h
Filter
Interpolation
Rate
(1×, 2×,
4×, 8×)
0 = Signed
Input Data
1 =
Unsigned
2
Data Rate
Filter
Interpolation
Rate
(1×, 2×,
4×, 8×)
0 = Two-Port
Mode
1 = One-Port
Mode
Clock
Output
04h
0 = PLL
2
OFF
1 = PLL ON
0 = Automatic
Charge Pump
Control
1 =
Programmable
05h
IDAC
Fine Gain
Adjustment
IDAC
Fine Gain
Adjustment
06h
07h
08h
IDAC Offset
Adjustment
Bit 9
IDAC I
OFFSET
IDAC Offset
Adjustment
Bit 8
Direction
09h
0 = I
I
OUTA
1 = I
I
OUT
QDAC
Fine Gain
Adjustment
OFFSET
OFFSET
B
on
on
QDAC
Fine Gain
Adjustment
Software
Reset on
Logic 1
Sleep Mode
Logic 1
Shuts Down
the DAC
Output
Currents
S
/2,
Modulation
Mode
(None, f
f
S
/4, fS/8)
S
/2,
DATACLK
Invert
0 = No
Modulation
Mode
(None, f
/4, fS/8)
f
S
DATACLK
Driver
Strength
Invert
1 = Invert
IDAC
Fine Gain
Adjustment
IDAC Offset
Adjustment
Bit 7
QDAC
Fine Gain
Adjustment
IDAC
Fine Gain
Adjustment
IDAC Offset
Adjustment
Bit 6
QDAC
Fine Gain
Adjustment
Power-Down
Mode Logic 1
Shuts Down All
Digital and
Analog
Func tions
0 = No Zero
Stuffing on
Interpolation
Filters, Logic 1
Enables Zero
Stuffing
IDAC
Fine Gain
Adjustment
IDAC
Coarse Gain
Adjustment
IDAC Offset
Adjustment
Bit 5
QDAC
Fine Gain
Adjustment
1R/2R Mode
DAC Output
Current Set by
One or Two
External
Resistors
0 = 2R, 1 = 1R
1 = Real Mix
Mode
0 = Complex
Mix Mode
ONEPORTCLK
Invert
0 = No Invert
1 = Invert
PLL
Charge
Pump
Control
IDAC
Fine Gain
Adjustment
IDAC
Coarse Gain
Adjustment
IDAC Offset
Adjustment
Bit 4
QDAC
Fine Gain
Adjustment
PLL_LOCK
Indicator
−jωt
0 = e
+jωt
1 = e
IQSEL
Invert
0 = No
Invert
1 = Invert
PLL Divide
(Prescaler)
Ratio
PLL
Charge
Pump
Control
IDAC
Fine Gain
Adjustment
IDAC
Coarse Gain
Adjustment
IDAC Offset
Adjustment
Bit 3
IDAC Offset
Adjustment
Bit 1
QDAC
Fine Gain
Adjustment
DATACLK/
PLL_LOCK
Select
0 =
PLL_LOCK
1 =
DATACLK
Q First
0 = I First
1 = Q First
PLL Divide
(Prescaler)
Ratio
PLL
Charge
Pump
Control
IDAC
Fine Gain
Adjustment
IDAC
Coarse Gain
Adjustment
IDAC Offset
Adjustment
Bit 2
IDAC Offset
Adjustment
Bit 0
QDAC
Fine Gain
Adjustment
2
Rev. C | Page 18 of 60
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