ANALOG DEVICES AD9776A, AD9778A, AD9779A Service Manual

Dual 12-/14-/16-Bit,1 GSPS,

FEATURES

Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,

full operating conditions Single carrier W-CDMA ACLR = 7 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA,

R

= 25 Ω to 50 Ω

L

Novel 2×, 4×, and 8× interpolator/coarse complex modulator

allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

APPLICATIONS

Wireless infrastructure

W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM Digital high or low IF synthesis Internal digital upconversion capability Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

Digital-to-Analog Converters

AD9776A/AD9778A/AD9779A

GENERAL DESCRIPTION

The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting a multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL537x FMOD series from Analog Devices, Inc. A serial peripheral interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 m CMOS process and operate on 1.8 V and

3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in a 100-lead TQFP.

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. CMOS data input interface with adjustable setup and hold.

5. Novel 2×, 4×, and 8× interpolator/coarse complex

modulator allows carrier placement anywhere in DAC bandwidth.

TYPICAL SIGNAL CHAIN

COMPLEX I AND Q

DC

FPGA/ASI C/DSP

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DIGITAL INTERPOL ATION FILTERS

AD9776A/AD9778A/AD9779A

QUADRATURE

MODULATOR/

MIXER/

AMPLIFIER

I DAC

POST DAC

ANALOG FILTER

Q DAC

Figure 1.

LO

A

6452-114

AD9776A/AD9778A/AD9779A

REVISION HISTORY

3/08—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Added Note 2 .................................................................................... 4

Changes to Table 2 ............................................................................ 5

Changes to Table 3 ............................................................................ 6

Changes to Thermal Resistance Section ........................................ 7

Inserted Table 6 ................................................................................. 8

Changes to Pin 39 Description, Table 7 ......................................... 9

Changes to Pin 39 Description, Table 8 ....................................... 10

Changes to Pin 39 Description, Table 9 ....................................... 12

Changes to Theory of Operation Section .................................... 23

Rev. A | Page 2 of 60

Changes to Table 10 ....................................................................... 23

Changes to Table 13 ....................................................................... 26

Changes to Table 14 ....................................................................... 27

Changes to Interpolation Filter Architecture Section ............... 33

Replaced Sourcing the DAC Sample Clock Section .................. 36

Replaced Transmit Path Gain and Offset Correction Section . 40

Replaced Input Data Ports Section .............................................. 42

Replaced Device Synchronization Section .................................. 45

Deleted Figure 112 to Figure 117 ................................................. 58

8/07—Revision 0: Initial Version

AD9776A/AD9778A/AD9779A

K

FUNCTIONAL BLOCK DIAGRAM

SYNC_O

SYNC_I

DATACLK

P1D<15:0>

P2D<15:0>

DELAY

LINE

DELAY

LINE

DATA

ASSEMBLER

LATCH

AD9779A

CLOCK GENERAT ION/DISTRIBUTIO N

I

Q

2× 2×

2× 2× 2×

DIGITAL CONTROLL ER

SERIAL

PERIPHERAL

INTERFACE

SDO

SDIO

SCL

CSB

POWER-ON

RESET

2×

n × f

/8

DAC

n = 0, 1, 2 ... 7

COMPLEX

MODULATOR

10

SYNC

CLOCK

MULTIPLIER

2×/4×/8×

GAIN

16-BIT

I DAC

16-BIT Q DAC

REFERENCE

AND BIAS

REFCLK+

REFCLK–

OUT1_P

OUT1_N

OUT2_P

OUT2_N

VREF

I120

AUX1_P AUX1_N

AUX2_P AUX2_N

6452-001

Figure 2. AD9779A Functional Block Diagram

Rev. A | Page 3 of 60

AD9776A/AD9778A/AD9779A

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

otherwise noted.

Table 1.

AD9776A AD9778A AD9779A Parameter Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 12 14 16 Bits ACCURACY

Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB

MAIN DAC OUTPUTS

Offset Error −0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR Gain Error (With Internal Reference) ±2 ±2 ±2 % FSR Full-Scale Output Current Output Compliance Range −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ Gain DAC Monotonicity Guaranteed Guaranteed Guaranteed

MAIN DAC TEMPERATURE DRIFT

Offset 0.04 0.04 0.04 ppm/°C Gain 100 100 100 ppm/°C Reference Voltage 30 30 30 ppm/°C

AUX DAC OUTPUTS

Resolution 10 10 10 Bits Full-Scale Output Current Output Compliance Range (Source) 0 1.6 0 1.6 0 1.6 V Output Compliance Range (Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V Output Resistance 1 1 1 MΩ AUX DAC Monotonicity Guaranteed Guaranteed Guaranteed

REFERENCE

Internal Reference Voltage 1.2 1.2 1.2 V Output Resistance 5 5 5 kΩ

ANALOG SUPPLY VOLTAGES

AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V CVDD18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 V

DIGITAL SUPPLY VOLTAGES

DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V DVDD18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 V

POWER CONSUMPTION

1× Mode, f 2× Mode, f 2× Mode, f 4× Mode, f

8× Mode, f

Power-Down Mode 2.5 9.8 2.5 9.8 2.5 9.8 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 % FSR/V

OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 °C

1

Based on a 10 kΩ external resistor.

2

See the Power Dissipation section for more details.

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

1

2

= 100 MSPS, IF = 1 MHz 250 300 250 300 250 300 mW

DAC

= 320 MSPS, IF = 16 MHz, PLL Off 498 498 498 mW

DAC

= 320 MSPS, IF = 16 MHz, PLL On 588 588 588 mW

DAC

/4 Modulation, f

DAC

= 500 MSPS,

DAC

8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA

−1.998 +1.998 −1.998 +1.998 −1.998 +1.998 mA

572 572 572 mW

IF = 137.5 MHz, Q DAC Off

/4 Modulation, f

DAC

= 1 GSPS,

DAC

980 980 980 mW

IF = 262.5 MHz

= 20 mA, maximum sample rate, unless

OUTFs

Rev. A | Page 4 of 60

AD9776A/AD9778A/AD9779A

DIGITAL SPECIFICATIONS

T

to T

MIN

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

CMOS INPUT LOGIC LEVEL

Input VIN Logic High 2.0 V

Input VIN Logic Low 0.8 V

Maximum Input Data Rate at Interpolation

1× 300 MSPS 2× 250 MSPS 4× 200 MSPS 8× DVDD18, CVDD18 = 1.8 V ± 5% 112.5 MSPS DVDD18, CVDD18 = 1.9 V ± 5% 125 MSPS DVDD18, CVDD18 = 2.0 V ± 2% 137.5 MSPS

CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)

Output V

Logic High 2.4 V

OUT

Logic Low 0.4 V

OUT

1

DATACLK Output Duty Cycle At 250 MHz, into 5 pF load 40 50 60 %

LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB

Input Voltage Range, VIA or VIB 825 1575 mV

Input Differential Threshold, V

Input Differential Hysteresis, V

−100 +100 mV

IDTH

− V

IDTHH

20 mV

IDTHL

Receiver Differential Input Impedance, RIN 80 120 Ω

LVDS Input Rate

Additional limits on f

apply; see description of

SYNC_I

Register 5, Bits<3:1> in Tab le 14 Setup Time, SYNC_I to REFCLK 0.4 ns Hold Time, SYNC_I to REFCLK 0.55 ns

LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination

Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, RO Single-ended 80 100 120 Ω

DAC CLOCK INPUT (REFCLK+, REFCLK−)

Differential Peak-to-Peak Voltage 400 800 2000 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate DVDD18, CVDD18 = 1.8 V ± 5% 900 MSPS DVDD18, CVDD18 = 1.9 V ± 5% 1000 MSPS DVDD18, CVDD18 = 2.0 V ± 2% 1100 MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns Setup Time, SDI to SCLK 1.6 ns Hold Time, SDI to SCLK 0.0 ns Data Valid, SDO to SCLK 2.0 ns

1

Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests

using an external buffer for this signal.

= 20 mA, maximum sample rate, unless

OUTFs

250 MSPS

Rev. A | Page 5 of 60

AD9776A/AD9778A/AD9779A

DIGITAL INPUT DATA TIMING SPECIFICATIONS

All modes, −40°C to +85°C.

Table 3.

Parameter Conditions Min Typ Max Unit

Input Data1

Setup Time Input data to DATACLK 3.0 ns Hold Time Input data to DATACLK 0.0 ns Setup Time Input data to REFCLK −0.8 ns Hold Time Input data to REFCLK 3.7 ns

Latency

1× Interpolation With or without modulation 25 DACCLK Cycles 2× Interpolation With or without modulation 70 DACCLK Cycles 4× Interpolation With or without modulation 146 DACCLK Cycles 8× Interpolation With or without modulation 297 DACCLK Cycles Inverse Sync 18 DACCLK Cycles

Power-Up Time

1

Timing vs. temperature and data valid keep out windows are delineated in Table 25.

2

Measured from CSB rising edge on Register 0x00, Bit 4 write from 0 to 1. VREF decoupling capacitor equal to 0.1 μF.

AC SPECIFICATIONS

T

to T

MIN

otherwise noted.

2

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

260 ms

= 20 mA, maximum sample rate, unless

OUTFs

Table 4.

AD9776A AD9778A AD9779A

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

= 100 MSPS, f

DAC

f

= 200 MSPS, f

DAC

f

= 400 MSPS, f

DAC

f

= 800 MSPS, f

DAC

= 20 MHz 82 82 82 dBc

OUT

= 50 MHz 81 81 82 dBc

OUT

= 70 MHz 80 80 80 dBc

OUT

= 70 MHz 85 85 87 dBc

OUT

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

= 200 MSPS, f

DAC

f

= 400 MSPS, f

DAC

f

= 400 MSPS, f

DAC

f

= 800 MSPS, f

DAC

NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz

= 50 MHz 87 87 91 dBc

OUT

= 60 MHz 80 85 85 dBc

OUT

= 80 MHz 75 81 81 dBc

OUT

= 100 MHz 75 80 81 dBc

OUT

TONE SPACING

f

= 200 MSPS, f

DAC

f

= 400 MSPS, f

DAC

f

= 800 MSPS, f

DAC

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),

= 80 MHz −152 −155 −158 dBm/Hz

OUT

= 80 MHz −155 −159 −160 dBm/Hz

OUT

= 80 MHz −157.5 −160 −161 dBm/Hz

OUT

SINGLE CARRIER

f

= 491.52 MSPS, f

DAC

f

= 491.52 MSPS, f

DAC

W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO

= 100 MHz 76 78 79 dBc

OUT

= 200 MHz 69 73 74 dBc

OUT

(ACLR), SINGLE CARRIER

f

= 491.52 MSPS, f

DAC

f

= 491.52 MSPS, f

DAC

= 100 MHz 77.5 80 81 dBc

OUT

= 200 MHz 76 78 78 dBc

OUT

Rev. A | Page 6 of 60

AD9776A/AD9778A/AD9779A

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter With Respect To Rating

AVDD33, DVDD33

DVDD18, CVDD18

AGND DGND, CGND −0.3 V to +0.3 V DGND AGND, CGND −0.3 V to +0.3 V CGND AGND, DGND −0.3 V to +0.3 V I120, VREF, IPTAT AGND

OUT1_P, OUT1_N, OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, AUX2_N

P1D<15> to P1D<0>, P2D<15> to P2D<0>

DATACLK, TXENABLE DGND

REFCLK+, REFCLK− CGND

RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO

Junction Temperature +125°C Storage Temperature

Range

AGND, DGND, CGND

AGND

DGND

−65°C to +150°C

−0.3 V to +3.6 V

−0.3 V to +2.1 V

−0.3 V to AVDD33 + 0.3 V

−1.0 V to AVDD33 + 0.3 V

−0.3 V to DVDD33 + 0.3 V

−0.3 V to CVDD18 + 0.3 V

−0.3 V to DVDD33 + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

For optimal thermal performance, the exposed paddle (EPAD) should be soldered to the ground plane for the 100-lead, thermally enhanced TQFP_EP package.

Typical θ Airflow increases heat dissipation effectively reducing θ

and θJC are specified for a 4-layer board in still air.

JA

.

Table 6. Thermal Resistance

Package Type θJA θJB θJC Unit

100-Lead TQFP_EP

EPAD Soldered 19.1 12.4 7.1 °C/W EPAD Not Soldered 27.4 °C/W

ESD CAUTION

Rev. A | Page 7 of 60

AD9776A/AD9778A/AD9779A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD33

100

CGND

AGND

DGND

P1D<9>

P1D<8>

P1D<7>

DGND

P1D<6>

P1D<5>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CVDD18

REFCLK+

REFCLK–

CVDD18

SYNC_I+

SYNC_I–

DVDD18

P1D<11>

P1D<10>

DVDD18

NC = NO CONNECT

PIN 1

26

P1D<4>27P1D<3>28P1D<2>29P1D<1>30P1D<0>

ANALOG DOMAIN

DIGITAL DO MAIN

AD9776A

TOP VIEW

(Not to Scale)

31NC32

33

DGND

DVDD18

34NC35NC36NC37

38

39

40

DVDD33

P2D<11>41P2D<10>

DATACLK

TXENABLE

Figure 3. AD9776A Pin Configuration

75

I120

74

VREF

73

IPTAT

72

AGND

71

IRQ

70

RESET

69

CSB

68

SCLK

67

SDIO

66

SDO

65

PLL_LOCK

64

DGND

63

SYNC_O+

62

SYNC_O–

61

DVDD33

60

DVDD18

59

NC

58

NC

57

NC

56

NC

55

P2D<0>

54

DGND

53

DVDD18

52

P2D<1>

51

P2D<2>

42

43

44

45

DGND

P2D<9>

P2D<8>46P2D<7>47P2D<6>48P2D<5>49P2D<4>50P2D<3>

DVDD18

06452-002

Table 7. AD9776A Pin Function Descriptions

Pin No. Mnemonic Description

1 CVDD18 1.8 V Clock Supply. 20 P1D<8> Port 1, Data Input D8. 2 CVDD18 1.8 V Clock Supply. 21 P1D<7> Port 1, Data Input D7. 3 CGND 4 CGND 5 REFCLK+ 6 REFCLK− 7 CGND 8 CGND 9 CVDD18 10 CVDD18 11 CGND 12 AGND 13 SYNC_I+ 14 SYNC_I− 15 DGND 16 DVDD18 17 P1D<11> 18 P1D<10> 19 P1D<9> Port 1, Data Input D9.

Clock Ground. 22 DGND Digital Ground. Clock Ground. 23 DVDD18 1.8 V Digital Supply. Differential Clock Input. 24 P1D<6> Port 1, Data Input D6. Differential Clock Input. 25 P1D<5> Port 1, Data Input D5. Clock Ground. 26 P1D<4> Port 1, Data Input D4. Clock Ground. 27 P1D<3> Port 1, Data Input D3.

1.8 V Clock Supply. 28 P1D<2> Port 1, Data Input D2.

1.8 V Clock Supply. 29 P1D<1> Port 1, Data Input D1. Clock Ground. 30 P1D<0> Port 1, Data Input D0 (LSB). Analog Ground. 31 NC No Connect. Differential Synchronization Input. 32 DGND Digital Ground. Differential Synchronization Input. 33 DVDD18 1.8 V Digital Supply. Digital Ground. 34 NC No Connect.

1.8 V Digital Supply. 35 NC No Connect. Port 1, Data Input D11 (MSB). 36 NC No Connect. Port 1, Data Input D10. 37

DATACLK

Data Clock Output.

38 DVDD33 3.3 V Digital Supply.

Rev. A | Page 8 of 60

AD9776A/AD9778A/AD9779A

Pin No. Mnemonic Description

39 TXENABLE

40 P2D<11> Port 2, Data Input D11 (MSB). 41 P2D<10> Port 2, Data Input D10. 42 P2D<9> Port 2, Data Input D9. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Ground. 45 P2D<8> Port 2, Data Input D8. 46 P2D<7> Port 2, Data Input D7. 47 P2D<6> Port 2, Data Input D6. 48 P2D<5> Port 2, Data Input D5. 49 P2D<4> Port 2, Data Input D4. 50 P2D<3> Port 2, Data Input D3. 51 P2D<2> Port 2, Data Input D2. 52 P2D<1> Port 2, Data Input D1. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Ground. 55 P2D<0> Port 2, Data Input D0 (LSB). 56 NC No Connect. 57 NC No Connect. 58 NC No Connect. 59 NC No Connect. 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output. 64 DGND Digital Ground. 65 PLL_LOCK PLL Lock Indicator. 66 SDO SPI Port Data Output. 67 SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request.

Transmit Enable. In single port mode, this pin also functions as IQSELECT.

Pin No. Mnemonic Description

72 AGND Analog Ground. 73 IPTAT

74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Ground. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Ground. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Ground. 82 AGND Analog Ground. 83 OUT2_P Differential DAC Current Output, Channel 2. 84 OUT2_N Differential DAC Current Output, Channel 2. 85 AGND Analog Ground. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 88 AGND Analog Ground. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 91 AGND Analog Ground. 92 OUT1_N Differential DAC Current Output, Channel 1. 93 OUT1_P Differential DAC Current Output, Channel 1. 94 AGND Analog Ground. 95 AGND Analog Ground. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Ground. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Ground. 100 AVDD33 3.3 V Analog Supply.

Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating.

Rev. A | Page 9 of 60

AD9776A/AD9778A/AD9779A

AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD33

100

CGND

AGND

DGND

P1D<9>

DGND

P1D<8>

P1D<7>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CVDD18

REFCLK+

REFCLK–

CVDD18

SYNC_I+

SYNC_I–

DVDD18

P1D<13>

P1D<12>

P1D<11>

P1D<10>

DVDD18

NC = NO CONNECT

PIN 1

26

P1D<6>27P1D<5>28P1D<4>29P1D<3>30P1D<2>31P1D<1>

ANALOG DOMAIN

DIGITAL DO MAIN

AD9778A

TOP VIEW

(Not to Scale)

32

33

34

DGND

DVDD18

35NC36NC37

P1D<0>

38

39

40

DVDD33

P2D<13>41P2D<12>42P2D<11>

DATACLK

TXENABLE

Figure 4. AD9778A Pin Configuration

75

I120

74

VREF

73

IPTAT

72

AGND

71

IRQ

70

RESET

69

CSB

68

SCLK

67

SDIO

66

SDO

65

PLL_LOCK

64

DGND

63

SYNC_O+

62

SYNC_O–

61

DVDD33

60

DVDD18

59

NC

58

NC

57

P2D<0>

56

P2D<1>

55

P2D<2>

54

DGND

53

DVDD18

52

P2D<3>

51

P2D<4>

43

44

45

46

DGND

P2D<9>47P2D<8>48P2D<7>49P2D<6>50P2D<5>

DVDD18

P2D<10>

06452-003

Table 8. AD9778A Pin Function Descriptions

Pin No. Mnemonic Description

1 CVDD18 1.8 V Clock Supply. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Ground. 4 CGND Clock Common. 5 REFCLK+ Differential Clock Input. 6 REFCLK− Differential Clock Input. 7 CGND Clock Ground. 8 CGND Clock Ground. 9 CVDD18 1.8 V Clock Supply. 10 CVDD18 1.8 V Clock Supply. 11 CGND Clock Ground. 12 AGND Analog Ground. 13 SYNC_I+ Differential Synchronization Input. 14 SYNC_I− Differential Synchronization Input. 15 DGND Digital Ground. 16 DVDD18 1.8 V Digital Supply. 17 P1D<13> Port 1, Data Input D13 (MSB). 18 P1D<12> Port 1, Data Input D12. 19 P1D<11> Port 1, Data Input D11. 20 P1D<10> Port 1, Data Input D10. 21 P1D<9> Port 1, Data Input D9.

Pin No. Mnemonic Description

22 DGND Digital Ground. 23 DVDD18 1.8 V Digital Supply. 24 P1D<8> Port 1, Data Input D8. 25 P1D<7> Port 1, Data Input D7. 26 P1D<6> Port 1, Data Input D6. 27 P1D<5> Port 1, Data Input D5. 28 P1D<4> Port 1, Data Input D4. 29 P1D<3> Port 1, Data Input D3. 30 P1D<2> Port 1, Data Input D2. 31 P1D<1> Port 1, Data Input D1. 32 DGND Digital Ground. 33 DVDD18 1.8 V Digital Supply. 34 P1D<0> Port 1, Data Input D0 (LSB). 35 NC No Connect. 36 NC No Connect. 37 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE

40 P2D<13> Port 2, Data Input D13 (MSB). 41 P2D<12> Port 2, Data Input D12.

Rev. A | Page 10 of 60

DATACLK

Data Clock Output.

Transmit Enable. In single port mode, this pin also functions as IQSELECT.

AD9776A/AD9778A/AD9779A

Pin No. Mnemonic Description

42 P2D<11> Port 2, Data Input D11. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Ground. 45 P2D<10> Port 2, Data Input D10. 46 P2D<9> Port 2, Data Input D9. 47 P2D<8> Port 2, Data Input D8. 48 P2D<7> Port 2, Data Input D7. 49 P2D<6> Port 2, Data Input D6. 50 P2D<5> Port 2, Data Input D5. 51 P2D<4> Port 2, Data Input D4. 52 P2D<3> Port 2, Data Input D3. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Ground. 55 P2D<2> Port 2, Data Input D2. 56 P2D<1> Port 2, Data Input D1. 57 P2D<0> Port 2, Data Input D0 (LSB). 58 NC No Connect. 59 NC No Connect. 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output. 64 DGND Digital Ground. 65 PLL_LOCK PLL Lock Indicator. 66 SDO SPI Port Data Output. 67 SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 72 AGND Analog Ground.

Pin No. Mnemonic Description

73 IPTAT

74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Ground. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Ground. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Ground. 82 AGND Analog Ground. 83 OUT2_P Differential DAC Current Output, Channel 2. 84 OUT2_N Differential DAC Current Output, Channel 2. 85 AGND Analog Ground. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 88 AGND Analog Ground. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 91 AGND Analog Ground. 92 OUT1_N Differential DAC Current Output, Channel 1. 93 OUT1_P Differential DAC Current Output, Channel 1. 94 AGND Analog Ground. 95 AGND Analog Ground. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Ground. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Ground. 100 AVDD33 3.3 V Analog Supply.

Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating.

Rev. A | Page 11 of 60

AD9776A/AD9778A/AD9779A

AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD33

100

CVDD18

CGND

REFCLK+

REFCLK–

CGND

CVDD18

CGND

AGND

SYNC_I+

SYNC_I–

DGND

DVDD18

P1D<15>

P1D<14>

P1D<13>

P1D<12>

P1D<11>

DGND

DVDD18

P1D<10>

P1D<9>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PIN 1

26

P1D<8>27P1D<7>28P1D<6>29P1D<5>30P1D<4>31P1D<3>

ANALOG DOMAIN

DIGITAL DO MAIN

AD9779A

TOP VIEW

(Not to Scale)

32

33

DGND

34

DVDD18

P1D<2>35P1D<1>36P1D<0>

37

38

39

40

DVDD33

P2D<15>41P2D<14>42P2D<13>

XENABLE

DATACLK

Figure 5. AD9779A Pin Configuration

75

I120

74

VREF

73

IPTAT

72

AGND

71

IRQ

70

RESET

69

CSB

68

SCLK

67

SDIO

66

SDO

65

PLL_LOCK

64

DGND

63

SYNC_O+

62

SYNC_O–

61

DVDD33

60

DVDD18

59

P2D<0>

58

P2D<1>

57

P2D<2>

56

P2D<3>

55

P2D<4>

54

DGND

53

DVDD18

52

P2D<5>

51

P2D<6>

43

44

45

48

DGND

DVDD18

P2D<12>46P2D<11>47P2D<10>

P2D<9>49P2D<8>50P2D<7>

6452-004

Table 9. AD9779A Pin Function Descriptions

Pin No. Mnemonic Description

1 CVDD18 1.8 V Clock Supply. 22 DGND Digital Ground. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Ground. 4 CGND Clock Ground. 5 REFCLK+ Differential Clock Input. 6 REFCLK− Differential Clock Input. 7 CGND Clock Ground. 8 CGND Clock Ground. 9 CVDD18 1.8 V Clock Supply. 10 CVDD18 1.8 V Clock Supply. 11 CGND Clock Ground. 12 AGND Analog Ground. 13 SYNC_I+ Differential Synchronization Input. 14 SYNC_I− Differential Synchronization Input. 15 DGND Digital Ground. 16 DVDD18 1.8 V Digital Supply. 17 P1D<15> Port 1, Data Input D15 (MSB). 18 P1D<14> Port 1, Data Input D14. 19 P1D<13> Port 1, Data Input D13. 20 P1D<12> Port 1, Data Input D12. 21 P1D<11> Port 1, Data Input D11.

Rev. A | Page 12 of 60

23 DVDD18 1.8 V Digital Supply. 24 P1D<10> Port 1, Data Input D10. 25 P1D<9> Port 1, Data Input D9. 26 P1D<8> Port 1, Data Input D8. 27 P1D<7> Port 1, Data Input D7. 28 P1D<6> Port 1, Data Input D6. 29 P1D<5> Port 1, Data Input D5. 30 P1D<4> Port 1, Data Input D4. 31 P1D<3> Port 1, Data Input D3. 32 DGND Digital Ground. 33 DVDD18 1.8 V Digital Supply. 34 P1D<2> Port 1, Data Input D2. 35 P1D<1> Port 1, Data Input D1. 36 P1D<0> Port 1, Data Input D0 (LSB).

DATACLK

37

Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE

Transmit Enable. In single port mode, this

pin also functions as IQSELECT. 40 P2D<15> Port 2, Data Input D15 (MSB). 41 P2D<14> Port 2, Data Input D14.

AD9776A/AD9778A/AD9779A

Pin No. Mnemonic Description

42 P2D<13> Port 2, Data Input D13. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Ground. 45 P2D<12> Port 2, Data Input D12. 46 P2D<11> Port 2, Data Input D11. 47 P2D<10> Port 2, Data Input D10. 48 P2D<9> Port 2, Data Input D9. 49 P2D<8> Port 2, Data Input D8. 50 P2D<7> Port 2, Data Input D7. 51 P2D<6> Port 2, Data Input D6. 52 P2D<5> Port 2, Data Input D5. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Ground. 55 P2D<4> Port 2, Data Input D4. 56 P2D<3> Port 2, Data Input D3. 57 P2D<2> Port 2, Data Input D2. 58 P2D<1> Port 2, Data Input D1. 59 P2D<0> Port 2, Data Input D0 (LSB). 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output. 64 DGND Digital Ground. 65 PLL_LOCK PLL Lock Indicator. 66 SDO SPI Port Data Output. 67 SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 72 AGND Analog Ground.

Pin No. Mnemonic Description

73 IPTAT

74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Ground. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Ground. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Ground. 82 AGND Analog Ground. 83 OUT2_P Differential DAC Current Output, Channel 2. 84 OUT2_N Differential DAC Current Output, Channel 2. 85 AGND Analog Ground. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 88 AGND Analog Ground. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 91 AGND Analog Ground. 92 OUT1_N Differential DAC Current Output, Channel 1. 93 OUT1_P Differential DAC Current Output, Channel 1. 94 AGND Analog Ground. 95 AGND Analog Ground. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Ground. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Ground. 100 AVDD33 3.3 V Analog Supply.

Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating.

Rev. A | Page 13 of 60

AD9776A/AD9778A/AD9779A

TYPICAL PERFORMANCE CHARACTERISTICS

4

3

2

1

0

–1

–2

INL (16-BIT LSB)

–3

–4

–5

–6

10k 20k 30k 60k50k

0

CODE

40k

06452-005

Figure 6. AD9779A Typical INL

100

f

= 160MSPS

90

80

70

SFDR (dBc)

60

50

0

DATA

f

= 200MSPS

DATA

f

= 250MSPS

DATA

20 40 60 80

f

(MHz)

OUT

Figure 9. AD9779A In-Band SFDR vs. f

OUT

100

06452-008

,

2× Interpolation

DNL (16-BIT L SB)

100

SFDR (dBc)

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0 60k50k40k30k20k10k

90

80

70

CODE

Figure 7. AD9779A Typical DNL

f

= 160MSPS

DATA

f

DATA

f

= 200MSPS

DATA

= 250MSPS

100

f

= 100MSPS

DATA

90

80

f

= 150MSPS

DATA

70

SFDR (dBc)

60

50

0

6452-006

20 40 60 80

f

(MHz)

OUT

Figure 10. AD9779A In-Band SFDR vs. f

DATA

= 200MSPS

OUT

100

06452-009

,

4× Interpolation

100

f

= 50MSPS

DATA

90

80

70

SFDR (dBc)

f

DATA

= 100MSPS

f

DATA

= 125MSPS

60

50

0

20 40 60 80

f

OUT

Figure 8. AD9779A In-Band SFDR vs. f

(MHz)

OUT

100

06452-007

,

1× Interpolation

60

50

0

10 20 30 40

Figure 11. AD9779A In-Band SFDR vs. f

8× Interpolation

f

OUT

(MHz)

OUT

50

06452-010

,

Rev. A | Page 14 of 60

AD9776A/AD9778A/AD9779A

100

90

f

= 160MSPS

DATA

80

70

SFDR (dBc)

60

50

0

20 40 60 80

Figure 12. AD9779A Out-of-Band SFDR vs. f

f

OUT

f

DATA

(MHz)

= 200MSPS

f

DATA

= 250MSPS

,

OUT

100

06452-011

2× Interpolation

100

90

80

f

= 150MSPS

DATA

70

SFDR (dBc)

f

= 100MSPS

DATA

90

80

70

SFDR (dBc)

60

50

0

10 20 30

f

OUT

PLL OFF

(MHz)

Figure 15. AD9779A In-Band SFDR, 4× Interpolation,

= 100 MSPS, PLL On/Off

f

DATA

100

90

80

70

SFDR (dBc)

0dBFS

–3dBFS

–6dBFS

PLL ON

40

06452-014

60

50

0

20 40 60 80

Figure 13. AD9779A Out-of-Band SFDR vs. f

f

OUT

(MHz)

f

DATA

= 200MSPS

OUT

100

06452-012

,

4× Interpolation

100

90

f

80

70

SFDR (dBc)

60

50

0

10 20 30 40

Figure 14. AD9779A Out-of-Band SFDR vs. f

DATA

= 50MSPS

f

DATA

f

OUT

= 125MSPS

(MHz)

f

DATA

= 100MSPS

,

OUT

50

06452-013

8× Interpolation

60

50

0

20 40 60

f

(MHz)

OUT

Figure 16. AD9779A In-Band SFDR vs. f

OUT

80

06452-015

,

Digital Full Scale

100

90

80

70

SFDR (dBc)

60

50

0

Figure 17. AD9779A In-Band SFDR vs. f

10mA

20mA

30mA

20 40 60

f

(MHz)

OUT

80

06452-016

,

Output Full-Scale Current

Rev. A | Page 15 of 60

AD9776A/AD9778A/AD9779A

IMD (dBc)

100

90

f

80

70

60

50

0

= 250MSPS

DATA

20 40 60 80 100

f

OUT

Figure 18. AD9779A Third-Order IMD vs. f

1× Interpolation

f

DATA

(MHz)

= 160MSPS

f

DATA

= 200MSPS

,

OUT

120

06452-017

IMD (dBc)

100

90

80

70

f

50

DATA

75

= 50MSPS

150

125

100

175

f

DATA

f

OUT

200

60

50

0

25

Figure 21. AD9779A Third-Order IMD vs. f

8× Interpolation

f

= 75MSPS

DATA

= 125MSPS

250

225

(MHz)

275

f

300

DATA

= 100MSPS

350

325

OUT

375

,

400

425

450

06452-020

100

f

= 160MSPS

DATA

90

80

IMD (dBc)

70

60

50

0 20 40 60 80 100 120 140 160 180 200

f

DATA

= 200MSPS

f

OUT

(MHz)

Figure 19. AD9779A Third-Order IMD vs. f

2× Interpolation

100

90

80

f

= 150MSPS

DATA

IMD (dBc)

70

f

= 100MSPS

DATA

60

f

= 200MSPS

DATA

50

0

40 80 120 160 200 240 280 320 360

f

(MHz)

OUT

Figure 20. AD9779A Third-Order IMD vs. f

4× Interpolation

f

DATA

= 250MSPS

,

OUT

,

OUT

220

400

100

90

80

PLL OFF

IMD (dBc)

70

60

50

0

20 40 60 80 120 140 160 180

06452-018

Figure 22. AD9779A Third-Order IMD vs. f

4× Interpolation, f

100

95

90

85

80

75

IMD (dBc)

70

65

60

55

50

0

40 80 120 160 200 240 280 320

06452-019

Figure 23. AD9779A Third-Order IMD vs. f

50 Parts, 4× Interpolation, f

PLL ON

100

f

(MHz)

OUT

= 100 MSPS, PLL On vs. PLL Off

DATA

f

(MHz)

OUT

= 200 MSPS

DATA

,

OUT

, over

200

06452-021

400360

06452-022

Rev. A | Page 16 of 60

AD9776A/AD9778A/AD9779A

–

100

95

90

85

80

75

IMD (dBc)

70

65

60

55

50

0 400

0dBFS

–3dBFS

–6dBFS

80 160 240 36032040 120 200 280

f

(MHz)

OUT

Figure 24. AD9779A IMD Performance vs. Digital Full-Scale Input over

Output Frequency, 4× Interpolation, f

= 200 MSPS

DATA

REF 0dBm *PEAK

Log 10dB

LGAV 51

S2

W1

FC

S3

AA £(f): FTUN SWP

START 1.0MHz

06452-117

*RES BW 20kHz

4× Interpolation, f

*ATTEN 20dB

EXT REF

DC-COUPLED

VBW 20kHz

STOP 400.0M Hz

SWEEP 1.203s (601 pts)

Figure 27. AD9779A Two-Tone Spectrum,

= 100 MSPS, f

DATA

= 30 MHz, 35 MHz

OUT

06452-024

100

95

90

85

80

75

30mA

IMD (dBc)

70

65

60

55

50

0 400

20mA

10mA

80 160 240 36032040 120 200 280

f

(MHz)

OUT

Figure 25. AD9779A IMD Performance vs. Full-Scale Output Current over

Output Frequency, 4× Interpolation, f

REF 0dBm *PEAK

Log 10dB

LGAV 51

S2

W1

FC

S3

AA £(f): FTUN SWP

START 1.0MHz *RES BW 20kHz

*ATTEN 20dB

VBW 20kHz

= 200 MSPS

DATA

EXT REF

DC-COUPLED

STOP 400.0M Hz

SWEEP 1.203s (601 pts)

06452-023

Figure 26. AD9779A Single Tone, 4× Interpolation,

f

= 100 MSPS, f

DATA

= 30 MHz

OUT

–142

–146

–150

–154

–158

NSD (dBm/Hz)

–162

–166

–170

0

06452-118

20 40 60 80

0dBFS

f

OUT

–6dBFS

(MHz)

–3dBFS

06452-025

Figure 28. AD9779A Noise Spectral Density vs. Digital Full-Scale over Output

Frequency of Single Tone Input, f

= 200 MSPS,

DATA

2× Interpolation

150

–154

f

= 400MSPS

DAC

f

–158

–162

NSD (dBm/Hz)

–166

–170

0

Figure 29. AD9779A Noise Spectral Density vs. f

Eight-Tone Input with 500 kHz Spacing, f

= 200MSPS

DAC

f

= 800MSPS

DAC

20 40 60 80

f

(MHz)

OUT

over Output Frequency for

DAC

= 200 MSPS

DATA

100

06452-026

Rev. A | Page 17 of 60

AD9776A/AD9778A/AD9779A

–

150

55

–154

f

= 200MSPS

DAC

f

DAC

= 400MSPS

DAC

= 800MSPS

NSD (dBm/Hz)

–158

–162

–166

–170

0

20 40 60 80

f

(MHz)

OUT

Figure 30. AD9779A Noise Spectral Density vs. f

over Output Frequency

DAC

100

06452-027

with a Single Tone Input at −6 dBFS

55

–60

–65

0dBFS, PLL ENABLED

0dBFS, PL L DISABLED

–70

–75

ACLR (dBc)

–3dBFS, PLL DISABLED

–80

–6dBFS, PL L DISABLED

–85

–90

0

f

(MHz)

OUT

26024022020018016014012010080604020

06452-300

Figure 31. AD9779A ACLR for First Adjacent Band W-CDMA, 4× Interpolation,

= 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF

f

DATA

REF –25.28dBm *AVG

Log 10dB

*ATTEN 4dB

EXT REF

–60

–65

0dBFS, PLL ENABLED

–70

ACLR (dBc)

–75

–6dBFS, PLL DISABLED

–80

–85

–90

–3dBFS , PLL DISABL ED

0

f

OUT

0dBFS, PLL DISABLED

(MHz)

Figure 33. AD9779A ACLR for Second Adjacent Band W-CDMA,

4× Interpolation, f

= 122.88 MSPS;

DATA

On-Chip Modulation Translates Baseband Signal to IF

55

–60

–65

ACLR (dBc)

–70

–75

0dBFS, PL L ENABLED

–6dBFS, PL L DISABLE D

–80

–85

–90

–3dBFS , PLL DISABL ED

0

f

OUT

0dBFS, PLL DISABLED

(MHz)

Figure 34. AD9779A ACLR for Third Adjacent Band W-CDMA, 4×

Interpolation, f

= 122.88 MSPS, On-Chip Modulation Translates

DATA

Baseband Signal to IF

REF –30.28dBm *AVG

Log 10dB

*ATTEN 4dB

EXT REF

26024022020018016014012010080604020

06452-301

26024022020018016014012010080604020

06452-302

PAVG

PAVG 10 W1 S2

CENTER 143.88MHz *RES BW 30kHz

RMS RESULTS

CARRIER POW ER –12.49dBm/

3.84000MHz

FREQ OFFSET

5.000MHz

10.00MHz

15.00MHz

VBW 300kHz

REF BW

3.840MHz

SWEEP 162. 2ms (601 pts)

LOWER

dBm

dBc

–89.23

–76.75

–93.43

–80.94

–92.44

–79.95

Figure 32. AD9779A W-CDMA Signal, 4× Interpolation,

= 122.88 MSPS, f

f

DATA

/4 Modulation

DAC

SPAN 50MHz

UPPER

dBc –77.42 –80.47 –78.96

dBm –89.91 –92.96 –91.45

06452-031

10 W1 S2

CENTER 151.38MHz *RES BW 30kHz

TOTAL CARRIER POWER –12.61dBm/15.3600MHz REF CARRIER PO WER –17.87dBm/3.84000MHz

1 –17.87dBm 2 –20.65dBm 3 –18.26dBm 4 –18.23dBm

VBW 300kHz

FREQ OFFSET

5.000MHz

10.00MHz

15.00MHz

INTEG BW

3.840MHz

Figure 35. AD9779A Multicarrier W-CDMA Signal,

4× Interpolation, f

= 122.88 MSPS, f

DAC

dBc

dBm

–67.70

–85.57

–69.32

–97.87

–71.00

–99.52

/4 Modulation

DAC

SPAN 50MHz

UPPER

SWEEP 162. 2ms (601 pts)

LOWER

dBc –67.70 –70.00 –71.65

dBm –85.57 –87.19 –88.88

06452-032

Rev. A | Page 18 of 60

ANALOG DEVICES AD9776A, AD9778A, AD9779A Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TYPICAL SIGNAL CHAIN

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

DIGITAL INPUT DATA TIMING SPECIFICATIONS

AC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS