Analog Devices AD9775 c Datasheet

14-Bit, 160 MSPS 2×/4×/8×

Interpolating Dual TxDAC+

FEATURES

14-bit resolution, 160 MSPS/400 MSPS input/output

data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment

/4, fS/8 digital quadrature modulation capability

f

S

Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI® port Excellent AC performance

SFDR −71 dBc @ 2 MHz to 35 MHz

WCDMA ACPR−71 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input

Differential/single-ended sine wave or TTL/CMOS/LVPECL

compatible Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thermally enhanced TQFP package

FUNCTIONAL BLOCK DIAGRAM

®

D/A Converter

AD9775

APPLICATIONS

Communications

Analog quadrature modulation architecture 3G, multicarrier GSM, TDMA, CDMA systems Broadband wireless, point-to-point microwave radios Instrumentation/ATE

GENERAL DESCRIPTION

The AD97751 is the 14-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; f modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.

1

Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other

patents pending.

/2, fS/4, or fS/8 digital quadrature

S

(continued on Page 4)

AD9775

HALFBAND

FILTER1*

DATA

ASSEMBLER

14

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

14

WRITE

SELECT

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

CONTROL

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

I

LATCH

16

Q

LATCH

MUX

HALF-BAND FILTERS ALSO CAN BE

*

CONFIGURED FOR "ZERO STUFFING ONLY"

/2

HALF-

BAND

FILTER2*

FILTER3*

16

161616

16

/2

/2 /2

16

BYPASS

COS

SIN

f

/2, 4, 8

DAC

FILTER

MUX

(

f

DAC

PRESCALER

PHASE DETECTOR

AND VCO

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

REJECTION/

SIN

COS

)

Figure 1.

IDAC

IMAGE

DUAL DAC

MODE

BYPASS

MUX

GAIN DAC

VREF

IDAC

OFFSET

I/Q DAC

GAIN/OFFSET

REGISTERS

DIFFERENTIAL CLK

DAC

IOFFSET

I

OUT

02858-C-001

www.analog.com

AD9775

GENERAL DESCRIPTION

(continued from Page 1) The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

The AD9775 features the ability to perform f digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9775 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.

/2, fS/4, and fS/8

S

PRODUCT HIGHLIGHTS

1. The AD9775 is the 14-bit member of the AD977x pin

compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.

2. Direct IF transmission capability for 70 MHz + IFs through

a novel digital mixing process.

/2, fS/4, and fS/8 digital quadrature modulation and user

3. f

S

selectable image rejection to simplify/remove cascaded SAW filter stages.

4. A 2×/4×/8× user selectable interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User selectable twos complement/straight binary data

coding.

6. User programmable channel gain control over 1 dB range

in 0.01 dB increments.

7. User programmable channel offset control ±10% over the

FSR.

8. Ultrahigh speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy

interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W from

a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation and several sleep functions are provided to reduce power during idle periods.

12. On-chip voltage reference: The AD9775 includes a 1.20 V

temperature compensated band gap voltage reference.

13. 80-lead thermally enhanced TQFP.

Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9775 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard systems, the superb baseband performance of the AD9775 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high-order QAM modulation schemes. The image rejection feature simplifies and can help reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.

Rev. C | Page 4 of 60

AD9775

SPECIFICATIONS

T

to T

MIN

Table 1. DC Specifications

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC Accuracy1

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)

Offset Error −0.02 ±0.01 +0.02 % of FSR

Gain Error (With Internal Reference) −1.0 +1.0 % of FSR

Gain Matching −1.0 ±0.1 +1.0 % of FSR

Full-Scale Output Current2 2 20 mA

Output Compliance Range −1.0 +1.25 V

Output Resistance 200 kΩ

Output Capacitance 3 pF

Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V

Reference Output Current3 100 nA REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 7 kΩ

Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift (With Internal Reference) 50 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C POWER SUPPLY

AVDD

CLKVDD

CLKVDD (PLL ON)

DVDD

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V OPERATING RANGE −40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

100 MSPS f

5

400 MSPS f

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

Integral Nonlinearity −5 ±1.5 +5 LSB Differential Nonlinearity −3 ±1.0 +3 LSB

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I I

in SLEEP Mode 23.3 26 mA

AVDD

)4 72.5 76 mA

AVDD

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

Clock Supply Current (I

)4 8.5 10.0 mA

CLKVDD

) 23.5 mA

CLKVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

)4 34 41 mA

DVDD

Nominal Power Dissipation 380 410 mW P

5 1.75 W

DIS

P

IN PWDN 6.0 mW

DIS

driving a virtual ground.

OUTA

with f

DAC

OUT

= 50 MSPS, fS/2 modulation, PLL enabled.

DAC

, is 32 × the I

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

current.

REF

Rev. C | Page 5 of 60

AD9775

T

to T

MIN

transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.

Table 2. Dynamic Specifications

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f Output Settling Time (tST) (to 0.025%) 11 ns Output Rise Time (10% to 90%)1 0.8 ns Output Fall Time (10% to 90%)1 0.8 ns Output Noise (I

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Spurious-Free Dynamic Range within a 1 MHz Window

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

1

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

) 400 MSPS

DAC

= 20 mA) 50 pA/√Hz

OUTFS

= 0 dBFS)

OUT

f

= 100 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 0 dBFS, f

OUT

f

= 65 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 100 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

= 1 MHz 71 84.5 dBc

OUT

= 1 MHz 84 dBc

OUT

= 15 MHz 80 dBc

OUT

= 1 MHz 84 dBc

OUT

= 15 MHz 80 dBc

OUT

= 1 MHz 82 dBc

OUT

= 15 MHz 80 dBc

OUT

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz; 0 dBFS −71 −82.5 dB

OUT

= 5 MHz; 0 dBFS 76 dB

OUT

= 5 MHz; 0 dBFS 74 dB

OUT

= 1 MHz 73 91.3 dBc

OUT

= f

OUT1

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, Interpolation = 2×, differential

OUTFS

WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing

IF = Baseband, f

IF = 19.2 MHz, f

21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f

201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f

= 76.8 MSPS 71 dBc

DATA

= 76.8 MSPS 71 dBc

DATA

= MSPS, Missing Center) 75 dBFS

DATA

= 160 MSPS, f

DATA

= 320 MHz) 72 dBFS

DAC

Rev. C | Page 6 of 60

AD9775

T

to T

MIN

Table 3. Digital Specifications

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V

Logic 0 Voltage 0 0.9 V

Logic 1 Current −10 +10 µA

Logic 0 Current −10 +10 µA

Input Capacitance 5 pF CLOCK INPUTS

Input Voltage Range 0 3 V

Common-Mode Voltage 0.75 1.5 2.25 V

Differential Voltage 0.5 1.5 V SERIAL CONTROL BUS

Maximum SCLK Frequency (f

Minimum Clock Pulse Width High (t

Minimum Clock Pulse Width Low (t

Maximum Clock Rise/Fall Time 1 ms

Minimum Data/Chip Select Setup Time (tDS) 25 ns

Minimum Data Hold Time (tDH) 0 ns

Maximum Data Valid Time (tDV) 30 ns

RESET Pulse Width 1.5 ns

Inputs (SDI, SDIO, SCLK, CSB)

SDIO Output

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

) 15 MHz

SLCK

) 30 ns

PWH

) 30 ns

PWL

= 20 mA, unless otherwise noted.

OUTFS

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF

Logic 1 Voltage DRVDD – 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA

Rev. C | Page 7 of 60

AD9775

Digital Filter Specifications

Table 4. Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8 2, 42 0 3, 41 −29 4, 40 0 5, 39 67 6, 38 0 7, 37 −134 8, 36 0 9, 35 244 10, 34 0 11, 33 −414 12, 32 0 13, 31 673 14, 30 0 15, 29 −1079 16, 28 0 17, 27 1,772 18, 26 0 19, 25 −3,280 20, 24 0 21, 23 10,364 22 16,384

Table 5. Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19 2, 18 0 3, 17 −120 4, 16 0 5, 15 438 6, 14 0 7, 13 −1,288 8, 12 0 9, 11 5,047 10 8,192

Table 6. Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7 2, 10 0 3, 9 −53 4, 8 0 5, 7 302 6 512

ATTENUATION (dBFS)

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

–120

20

0

0.50 1.0 1.5 2.0

f

(NORMALIZED TO INPUT DATA RATE)

OUT

02858-C-002

Figure 2. 2× Interpolating Filter Response

20

0

0.50 1.0 1.5 2.0

f

(NORMALIZED TO INPUT DATA RATE)

OUT

02858-C-003

Figure 3. 4× Interpolating Filter Response

20

0

20468

f

(NORMALIZED TO INPUT DATA RATE)

OUT

02858-C-004

Figure 4. 8× Interpolating Filter Response

Rev. C | Page 8 of 60

AD9775

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter With Respect To Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V I

, I

OUTA

P1B13 to P1B0, P2B13 to P2B0 DGND −0.3 DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK–, RESET CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, DGND −0.3 DVDD + 0.3 V SPI_SDIO, SPI_SDO Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

AGND −1.0 AVDD + 0.3 V

OUTB

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced TQFP Package

= 23.5°C/W (with thermal pad soldered to PCB)

θ

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 9 of 60

AD9775

2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLKVDD

LPF CLKVDD CLKGND

CLK+ CLK–

CLKGND

DATACLK/PLL_LOCK

DGND DVDD

P1B13 (MSB)

P1B12 P1B11 P1B10

P1B9 P1B8

DGND

DVDD

P1B7 P1B6

NC = NO CONNECT

OUTA1IOUTA

AVDD

AGND

PIN 1 IDENTIFIER

P1B5

P1B4

AGND

P1B3

P1B2

DGND

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

AGND

P1B1

DVDD

OUTB1

I

AD9775

TxDAC+

TOP VIEW

(Not to Scale)

NC

AGND

NC

OUTB

I

P2B11

AGND

DGND

P2B10

AVDD

DVDD

P1B0 (LSB)

IQSEL/P2B13 (MSB)

ONEPORTCLK/P2B12

Figure 5. Pin Configuration

AGND

AVDD

P2B9

P2B8

AGND

AVDD

P2B7

P2B6

60

FSADJ1

59

FSADJ2

58

REFIO

57

RESET

56

SPI_CSB

55

SPI_CLK

54

SPI_SDIO

53

SPI_SDO

52

DGND

51

DVDD

50

NC

49

NC

48

P2B0 (LSB)

47

P2B1

46

P2B2

45

P2B3

44

DGND

43

DVDD

42

P2B4

41

P2B5

02858-C-005

Rev. C | Page 10 of 60

AD9775

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK

9, 17, 25,

DGND Digital Common.

35, 44, 52 10, 18, 26,

DVDD Digital Supply Voltage.

36, 43, 51 11 to 16, 19

to 24, 27, 28 29, 30, 49,

P1B13 (MSB) to P1B0 (LSB)

NC No Connect.

50 31 IQSEL/P2B13 (MSB)

32 ONEPORTCLK/P2B12

33, 34,

P2B11 to P2B0 (LSB) Port 2 Data Inputs. 37 to 42, 45 to 48

53 SPI_SDO

54 SPI_SDIO

55 SPI_CLK

56 SPI_CSB

57 RESET

58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65,

AVDD Analog Supply Voltage. 76, 78, 80

62, 64, 66,

AGND Analog Common. 67, 70, 71, 74, 75, 77, 79

68, 69 I 72, 73 I

, I

OUTB2

OUTA2

OUTB1, IOUTA1

Differential DAC Current Outputs, Q Channel.

Differential DAC Current Outputs, I Channel.

With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate.

Port 1 Data Inputs.

In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock will latch the data into the I channel input register. IQSEL = 0 will latch the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB.

With the PLL disabled and the AD9775 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9775 to accept and demux interleaved I and Q data to the I and Q input registers.

In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two-Port Data Input Mode section.

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle.

Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bit in Address 00h.

Rev. C | Page 11 of 60

AD9775

DEFINITIONS OF SPECIFICATIONS

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Offset Error

The deviation of the output current from the ideal of 0 is called offset error. For I are all 0. For I

, 0 mA output is expected when the inputs

OUTA

, 0 mA output is expected when all inputs are

OUTB

set to 1.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Complex Modulation

The process of passing the real and imaginary components of a

jωt

signal through a complex modulator (transfer function = e

= cosωt + jsinωt) and realizing real and imaginary components on the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.

Group Delay

Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed with

f

DATA

a sharp transition band near fDATA/2. Images that would typically appear around f

(output data rate) can be greatly

DAC

suppressed.

Linearity Error (Also Called Integral Nonlinearity or INL)

It is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Temperature Drift

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

Rev. C | Page 12 of 60

AD9775

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I 50 Ω doubly terminated, unless otherwise noted.

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 65 130

FREQUENCY (MHz)

Figure 6. Single-Tone Spectrum @ f

90

85

80

0dBFS

–6dBFS

= 65 MSPS with f

DATA

OUT

= f

DATA

= 20 mA, Interpolation = 2×, differential transformer coupled output,

OUTFS

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 10050 150

FREQUENCY (MHz)

= 78 MSPS with f

DATA

0dBFS

/3

02858-C-006

Figure 9. Single-Tone Spectrum @ f

90

85

80

OUT

= f

DATA

02858-C-009

/3

75

70

SFDR (dBc)

65

60

55

50

–12dBFS

Figure 7. In-Band SFDR vs. f

90

85

80

75

70

–12dBFS

SFDR (dBc)

65

60

55

50

–6dBFS

0dBFS

Figure 8. Out-of-Band SFDR vs. f

10 150 5 20 25 30

FREQUENCY (MHz)

@ f

OUT

@ f

DATA

= 65 MSPS

OUT

10 150 5 20 25 30

FREQUENCY (MHz)

02858-C-007

02858-C-008

75

–12dBFS

70

SFDR (dBc)

65

60

55

50

–6dBFS

Figure 10. In-Band SFDR vs. f

90

85

–6dBFS

80

75

70

SFDR (dBc)

65

60

55

50

0dBFS

–12dBFS

Figure 11. Out-of-Band SFDR vs. f

10 150 5 20 25 30

FREQUENCY (MHz)

@ f

OUT

= 78 MSPS

DATA

@ f

DATA

= 78 MSPS

OUT

10 150 5 20 25 30

FREQUENCY (MHz)

02858-C-010

02858-C-011

Rev. C | Page 13 of 60

AD9775

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 200100 300

FREQUENCY (MHz)

Figure 12. Single-Tone Spectrum @ f

90

–6dBFS

85

80

0dBFS

= 160 MSPS with f

DATA

OUT

= f

DATA

/3

02858-C-012

90

85

80

75

70

IMD (dBc)

65

60

55

50

–6dBFS

0dBFS

10 150 5 20 25 30

FREQUENCY (MHz)

Figure 15. Third-Order IMD Products vs. f

90

85

80

–6dBFS

–3dBFS

OUT

@ f

= 65 MSPS

DATA

0dBFS

02858-C-015

75

70

–12dBFS

SFDR (dBc)

65

60

55

50

0 1020304050

FREQUENCY (MHz)

Figure 13. In-Band SFDR vs. f

90

85

80

75

70

SFDR (dBc)

65

60

55

50

–6dBFS

0dBFS

–12dBFS

0 1020304050

FREQUENCY (MHz)

Figure 14. Out-of-Band SFDR vs. f

OUT

@ f

OUT

@ f

= 160 MSPS

DATA

= 160 MSPS

DATA

02858-C-013

02858-C-014

75

70

IMD (dBc)

65

60

55

50

10 150 5 20 25 30

FREQUENCY (MHz)

Figure 16. Third-Order IMD Products vs. f

90

85

80

75

70

IMD (dBc)

65

60

55

50

–3dBFS

20 300 10 405060

FREQUENCY (MHz)

Figure 17. Third-Order IMD Products vs. f

0dBFS

–3dBFS

OUT

–6dBFS

@ f

OUT

@ f

DATA

= 78 MSPS

= 160 MSPS

02858-C-016

02858-C-017

Rev. C | Page 14 of 60

AD9775

90

8

85

×

90

–3dBFS

85

80

75

70

IMD (dBc)

65

60

55

50

Figure 18. Third-Order IMD Products

1× f

4× f

90

85

80

75

70

IMD (dBc)

65

60

55

50

–15 –5–10 0

Figure 19. Third-Order IMD Products vs. A

= 50 MSPS for All Cases, 1× f

f

DATA

4× f

90

85

4

×

20 300 10 405560

FREQUENCY (MHz)

= 160 MSPS, 2× f

DATA

= 80 MSPS, 8× f

DATA

= 200 MSPS, 8× f

DAC

1

×

vs. f

4

×

2

×

A

(dBFS)

OUT

= 50 MSPS, 2× f

DAC

2

×

and Interpolation Rate,

OUT

= 160 MSPS,

DATA

= 50 MSPS

DATA

8

×

1

×

and Interpolation Rate

OUT

= 400 MSPS

DAC

0dBFS

= 100 MSPS,

DAC

02858-C-018

02858-C-019

80

75

70

SFDR (dBc)

65

60

55

50

–6dBFS

3.23.1 3.3 3.4 3.5

0dBFS

AVDD (V)

Figure 21. Third-Order IMD Products vs. AVDD @ f

f

= 320 MSPS, f

DAC

90

85

80

75

70

SNR (dB)

65

60

55

50

0 10050 150

PLL ON

INPUT DATA RATE (MSPS)

Figure 22. SNR vs. Data Rate for f

90

85

78MSPS

DATA

PLL OFF

= 160 MSPS

OUT

= 5 MHz

= 10 MHz,

02858-C-021

02858-C-022

80

75

70

SFDR (dBc)

65

60

55

50

–12dBFS

3.23.1 3.3 3.4 3.5

Figure 20. SFDR vs. AVDD @ f

AVDD (V)

= 10 MHz, f

OUT

–6dBFS

DAC

= 320 MSPS, f

= 160 MSPS

DATA

02858-C-020

Rev. C | Page 15 of 60

80

75

70

SFDR (dBc)

65

60

55

50

–50 500 100

f

= 65MSPS

DATA

TEMPERATURE (°C)

Figure 23. SFDR vs. Temperature @ f

160MSPS

= f

OUT

DATA

/11

02858-C-023

AD9775

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 10050 150

FREQUENCY (MHz)

Figure 24. Single-Tone Spurious Performance, f

f

= 150 MSPS, No Interpolation

DATA

0

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

01020304050

FREQUENCY (MHz)

Figure 25. Two-Tone IMD Performance, f

0

–10

–20

–30

–40

–50

–60

AMPLIFIER (dBm)

–70

–80

–90

–100

100 1500 50 200 250 300

FREQUENCY (MHz)

= 150 MSPS, No Interpolation

DATA

Figure 26. Single-Tone Spurious Performance, f

f

= 150 MSPS, Interpolation = 2×

DATA

OUT

= 10 MHz,

02858-C-024

02858-C-025

02858-C-026

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 5 10 15 20 25 30 35 40 45 50

FREQUENCY (MHz)

Figure 27. Two-Tone IMD Performance, f

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

100 1500 50 200 250 300

FREQUENCY (MHz)

= 150 MSPS, Interpolation = 4×

DATA

Figure 28. Single-Tone Spurious Performance, f

f

= 80 MSPS, Interpolation = 4×

DATA

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 5 10 15 20 25

FREQUENCY (MHz)

Figure 29. Two-Tone IMD Performance, f

f

= 50 MSPS, Interpolation = 8×

DATA

OUT

= 10 MHz,

OUT

= 10 MHz,

02858-C-027

02858-C-028

02858-C-029

Rev. C | Page 16 of 60

AD9775

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

1000 200 300 400

FREQUENCY (MHz)

Figure 30. Single-Tone Spurious Performance, f

f

= 50 MSPS, Interpolation = 8×

DATA

= 10 MHz,

OUT

02858-C-030

0

–20

–40

–60

–80

AMPLITUDE (dBm)

–100

–120

200406080

FREQUENCY (MHz)

Figure 31. Eight-Tone IMD Performance, f

= 160 MSPS, Interpolation = 8×

DATA

02858-C-031

Rev. C | Page 17 of 60

AD9775

MODE CONTROL (VIA SPI PORT)

Table 9. Mode Control via SPI Port (Default Values Are Highlighted)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h

01h

02h

SDIO Bidirectional 0 = Input 1 = I/O

Filter Interpolation Rate (1×, 2×, 4×, 8×)

0 = Signed Input Data

1 = Unsigned

LSB, MSB First 0 = MSB 1 = LSB

Filter Interpolation Rate (1×, 2×, 4×, 8×)

0 = Two-Port Mode

1 = One-Port

Software Reset on Logic 1

Modulation Mode

/4, fS/8)

S

/2,

(None, f f

DATACLK Driver Strength

Mode

03h

04h

Data Rate Clock

1

Output

0 = PLL OFF

1 = PLL ON

1

0 = Automatic Charge Pump Control

1 = Programmable

05h

IDAC Fine Gain Adjustment

06h

07h

08h

IDAC Offset Adjustment Bit 9

IDAC I

OFFSET

IDAC Offset Adjustment Bit 8

IDAC Offset Adjustment Bit 7

Direction

OFFSET

OUTA

OFFSET

OUTB

QDAC Fine Gain Adjustment

09h

0 = I on I

1 = I on I

QDAC Fine Gain Adjustment

Sleep Mode Logic 1 shuts down the DAC output currents

Modulation Mode (None, f f

S

/4, fS/8)

S

/2,

DATACLK Invert

0 = No Invert

1 = Invert

IDAC Fine Gain Adjustment

IDAC Offset Adjustment Bit 6

QDAC Fine Gain Adjustment

Power-Down Mode Logic 1 shuts down all digital and analog functions

0 = No Zero Stuffing on Interpolation Filters, Logic 1

enables zero stuffing.

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 5

QDAC Fine Gain Adjustment

1R/2R Mode DAC output current set by one or two external resistors.

0 = 2R, 1 = 1R 1 = Real

Mix Mode

0 = Complex Mix Mode

ONEPORTCLK Invert

0 = No Invert

1 = Invert

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 4

QDAC Fine Gain Adjustment

PLL_LOCK Indicator

−jωt

0 = e

+jωt

1 = e

IQSEL Invert

0 = No Invert

1 = Invert PLL Divide

(Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 3

IDAC Offset Adjustment Bit 1

QDAC Fine Gain Adjustment

DATACLK/ PLL_LOCK Select

0 = PLLLOCK

1 = DATACLK

Q First 0 = I First 1 = Q First

PLL Divide (Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 2

IDAC Offset Adjustment Bit 0

QDAC Fine Gain Adjustment

1

Rev. C | Page 18 of 60

Analog Devices AD9775 c Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DEFINITIONS OF SPECIFICATIONS

TYPICAL PERFORMANCE CHARACTERISTICS

MODE CONTROL (VIA SPI PORT)