Analog Devices AD9775EB, AD9775BSV Datasheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD9775

*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

14-Bit, 160 MSPS 2ⴛ/4ⴛ/8ⴛ

Interpolating Dual TxDAC+

®

D/A Converter

FUNCTIONAL BLOCK DIAGRAM

DIFFERENTIAL
CLK

COS

SIN

HALF­BAND

FILTER 1

16

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

I AND Q

NONINTERLEAVED

OR

INTERLEAVED

DATA

WRITE

SELECT

CLOCK OUT

HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR "ZERO STUFFING ONLY"

*

GAIN
DAC

OFFSET

DAC

f

DAC

/2, 4, 8

SIN

COS

I/Q DAC

GAIN/OFFSET

REGISTERS

IOFFSET

VREF

(

f

DAC

)

PHASE DETECTOR

AND VCO

PRESCALER

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

16

16

/2

16

DATA

ASSEMBLER

1616

16

16

16

16

MUX

CONTROL

/2

/2

I

LATCH

Q

LATCH

/2

HALF­BAND

FILTER 2

HALF­BAND

FILTER 3

***

AD9775

SPI INTERFACE AND

CONTROL REGISTERS

FILTER

BYPASS

MUX

IDAC

IDAC

I

OUT

FEATURES
14-Bit Resolution, 160/400 MSPS Input/Output Data Rate
Selectable 2ⴛ/4ⴛ/8ⴛ Interpolating Filter
Programmable Channel Gain and Offset Adjustment
f

S

/4, fS/8 Digital Quadrature Modulation

Capability
Direct IF Transmission Mode for 70 MHz + IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance

SFDR –71 dBc @ 2 MHz–35 MHz

WCDMA ACPR –71 dB @ IF = 71 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input

Differential/Single-Ended Sine Wave or

TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface

Two’s Complement/Straight Binary Data Coding

Dual-Port or Single-Port Interleaved Input Data
Single 3.3 V Supply Operation
Power Dissipation: Typical 1.2 W @ 3.3 V
On-Chip 1.2 V Reference
80-Lead Thermally Enhanced TQFP Package

GENERAL DESCRIPTION

The AD9775 is the 14-bit member of the AD977x pin-compatible,
high performance, programmable 2×/4×/8× interpolating TxDAC+
family. The AD977x family features a serial port interface (SPI)
providing a high level of programmability, thus allowing for
enhanced system-level options. These options include: select­able 2×/4×/8× interpolation filters; f

S

/2, fS/4, or fS/8 digital
quadrature modulation with image rejection; a direct IF mode;
programmable channel gain and offset control; programmable
internal clock divider; straight binary or two’s complement data
interface; and a single-port or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the require­ments of the reconstruction filters while simultaneously enhancing
the TxDAC+ family’s pass-band noise/distortion performance.
The independent channel gain and offset adjust registers allow
the user to calibrate LO feedthrough and sideband suppression

(continued on page 2)

APPLICATIONS
Communications

Analog Quadrature Modulation Architectures
3G, Multicarrier GSM, TDMA, CDMA Systems
Broadband Wireless, Point-to-Point Microwave Radios
Instrumentation/ATE

TxDAC+ is a registered trademark of Analog Devices, Inc.

*Protected bu U.S. Patent Numbers 5568145, 5689257, and 5703519. Other Patents pending.

REV. 0

AD9775

–2–

(continued from page 1)

errors associated with analog quadrature modulators. The 6 dB
of gain adjustment range can also be used to control the output
power level of each DAC.

The AD9775 features the ability to perform f

S

/2, fS/4, and fS/8
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9775 ac­cepts I and Q complex data (representing a single or multicarrier
waveform), generates a quadrature modulated IF signal along with
its orthogonal representation via its dual DACs, and presents
these two reconstructed orthogonal IF carriers to an analog
quadrature modulator to complete the image rejection
upconversion process. Another digital modulation mode (i.e.,
the Direct IF Mode) allows the original baseband signal repre­sentation to be frequency translated such that pairs of images fall
at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs. An
internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source.
An internal programmable divider simplifies clock generation in
the converter when using an external clock source. A flexible data
input interface allows for straight binary or two’s complement
formats and supports single-port interleaved or dual-port data.

Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9775 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard
systems, the superb baseband performance of the AD9775 is ideal
for wideband CDMA, multicarrier CDMA, multicarrier TDMA,
multicarrier GSM, and high performance systems employing
high order QAM modulation schemes. The image rejection
feature simplifies and can help to reduce the number of signal
band filters needed in a transmit signal chain. The direct IF
mode helps to eliminate a costly mixer stage for a variety of
communications systems.

PRODUCT HIGHLIGHTS

1. The AD9775 is the 14-bit member of the AD977x pin-

compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.

2. Direct IF transmission capability for 70 MHz + IFs through
a novel digital mixing process.

3. f

S

/2, fS/4, and fS/8 digital quadrature modulation and user­selectable image rejection to simplify/remove cascaded
SAW filter stages.

4. A 2×/4×/8× user-selectable interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User-selectable two’s complement/straight binary data
coding.

6. User-programmable channel gain control over 1 dB
range in 0.01 dB increments.

7. User-programmable channel offset control ± 10% over
the FSR.

8. Ultra high speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy
interfacing.

10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W
from a 3.1 V to 3.5 V single supply. The 20 mA full-scale
current can be reduced for lower power operation and
several sleep functions are provided to reduce power dur­ing idle periods.

12. On-chip voltage reference: The AD9775 includes a 1.20 V
temperature compensated band gap voltage reference.

13. 80-lead thermally enhanced TQFP.

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–3–

AD9775

DC SPECIFICATIONS

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC Accuracy

1

Integral Nonlinearity –5 ±1.5 +5 LSB
Differential Nonlinearity –3 ±1.0 +3 LSB

ANALOG OUTPUT (for IR and 2R Gain Setting Modes)

Offset Error –0.02 ±0.01 +0.02 % of FSR

Gain Error (With Internal Reference) –1.0 +1.0 % of FSR
Gain Matching –1.0 ± 0.1 +1.0 % of FSR
Full-Scale Output Current

2

220mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 200 kΩ
Output Capacitance 3 pF
Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (REFLO = 3 V) 10 MΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift (With Internal Reference) 50 ppm of FSR/°C
Reference Voltage Drift ppm/°C

POWER SUPPLY

AVDD

Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I

AVDD

)

4

72.5 76 mA

I

AVDD

in SLEEP Mode 23.3 26 mA

CLKVDD

Voltage Range 3.1 3.3 3.5 V
Clock Supply Current (I

CLKVDD

)

4

8.5 mA

CLKVDD (PLL ON)

Clock Supply Current (I

CLKVDD

)23.5mA

DVDD

Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I

DVDD

)

4

34 41 mA
Nominal Power Dissipation 380 410 mW
P

DIS

5

1.75 W

P

DIS

IN PWDN 6.0 mW

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

OUTA

driving a virtual ground.

2

Nominal full-scale current, I

OUTFS

, is 32× the I

REF

current.

3

Use an external amplifier to drive any external load.

4

100 MSPS f

DAC

with f

OUT

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

5

400 MSPS f

DAC

= 50 MSPS, fS/2 modulation, PLL enabled.

Specifications subject to change without notice.

(T

MIN

to T

MAX

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

OUTFS

= 20 mA, unless

otherwise noted.)

AD9775–SPECIFICATIONS

REV. 0

–4–

AD9775

DYNAMIC SPECIFICATIONS

(T

MIN

to T

MAX

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

OUTFS

= 20 mA,
Interpolation = 2ⴛ, Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated,
unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f

DAC

) 400 MSPS

Output Settling Time (t

ST

) (to 0.025%) 11 ns

Output Rise Time (10% to 90%)* 0.8 ns
Output Fall Time (10% to 90%)* 0.8 ns
Output Noise (I

OUTFS

= 20 mA) 50 pA√Hz

AC LINEARITY—–BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

OUT

= 0 dBFS)

f

DATA

= 100 MSPS, f

OUT

= 1 MHz 71 84.5 dBc

f

DATA

= 65 MSPS, f

OUT

= 1 MHz 84 dBc

f

DATA

= 65 MSPS, f

OUT

= 15 MHz 80 dBc

f

DATA

= 78 MSPS, f

OUT

= 1 MHz 84 dBc

f

DATA

= 78 MSPS, f

OUT

= 15 MHz 80 dBc

f

DATA

= 160 MSPS, f

OUT

= 1 MHz 82 dBc

f

DATA

= 160 MSPS, f

OUT

= 15 MHz 80 dBc

Spurious-Free Dynamic Range within a 1 MHz Window

(f

OUT

= 0 dBFS, f

DATA

= 100 MSPS, f

OUT

= 1 MHz) 73 91.3 dBc

Two-Tone Intermodulation (IMD) to Nyquist (f

OUT1

= f

OUT2

= –6 dBFS)

f

DATA

= 65 MSPS, f

OUT1

= 10 MHz; f

OUT2

= 11 MHz 81 dBc

f

DATA

= 65 MSPS, f

OUT1

= 20 MHz; f

OUT2

= 21 MHz 76 dBc

f

DATA

= 78 MSPS, f

OUT1

= 10 MHz; f

OUT2

= 11 MHz 81 dBc

f

DATA

= 78 MSPS, f

OUT1

= 20 MHz; f

OUT2

= 21 MHz 76 dBc

f

DATA

= 160 MSPS, f

OUT1

= 10 MHz; f

OUT2

= 11 MHz 81 dBc

f

DATA

= 160 MSPS, f

OUT1

= 20 MHz; f

OUT2

= 21 MHz 76 dBc

Total Harmonic Distortion (THD)

f

DATA

= 100 MSPS, f

OUT

= 1 MHz; 0 dBFS –71 –82.5 dB

Signal-to-Noise Ratio (SNR)

f

DATA

= 78 MSPS, f

OUT

= 5 MHz; 0 dBFS 76 dB

f

DATA

= 160 MSPS, f

OUT

= 5 MHz; 0 dBFS 74 dB

Adjacent Channel Power Ratio (ACLR)

WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing

IF = Baseband, f

DATA

= 76.8 MSPS 75 dBc

IF = 19.2 MHz, f

DATA

= 76.8 MSPS 73 dBc

Four-Tone Intermodulation

21 MHz, 22 MHz, 23 MHz, and 24 MHz at –12 dBFS 75 dBFS
(f

DATA

= MSPS, Missing Center)

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

MHz, MHz, MHz, and MHz at dBFS 72 dBFS
(f

DATA

= MSPS, f

DAC

= MHz)

*Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

REV. 0

–5–

AD9775

DIGITAL SPECIFICATIONS

(T

MIN

to T

MAX

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

OUTFS

= 20 mA, unless

otherwise noted.)

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic “1” Voltage 2.1 3 V
Logic “0” Voltage 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

Specifications subject to change without notice.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9775 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect to Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND –0.3 +4.0 V
AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD –4.0 +4.0 V
AGND, DGND, CLKGND AGND, DGND, CLKGND –0.3 +0.3 V
REFIO, REFLO, FSADJ1/2 AGND –0.3 AVDD + 0.3 V
I

OUTA

, I

OUTB

AGND –1.0 AVDD + 0.3 V

P1B13–P1B0, P2B13–P2B0 DGND –0.3 DVDD + 0.3 V
DATACLK, PLL_LOCK DGND –0.3 DVDD + 0.3 V
CLK+, CLK–, RESET CLKGND –0.3 CLKVDD + 0.3 V
LPF CLKGND –0.3 CLKVDD + 0.3 V
SPI_CSB, SPI_CLK, DGND –0.3 DVDD + 0.3 V
SPI_SDIO, SPI_SDO
Junction Temperature +125 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

*Stresses above those listed under the ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9775BSV –40°C to +85°C 80-Lead TQFP SV-80
AD9775EB Evaluation Board

*SV = Thin Plastic Quad Flatpack

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced
TQFP Package ␪

JA

= 23.5 °C/W*

*With thermal pad soldered to PCB.

REV. 0

AD9775

–6–

PIN CONFIGURATION

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

12

17

18

20

19

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

NC = NO CONNECT

AVDD

AGND

AVDD

AGND

AVDD

AGND

AGND

I

OUTA1

I

OUTB1

AGND

AGND

I

OUTA2

I

OUTB2

AGND

AGND

AVDD

AGND

AVDD

AGND

AVDD

CLKVDD

LPF

CLKVDD

CLKGND

CLK+

CLK–

DATACLK/PLL_LOCK

DGND

DVDD

P1B13 (MSB)

P1B12

P1B11

P1B10

P1B9

P1B8

DGND

DVDD

P1B7

P1B6

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

NC

NC

P2B0 (LSB)

P2B1

P2B2

P2B3

P1B5

P1B4

P1B3

P1B2

DGND

DVDD

P1B1

P1B0 (LSB)

NC

NC

ONEPORTCLK/P2B12

P2B11

P2B10

DGND

DVDD

IQSEL/P2B13 (MSB)

AD9775

TxDAC+

DGND

DVDD

P2B4

P2B5

P2B9

P2B8

P2B7

P2B6

CLKGND

REV. 0

AD9775

–7–

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage
2 LPF PLL Loop Filter
4, 7 CLKGND Clock Supply Common
5 CLK+ Differential Clock Input
6 CLK– Differential Clock Input
8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a

Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the
PLL has not achieved lock. This pin may also be programmed to act as
either an input or output (Address 02h, Bit 3) DATACLK signal running at

the input data rate.
9, 17, 25, 35, 44, 52 DGND Digital Common
10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage
11–16, 19–24, 27, 28 P1B13 (MSB) to P1B0 (LSB) Port “1” Data Inputs
29, 30, 49, 50 NC No Connect
31 IQSEL/P2B13 (MSB) In “1” port mode, IQSEL = 1 followed by a rising edge of the differential

input clock will latch the data into the I channel input register. IQSEL = 0

will latch the data into the Q channel input register. In “2” port mode, this

pin becomes the port “2” MSB.
32 ONEPORTCLK/P2B12 With the PLL disabled and the AD9775 in “1” port mode, this pin becomes

a clock output that runs at twice the input data rate of the I and Q channels.

This allows the AD9775 to accept and demux interleaved I and Q data to

the I and Q input registers.
33, 34, 37–42, 45–48 P2B11 to P2B0 (LSB) Port “2” Data Inputs
53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO

becomes an output, SDO enters a High-Z state.
54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register

Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.
55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK.

Data output on the SPI port is registered on the falling edge.
56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets

SPI port logic and initializes instruction cycle.
57 RESET Logic “1” resets all of the SPI port registers, including Address 00h, to their

default values. A software reset can also be done by writing a Logic “1” to

SPI Register 00h, Bit 5. However, the software reset has no effect on the bits

in Address 00h.
58 REFIO Reference Output, 1.2 V Nominal
59 FSADJ2 Full-Scale Current Adjust, Q Channel
60 FSADJ1 Full-Scale Current Adjust, I Channel
61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage
62, 64, 66, 67, 70, 71, AGND Analog Common

74, 75, 77, 79
68, 69 I

OUTA2

, I

OUTB2

Differential DAC Current Outputs, Q Channel
72, 73 I

OUTA1

, I

OUTB1

Differential DAC Current Outputs, I Channel

REV. 0

AD9775

–8–

DIGITAL FILTER SPECIFICATIONS

Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8
2, 42 0
3, 41 –29
4, 40 0
5, 39 67
6, 38 0
7, 37 –134
8, 36 0
9, 35 244
10, 34 0
11, 33 –414
12, 32 0
13, 31 673
14, 30 0
15, 29 –1079
16, 28 0
17, 27 1772
18, 26 0
19, 25 –3280
20, 24 0
21, 23 10364
22 16384

Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19
2, 18 0
3, 17 –120
4, 16 0
5, 15 438
6, 14 0
7, 13 –1288
8, 12 0
9, 11 5047
10 8192

Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7
2, 10 0
3, 9 –53
4, 8 0
5, 7 302
6 512

f

OUT

– Normalized to Input Data Rate

–120

0 0.5

ATTENUATION – dBFS

–100

–80

–60

–40

–20

0

20

1.0 1.5 2.0

Figure 1a. 2ⴛ Interpolating Filter Response

f

OUT

– Normalized to Input Data Rate

–120

0 0.5

ATTENUATION – dBFS

–100

–80

–60

–40

–20

0

20

1.0 1.5 2.0

Figure 1b. 4ⴛ Interpolating Filter Response

f

OUT

– Normalized to Input Data Rate

–120

02

ATTENUATION – dBFS

–100

–80

–60

–40

–20

0

20

468

Figure 1c. 8ⴛ Interpolating Filter Response

REV. 0

AD9775

–9–

DEFINITIONS OF SPECIFICATIONS

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex modu­lator in series with the first complex modulator, either the upper
or lower frequency image near the second IF can be rejected.

Complex Modulation

The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e

j␻t

=
cos␻t + jsin␻t) and realizing real and imaginary components on
the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to “1,” minus the output when all inputs are set to “0.”

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV

–S

.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of
f

DATA

(interpolation rate), a digital filter can be constructed

with a sharp transition band near f

DATA

/2. Images that would

typically appear around f

DAC

(output data rate) can be greatly

suppressed.

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.

Monotonicity

A D/A converter is monotonic if the output either increases
or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of “0” is
called offset error. For I

OUTA

, 0 mA output is expected when the

inputs are all “0.” For I

OUTB

, 0 mA output is expected when all

inputs are set to “1.”

Output Compliance Range

The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).

REV. 0

AD9775

–10–

FREQUENCY – MHz

AMPLITUDE – dBm

–90

0

65 130

–80

–70

–60

–50

–40

–30

–20

–10

0

10

TPC 1. Single-Tone Spec­trum @ f

DATA

= 65 MSPS with

f

OUT

= f

DATA

/3

FREQUENCY – MHz

AMPLITUDE – dBm

–90

0

50 150

–80

–70

–60

–50

–40

–30

–20

–10

0

10

100

TPC 4. Single-Tone Spec­trum @ f

DATA

= 78 MSPS with

f

OUT

= f

DATA

/3

FREQUENCY – MHz

AMPLITUDE – dBm

–90

0

100 300

–80

–70

–60

–50

–40

–30

–20

–10

0

10

200

TPC 7. Single-Tone Spec­trum @ f

DATA

= 160 MSPS

with f

OUT

= f

DATA

/3

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

–12dBFS

–6dBFS

0dBFS

TPC 2. In-Band SFDR vs. f

OUT

@ f

DATA

= 65 MSPS

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

–6dBFS

–12dBFS

0dBFS

TPC 5. In-Band SFDR vs. f

OUT

@ f

DATA

= 78 MSPS

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

–6dBFS

–12dBFS

0dBFS

40 50

TPC 8. In-Band SFDR vs. f

OUT

@ f

DATA

= 160 MSPS

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

–12dBFS

0dBFS

–6dBFS

TPC 3. Out-of-Band SFDR vs.
f

OUT

@ f

DATA

= 65 MSPS

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

–12dBFS

0dBFS

–6dBFS

TPC 6. Out-of-Band SFDR vs.
f

OUT

@ f

DATA

= 78 MSPS

FREQUENCY – MHz

SFDR – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

–6dBFS

–12dBFS

0dBFS

40 50

TPC 9. Out-of-Band SFDR vs.
f

OUT

@ f

DATA

= 160 MSPS

–Typical Performance Characteristics

(T = 25ⴗC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I

OUTFS

= 20 mA, Interpolation = 2ⴛ, Differential Coupled Transformer Output, 50 ⍀

Doubly Terminated, unless otherwise noted.)

REV. 0

–11–

AD9775

FREQUENCY – MHz

IMD – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

0dBFS

–3dBFS

–6dBFS

TPC 10. Third Order IMD
Products vs. f

OUT

@ f

DATA

=

65 MSPS

FREQUENCY – MHz

IMD – dBc

50

0

40 60

55

60

65

70

75

80

85

90

20

8ⴛ

4ⴛ

1ⴛ

2ⴛ

30 5510

TPC 13. Third Order IMD
Products vs. f

OUT

and
Interpolation Rate,
1ⴛ f

DATA

= 160 MSPS,

2

ⴛ

f

DATA

= 160 MSPS,

4ⴛ f

DATA

= 80 MSPS,

8ⴛ f

DATA

= 50 MSPS

AVDD – V

SFDR – dBc

50

3.5

55

60

65

70

75

80

85

90

0dBFS

3.43.33.23.1

–3dBFS

–6dBFS

TPC 16. Third Order IMD
Products vs. AVDD @ f

OUT

=

10 MHz, f

DAC

= 320 MSPS,

f

DATA

= 160 MSPS

FREQUENCY – MHz

IMD – dBc

50

0

20 30

55

60

65

70

75

80

85

90

10

15 255

–3dBFS

0dBFS

–6dBFS

TPC 11. Third Order IMD
Products vs. f

OUT

@ f

DATA

=

78 MSPS

A

OUT

– dBFS

IMD – dBc

50

–5 0

55

60

65

70

75

80

85

90

–10

8ⴛ

4ⴛ

1ⴛ

2ⴛ

–15

TPC 14. Third Order IMD
Products vs. A

OUT

and Inter-

polation Rate f

DATA

= 50
MSPS for All Cases,
1

ⴛ

f

DAC

= 50 MSPS,

2ⴛ f

DAC

= 100 MSPS,

4ⴛ f

DAC

= 200 MSPS,

8

ⴛ

f

DAC

= 400 MSPS

SNR – dB

55

60

65

70

75

80

85

90

INPUT DATA RATE – MSPS

050 150100

50

PLL ON

PLL OFF

TPC 17. SNR vs. Data Rate
for f

OUT

= 5 MHz

FREQUENCY – MHz

IMD – dBc

50

0

40 60

55

60

65

70

75

80

85

90

20

30 5010

–3dBFS

0dBFS

–6dBFS

TPC 12. Third Order IMD
Products vs. f

OUT

@ f

DATA

=

160 MSPS

AVDD – V

SFDR – dBc

50

3.5

55

60

65

70

75

80

85

90

0dBFS

3.43.33.23.1

–6dBFS

–12dBFS

TPC 15. SFDR vs. AVDD @
f

OUT

= 10 MHz, f

DAC

= 320 MSPS,

f

DATA

= 160 MSPS

TEMPERATURE – ⴗC

SFDR – dBc

90

85

50

–50 0 100

50

70

65

55

60

80

75

FDATA = 65MSPS

160MSPS

78MSPS

TPC 18. SFDR vs. Temperature
@ f

OUT

= f

DATA

/11

(T = 25ⴗC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I

OUTFS

= 20 mA, Interpolation = 2ⴛ, Differential Coupled Transformer Output, 50 ⍀

Doubly Terminated, unless otherwise noted.)

REV. 0

AD9775

–12–

FREQUENCY – MHz

AMPLITUDE – dBm

0

–10

–100

050 150

100

–70

–90

–80

–50

–60

–20

–40

–30

TPC 19. Single-Tone Spuri­ous Performance, f

OUT

=

10 MHz, f

DATA

= 150 MSPS,

No Interpolation

FREQUENCY – MHz

AMPLITUDE – dBm

0

–20

–100

05 50

10 15 20 25 30 35 40 45

–40

–60

–80

–10

–30

–50

–40

–90

TPC 22. Two-Tone IMD Per­formance, f

DATA

= 150 MSPS,

Interpolation = 4

ⴛ

FREQUENCY – MHz

AMPLITUDE – dBm

0

–10

–100

0 100 400200 300

–60

–70

–80

–90

–20

–30

–40

–50

TPC 25. Single-Tone Spuri­ous Performance, f

OUT

=

10 MHz, f

DATA

= 50 MSPS,

Interpolation = 8

ⴛ

FREQUENCY – MHz

AMPLITUDE – dBm

0

–20

–100

010 50

20 30 40

–40

–60

–80

TPC 20. Two-Tone IMD Per­formance, f

DATA

= 150 MSPS,

No Interpolation

FREQUENCY – MHz

AMPLITUDE – dBm

0

–100

050 300100 150 200 250

–10

–60

–70

–80

–90

–20

–30

–50

–40

TPC 23. Single-Tone Spuri­ous Performance, f

OUT

=

10 MHz, f

DATA

= 80 MSPS,

Interpolation = 4

ⴛ

0

FREQUENCY – MHz

AMPLITUDE – dBm

–120

020 8040 60

–40

–60

–80

–100

–20

TPC 26. Eight-Tone IMD
Performance, f

DATA

=

160 MSPS, Interpolation = 8

ⴛ

FREQUENCY – MHz

AMPLIFIER – dBm

0

–100

050 300

100 150 200 250

–10

–60

–70

–80

–90

–20

–30

–50

–40

TPC 21. Single-Tone Spuri­ous Performance, f

OUT

=

10 MHz, f

DATA

= 150 MSPS,

Interpolation = 2

ⴛ

FREQUENCY – MHz

AMPLITUDE – dBm

0

–20

–100

05 2510 15 20

–40

–60

–80

–10

–30

–50

–70

–90

TPC 24. Two-Tone IMD Per­formance, f

OUT

= 10 MHz,

f

DATA

= 50 MSPS, Interpola-

tion = 8

ⴛ

(T = 25ⴗC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I

OUTFS

= 20 mA, Interpolation = 2ⴛ, Differential Coupled Transformer Output, 50 ⍀

Doubly Terminated, unless otherwise noted.)

REV. 0

AD9775

–13–

MODE CONTROL (VIA SPI PORT)

Table I. Mode Control via SPI Port

(Default Values Are Highlighted)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h SDIO LSB, MSB First Software Reset on Sleep Mode Power-Down Mode 1R/2R Mode PLL_LOCK

Bidirectional 0 = MSB Logic “1” Logic “1” shuts down Logic “1” shuts down DAC output current set Indicator
0 = Input 1 = LSB the DAC output all digital and analog by one or two external
1 = I/O currents. functions. resistors.

0 = 2R, 1 = 1R

01h Filter Filter Modulation Modulation Mode 0 = No Zero Stuffing 1 = Real Mix Mode 0 = e

–j␻

DATACLK/

Interpolation Interpolation Mode (None, f

S

/2, fS/4, fS/8) on Interpolation 0 = Complex 1 = e

+j␻

PLL_LOCK

Rate Rate (None, f

S

/2, Filters, Logic “1” Mix Mode Select

(1×, 2×, 4×, 8×)(1×, 2×, 4×, 8×)f

S

/4, fS/8) enables zero stuffing. 0 = PLLLOCK

1 = DATACLK

02h 0 = Signed Input 0 = Two Port Mode DATACLK Driver DATACLK Invert ONEPORTCLK Invert IQSEL Invert Q First

Data 1 = One Port Mode Strength 0 = No Invert 0 = No Invert 0 = No Invert 0 = I First
1 = Unsigned 1 = Invert 1 = Invert 1 = Invert 1 = Q First

03h PLL Divide PLL Divide

(Prescaler) Ratio (Prescaler) Ratio

04h 0 = PLL OFF 0 = Automatic PLL Charge Pump PLL Charge Pump PLL Charge Pump

1 = PLL ON Charge Pump Control Control Control Control

1 = Programmable

05h IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

06h IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain

Adjustment Adjustment Adjustment Adjustment

07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

08h IDAC I

OFFSET

IDAC Offset IDAC Offset

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

OFFSET

on

I

OUTB

09h QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

0Ah QDAC Coarse QDAC Coarse QDAC Coarse QDAC Coarse

Gain Adjustment Gain Adjustment Gain Adjustment Gain Adjustment

0Bh QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

0Ch QDAC I

OFFSET

QDAC Offset QDAC Offset

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

OFFSET

on I

OUTB

0Dh Version Register Version Register Version Register Version Register

REV. 0

AD9775

–14–

REGISTER DESCRIPTION
Address 00h

Bit 7 Logic “0” (default). Causes the SDIO pin to act as

an input during the data transfer (Phase 2) of the
communications cycle. When set to “1,” SDIO
can act as an input or output, depending on Bit 7 of
the instruction byte.

Bit 6 Logic “0” (default). Determines the direction

(LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the section
MSB/LSB Transfers for a detailed description.

Bit 5 Writing a “1” to this bit resets the registers to their

default values and restarts the chip. The RESET bit
always reads back “0.” Register Address 00h bits are
not cleared by this software reset. However, a high
level at the RESET pin forces all registers, including
those in Address 00h, to their default state.

Bit 4 Sleep Mode. A Logic “1” to this bit shuts down the

DAC output currents.

Bit 3 Power-Down. Logic “1” shuts down all analog and

digital functions except for the SPI port.

Bit 2 1R/2R Mode. The default (“0”) places the AD9775

in two resistor mode. In this mode, the I

REF

currents
for the I and Q DAC references are set separately by
the R

SET

resistors on FSADJ1 and FSADJ2 (Pins
59 and 60). In the 2R mode, assuming the coarse
gain setting is full scale and the fine gain setting is
zero, I

FULLSCALE1

= 32 × V

REF

/FSADJ1 and

I

FULLSCALE2

= 32 × V

REF

/FSADJ2. With this bit set
to “1,” the reference currents for both I and Q
DACs are controlled by a single resistor on Pin 60.
I

FULLSCALE

in one resistor mode for both of the I
and Q DACs is half of what it would be in the 2R
mode, assuming all other conditions (R

SET

, register
settings) remain unchanged. The full-scale current
of each DAC can still be set to 20 mA by choosing
a resistor of half the value of the R

SET

value used in

the 2R mode.

Bit 1 PLL_LOCK Indicator. When the PLL is enabled,

reading this bit will give the status of the PLL. A
Logic “1” indicates the PLL is locked. A Logic “0”
indicates an unlocked state.

Address 01h

Bits 7, 6 Filter interpolation rate according to the follow-

ing table:
00 1×

01 2×
10 4×
11 8×

Bits 5, 4 Modulation mode according to the following table:

00 none
01 f

S

/2

10 f

S

/4

11 f

S

/8

Bit 3 Logic “1” enables zero stuffing mode for interpo-

lation filters.

Bit 2 Default (“1”) enables the real mix mode. The I and

Q data channels are individually modulated by f

S

/2,

f

S

/4, or fS/8 after the interpolation filters. However, no
complex modulation is done. In the complex mix
mode (Logic “0”), the digital modulators on the I
and Q data channels are coupled to create a digi­tal complex modulator. When the AD9775 is
applied in conjunction with an external quadrature
modulator, rejection can be achieved of either the
higher or lower frequency image around the second
IF frequency (i.e., the second IF frequency is the
LO of the analog quadrature modulator external to
the AD9775) according to the bit value of Register
01h, Bit 1.

Bit 1 Logic “0” (default) causes the complex modulation

to be of the form e

–j␻t

, resulting in the rejection of
the higher frequency image when the AD9775 is used
with an external quadrature modulator. A Logic “1”
causes the modulation to be of the form e

+j␻t

, which

causes rejection of the lower frequency image.

Bit 0 In two port mode, a Logic “0” (default) causes Pin 8

to act as a lock indicator for the internal PLL. A
Logic “1” in this register causes Pin 8 to act as a
DATACLK, either generating or acting as an input
clock (see Register 02h, Bit 3) at the input data rate
of the AD9775.

Address 02h

Bit 7 Logic “0” (default) causes data to be accepted on

the inputs as two’s complement binary. Logic “1”
causes data to be accepted as straight binary.

Bit 6 Logic “0” (default) places the AD9775 in two port

mode. I and Q data enters the AD9775 via Ports 1
and 2, respectively. A Logic “1” places the AD9775
in one port mode in which interleaved I and Q data
is applied to Port 1. See the Pin Function Descrip­tions for DATACLK/PLL_LOCK, IQSEL, and
ONEPORTCLK for detailed information on how
to use these modes.

Bit 5 DATACLK Driver Strength. With the internal PLL

disabled, and this bit set to Logic “0,” it is recom­mended that DATACLK be buffered. When this bit
is set to Logic “1,” DATACLK acts as a stronger
driver capable of driving small capacitive loads.

Bit 4 Default Logic “0.” A value of “1” inverts DATACLK

at Pin 8.

Bit 2 Default Logic “0.” A value of 1 inverts

ONEPORTCLK at Pin 32.

Bit 1 The default of Logic “0” causes IQSEL = 1 to

direct input data to the I channel, while IQSEL = 0
directs input data to the Q channel. A Logic “1” in
this register inverts the sense of IQSEL.

Bit 0 The default of Logic “0” defines IQ pairing as IQ,

IQ...while programming a Logic “1” causes the pair
ordering to be QI, QI...

REV. 0

AD9775

–15–

Address 03h

Bits 1, 0 Setting this divide ratio to a higher number allows

the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output clocks
run substantially slower. The divider ratio is set
according to the following table:

00 ⫼1
01 ⫼2
10 ⫼4
11 ⫼8

Address 04h

Bit 7 Logic “0” (default) disables the internal PLL. Logic

“1” enables the PLL.

Bit 6 Logic “0” (default) sets the charge pump control to

automatic. In this mode, the charge pump bias
current is controlled by the divider ratio defined in
Address 03h, Bits 1 and 0. Logic “1” allows the
user to manually define the charge pump bias cur­rent using Address 04h, Bits 2, 1, and 0. Adjusting
the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.

Bits 0, 1, 2 With the charge pump control set to manual, these

bits define the charge pump bias current according
to the following table:

000 50 µA
001 100 µA
010 200 µA
011 400 µA
100 800 µA

Address 05h, 09h

Bits 7–0 These bits represent an 8-bit binary number (Bit 7

MSB) that defines the fine gain adjustment of the I
(05h) and Q (09h) DAC, according to the equation
given below.

Address 06h, 0Ah

Bits 3–0 These bits represent a 4-bit binary number (Bit 3 MSB)

that defines the coarse gain adjustment of the I (06h)
and Q (0Ah) DACs according to the equation below.

Address 07h, 0Bh

Bits 7–0

Address 08h, 0Ch

Bit 1, 0 The 10 bits from these two address pairs (07h, 08h

and 0Bh, 0Ch) represent a 10-bit binary number
that defines the offset adjustment of the I and Q
DACs according to the equation below (07h, 0Bh–Bit
7 MSB/08h, 0Ch–Bit 0 LSB)

Address 08h, 0Ch

Bit 7 This bit determines the direction of the offset of the

I (08h) and Q (0Ch) DACs. A Logic “0” will apply
a positive offset current to I

OUTA

, while a Logic “1”

will apply a positive offset current to I

OUTB

. The
magnitude of the offset current is defined by the
bits in Addresses 07h, 0Bh, 08h, and 0Ch accord­ing to the formulas given below.

I

I

COARSE

I

FINE DATA

I

I

COARSE

I

FINE

OUTA

REF REF

OUTB

REF REF

=

×











+











×































×































=

×











+











×














6

8

1

16

3

32 256

1024

24

2

6

8

1

16

3

32 256

14

–

–


















×



































=×











10242421

2

4

1024

14

14

––DATA

II

OFFSET

OFFSET REF

(1)

Equation 1 shows I

OUTA

and I

OUTB

as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R

mode, the current I

REF

is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a

scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.