Analog Devices AD9773EB, AD9773AST Datasheet

PRELIMINAR Y TECHNICAL D A T A

a

12-Bit, 160 MSPS

××

×/4

××

××

×/8

××

2

®

Dual TxDAC+

××

× Interpolating

××

D/A Converter

Preliminary Technical Data

FEATURES

01-19-01

12 bit Resolution, 160 MSPS Conversion Rate
Selectable 2×/4×/8× Interpolating Filter
Programmable Channel Gain and Offset Adjustment
Fs/2,4,8 Digital Quadrature Modulation Capability
Direct IF Transmission Mode for 70MHz+ IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance

- SFDR -69dBc @ 2-35MHz

-WCDMA ACPR -70dB @ IF=16.25 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input

-Differential/Single Ended

-Sine W ave or TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface

-2’s Complement/Straight Binary Data Coding

-Dual Port or Single Port Interleaved Data
Single +3.3V Supply Operation
Power Dissipation: <700 mW @ 3.3V
On-chip 1.2 V Reference, 80-Lead LQFP

PROGRAMABLE DUAL INTERPOLATION DAC

WITH IMAGE REJECTION/DIGITAL MODULATION

AD9773

APPLICATIONS

Communications:
Analog Quadrature Modulation Architectures
3G, Multi-Carrier GSM, TDMA, CDMA Systems
Multi-Level QAM Modulators, Instrumentation

PRODUCT DESCRIPTION

The AD9773 is the 12 bit member of the AD977x family of
pin-compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+s. The AD977x family features a serial
port interface (SPI) providing a high level of programmabil­ity thus allowing for enhanced system level options. These
options include: selectable 2×/4×/8× interpolation filters;
Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image
rejection; a direct IF mode; programmable channel gain
and offset control; programmable internal clock divider;
straight binary or two’s complement data interface; and a
single port or dual port data interface.

I AND Q

NO NINTE RLE AV ED

OR INTERLEAVED DATA

WRITE

SELECT

CLOCK OUT

HALF-B AND

I

LATCH

Q

LATCH

FILTER #1*

12

12

⫼2

⫼2

DATA

ASSEMBLER

12

12

MUX

CONTROL

SPI INTERFACE &

CONTROL REGISTERS

*Half-Band Filters also can be configured for "Zero-Stuffing Only"

HALF-B AND

22

22

FILTER #2*

⫼2

HALF-B AND

22

22

REV. PrA

BLOCK DIAGRAM

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

I DAC

COS

FILTER#3*

22

22

FILTER

BYPASS MUX

⫼2

PLL CLO CK MULTIP LIER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

+

-/+

SIN

/2,4,8

F

DAC

SIN

+/-

+

COS

(F

)

DAC

PRESCALER

PHASE DETEC

TOR & VCO

AND CLOCK DIVIDER

DAC MODE B YPASS MUX

IMAGE REJE CTION/DUAL

-

I DAC

GAIN

DAC

VREF

I/Q DAC

Q DAC

I

OUT

OFFSET

DAC

I OFFSET

REGISTERS

GAIN/OFFSET

I

OUT

DIFF.

REFCLK

1

AD9773

REV. PrA

PRELIMINAR Y TECHNICAL D A T A

PRODUCT DESCRIPTION (Continued)

The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simulta­neously enhancing the TxDAC+ family’s passband noise/
distortion performance. The independent channel gain and
offset registers allow the user to calibrate LO feedthrough
and sideband suppression errors associated with analog
quadrature modulators. The 6 dB of gain adjustment range
also can be used to control the output power level of each
DAC.

The AD9773 features the ability to perform Fs/4 and Fs/8
digital modulation and image rejection when combined
with an analog quadrature modulator. In this mode, the
AD9773 would accept I and Q complex data (representing a
single or multicarrier waveform), generate a quadrature
modulated IF signal along with its orthogonal representa­tion via its dual DACs, and present these two recon­structed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion
process. Another digital modulation mode (i.e. the Direct
IF Mode) allows the original baseband signal representa­tion to be frequency translated such that pairs of images
fall at multiples of 1/2 the DAC update rate.

The AD9773 family includes a flexible clock interface
accepting differential or single-ended sinewave or digital
logic inputs. An internal PLL clock multiplier is also
included to generate the necessary on-chip high frequency
clocks. It can also be disabled to allow the use of a higher
performance external clock source. An internal program­mable divider simplifies clock generation in the converter
when using an external clock source. A flexible data input
interface allows for straight binary or 2’s complement
formats as well as supports single port interleaved or dual
port data.

PRODUCT HIGHLIGHTS

1. The AD9773 is the 12 bit member of the AD977x family of
pin-compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+s.

2. Direct IF Transmission capability for 70MHz +IFs
through a novel digital mixing process

3. Fs/8 Digital Quadrature Modulation and user selectable
image rejection to simplify /remove cascaded SA W filter
stages

4. 2×/4×/8× User Selectable Interpolating Filter eases data
rate and output signal reconstruction filter requirements.

5. User selectable 2’s Complement/Straight Binary Data
Coding.

6. User programmable Channel Gain Control over 1 dB
range in 0.01dB increments

7. User programmable Channel Offset +/-10% over the FSR

8. Ultra high speed 400 MSPS DAC conversion rate.

9. Internal Clock Divider provides data rate clock for easy
interfacing.

10. Flexible Clock Input with Single Ended or Differential
Input, CMOS or 1V p-p LO Sinewave input capability .

11. Low Power: Complete CMOS DAC operates on <700
mW from a 3.0V to 3.6V single supply. The 20ma full-scale
current can be reduced for lower power operation, and a
several sleep functions are provided to reduce power
during idle periods.

12. On-chip V oltage Reference: The AD9773 includes a 1.20
V temperature-compensated bandgap voltage reference.

13. Small 80 lead LQFP

Dual high performance TxDAC+s provides a differential
current output programmable over a 0-20mA range. The
AD9773 is manufactured on an advanced 0.35 micron
CMOS process, operates from a single supply of 3.0V to 3.6
V and consumes <700 mW of power.

T argeted at wide dynamic range, Multi-Carrier and Multi­Standard systems, the superb baseband performance of the
AD9773 is ideal for Wideband-CDMA, Multi-Carrier
CDMA, Multi-Carrier TDMA, Multi-Carrier GSM and high
performance systems employing high order QAM modula­tion schemes. The image rejection feature simplifies and
can help to reduce the number of signal band filters needed
in an transmit signal chain. The direct IF mode helps to
eliminate a costly mixer stage for a variety of communica-

tions systems.

2

PRELIMINAR Y TECHNICAL D A TA

REV. PrA

AD9773–SPECIFICATIONS

DC SPECIFICATIONS (T

MIN

to T

, AVDD = +3.3 V, CLKVDD = +3.3 V, DVDD = +3.3 V, PLLVDD = +3.3v, I

MAX

OUTFS

= 20 mA,

unless otherwise noted)

PARAMETER MIN TYP MAX UNITS
RESOLUTION 12 bits

DC Accuracy

1

Integral Non-Linearity LSB
Differential Non_Linearity LSB
Monotonicity

ANALOG OUTPUT
Offset Error % of FSR

Gain Error (Without Internal Reference) % of FSR
Gain Error (With Internal Reference) % of FSR
Full-Scale Output Current

2

20 mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 200 kΩ
Output Capacitance 3 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

1µA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (REFLO = 3 V) 10 MΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift ppm of FSR/°C
Gain Drift (Without Internal Reference) ppm of FSR/°C
Gain Drift (With Internal Reference) ppm of FSR/°C
Reference Voltage Drift ppm/°C

POWER SUPPLY

AVDD
Voltage Range 3.0 3.3 3.6 V
Analog Supply Current (I
I

in SLEEP Mode mA

AV DD

)mA

AVDD

CLKVDD
Voltage Range 3.0 3.3 3.6 V
Clock Supply Current (I

)mA

CLKVDD

PLLVDD
Voltage Range 3.0 3.3 3.6 V
PLL Multiplier Supply Current (I

)mA

PLLVDD

DVDD
Voltage Range 3.0 3.3 3.6 V
Digital Supply Current (I

)mA

DVDD

Nominal Power Dissipation <700 mW
Power Supply Rejection Ratio – AVDD % of FSR/V
Power Supply Rejection Ratio – DVDD % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

Specifications subject to change without notice.

driving a virtual ground.

OUTA

OUTFS

, is 32× the I

current.

REF

3

PRELIMINAR Y TECHNICAL D A TA

REV. PrA

AD9773–SPECIFICATIONS

(T

to T

DYNAMIC SPECIFICATIONS

MIN

Differential Transformer Coupled Output, 50Ω Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units
DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f
Output Settling Time (t
Output Propagation Delay
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I

OUTFS

) (to 0.025%) ns

ST

1

(tPD) ns

2

2

= 20 mA) pA√Hz

) 400 MSPS

DAC

AC LINEARITY–BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

f

= MSPS; f

DATA

= MSPS; f

f

DATA

= MSPS; f

f

DATA

f

= MSPS; f

DATA

= MSPS; f

f

DATA

= MSPS; f

f

DATA

= MHz dBc

OUT

= MHz dBc

OUT

= MHz dBc

OUT

= MHz dBc

OUT

= MHz dBc

OUT

= MHz dBc

OUT

Two-Tone Intermodulation (IMD) to Nyquist (f

= MSPS; f

f

DATA

f

= MSPS; f

DATA

f

= MSPS; f

DATA

= MSPS; f

f

DATA

f

= MSPS; f

DATA

f

= MSPS; f

DATA

= MHz; f

OUT1

= MHz; f

OUT1

= MHz; f

OUT1

= MHz; f

OUT1

= MHz; f

OUT1

= MHz; f

OUT1

OUT2
OUT2
OUT2
OUT2
OUT2

= MHz dBc

OUT2

Total Harmonic Distortion (THD)

= MSPS; f

f

DATA

f

= MSPS; f

DATA

= MHz; 0 dBFS dB

OUT

= MHz; 0 dBFS dB

OUT

Signal-to-Noise Ratio (SNR)

= MSPS; f

f

DATA

= MSPS; f

f

DATA

= MHz; 0 dBFS dB

OUT

= MHz; 0 dBFS dB

OUT

Adjacent Channel Power Ratio (ACPR)

WCDMA with MHz BW, MHz Channel Spacing

IF = 16 MHz, f
IF = 32 MHz, f

= 65.536 MSPS dBc

DATA

= 131.072 MSPS dBc

DATA

Four-Tone Intermodulation

MHz, MHz, MHz and MHz at –12 dBFS dBFS

(f

= MSPS, Missing Center)

DATA

AC LINEARITY–IF MODE

Four-Tone Intermodulation at IF = MHz

MHz, MHz, MHz and MHz at dBFS dBFS

f

= MSPS, f

DATA

NOTES

1

Propagation delay is delay from CLK input to DAC update.

2

Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

= MHz

DAC

, AVDD = +3.3 V, CLKVDD = +3.3 V, DVDD = +3.3 V, PLLVDD = 0 V, I

MAX

ns
ns

= 0 dBFS)

OUT

= f

OUT1

= –6 dBFS)

OUT2

= MHz dBc
= MHz dBc
= MHz dBc
= MHz dBc
= MHz dBc

OUTFS

= 20 mA,

4

PRELIMINAR Y TECHNICAL D A TA

REV. PrA

AD9773–SPECIFICATIONS

(T

to T

DIGITAL SPECIFICATIONS

Parameter Min Typ Max Units
DIGITAL INPUTS

Logic “1” Voltage 2.1 3 V
Logic “0” Voltage 0 0.9 V
Logic “1” Current
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

PLL CLOCK ENABLED

Input Setup Time (tS) 0.2 ns
Input Hold Time (t
Latch Pulsewidth (t

PLL CLOCK DISABLED

Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
CLK/PLLLOCK Delay (tOD) TBD ns

1

) 1.8 ns

H

) 1.5 ns

LPW

) -1.2 ns

S

) 3.2 ns

H

) 1.5 ns

LPW

MIN

mA, unless otherwise noted)

, AVDD = +3.3 V, CLKVDD = +3.3 V, PLLVDD = +0 V, DVDD = +3.3 V, I

MAX

–10 +10 µA

OUTFS

= 20

Specifications subject to change without notice.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*
AD9773AST –40°C to +85°C 80-Lead LQFP ST-80

AD9773EB Evaluation Board

*ST = Thin Plastic Quad Flatpack.

5

PRELIMINAR Y TECHNICAL D A TA

REV. PrA

AD9773–SPECIFICATIONS

CLKVDD

LPF

CLKVDD

CLKCOM

CLK+

CLK-

CLKCOM

DATACLK/PLL_LOCK

DCOM

DVDD

P1B11(MSB)

P1B10

P1B9
P1B8
P1B7
P1B6

DVDD

DCOM

P1B5
P1B4

OUTA1IOUTB1

AVDD

ACOM

AVDD

ACOM

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

AVDD

AD9773+ TSP

ACOM

ACOM

I

ACOM

ACOM

OUTA2IOUTB2

I

ACOM

ACOM

AVDD

ACOM

AVDD

ACOM

AVDD

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

FSADJ1
FSADJ2
REFIO
RESET
SPI_CSB
SPI_CLK
SPI_SDIO
SPI_SDO
DCOM
DVDD
NC
NC
NC
NC
P2B0(LSB)
P2B1
DCOM
DVDD
P2B2
P2B3

P1B3

P1B2

P1B1

DCOM

NCNCNC

DVDD

NC

P2B9

P2B8

DCOM

DVDD

P2B7

P2B6

P2B5

P2B4

P1B0(LSB)

IQ SEL/P2B11(MSB)

ONEPORTCLK/P2B10

6