ANALOG DEVICES AD9773 Service Manual

12-Bit, 160 MSPS, 2×/4×/8× Interpolating

FEATURES

12-bit resolution, 160 MSPS/400 MSPS

input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment f

/2, fS/4, fS/8 digital quadrature modulation capability

S

Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI port Excellent ac performance

SFDR −69 dBc @ 2 MHz to 35 MHz

WCDMA ACPR −69 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input

Differential/single-ended sine wave or

TTL/CMOS/LVPECL compatible

FUNCTIONAL BLOCK DIAGRAM

Dual TxDAC D/A Converter

AD9773

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

WRITE

SELECT

AD9773

DATA

ASSEMBLER

12

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

LATCH

MUX

CONTROL

HALF-BAND FILTERS ALSO CAN BE

*

CONFIGURED FOR ZERO STUFFING ONLY

GAIN DAC

VREF

IDAC

I/Q DAC

GAIN/OFFSET

REGISTERS

DIFFERENTIAL CLK

OFFSET

DAC

I

OUT

IOFFSET

02857-001

COS

HALFBAND

FILTER1*

I

16

Q

/2

HALFBAND

FILTER2*

16

/2

HALFBAND

FILTER3*

161616

16

/2 /2

SIN

16

FILTER

BYPASS

MUX

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

Figure 1.

f

/2, 4, 8

DAC

SIN

COS

f

)

(

DAC

PRESCALER

PHASE DETECTOR

AND VCO

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9773

GENERAL DESCRIPTION

The AD97731 is the 12-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8× interpolating TxDAC+® family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; f with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a singleport or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

The AD9773 features the ability to perform f digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9773 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (for example, the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.

1

Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other

patents pending.

/2, fS/4, or fS/8 digital quadrature modulation

S

/2, fS/4, and fS/8

S

Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9773 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.

Targeted at a wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the AD9773 is ideal for wide band CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.

PRODUCT HIGHLIGHTS

1. The AD9773 is the 12-bit member of the AD977x pin

compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.

2. Direct IF transmission is possible for 70 MHz + IFs

through a novel digital mixing process.

/2, fS/4, and fS/8 digital quadrature modulation and user

3. f

S

selectable image rejection simplify/remove cascaded SAW filter stages.

4. A 2×/4×/8× user selectable interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User selectable twos complement/straight binary

data coding.

6. User programmable channel gain control over 1 dB range

in 0.01 dB increments.

7. User programmable channel offset control ±10% over

the FSR.

8. Ultrahigh speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for

easy interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W from a

3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions reduce power during idle periods.

12. On-chip voltage reference: The AD9773 includes a 1.20 V

temperature compensated band gap voltage reference.

13. 80-lead thin quad flat package, exposed pad (TQFP_EP).

Rev. D | Page 4 of 60

AD9773

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 12 Bits

DC Accuracy1

ANALOG OUTPUT (for IR and 2R Gain Setting Modes)

Offset Error −0.02 ±0.01 +0.02 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1.0 ±0.1 +1.0 % of FSR Full-Scale Output Current2 2 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V Reference Output Current

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C Gain Drift (With Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

AVDD

CLKVDD

CLKVDD (PLL ON)

DVDD

P

DIS

P

DIS

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V

OPERATING RANGE −40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

100 MSPS f

5

400 MSPS f

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

Integral Nonlinearity −1.5 ±0.4 +1.5 LSB Differential Nonlinearity −1 ±0.2 +1 LSB Monotonicity Guaranteed over specified temperature range

3

100 nA

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I I

in Sleep Mode 23.3 26 mA

AVDD

4

)

72.5 76 mA

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

Clock Supply Current (I

)4 8.5 10.0 mA

CLKVDD

) 23.5 mA

CLKVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

)4 34 41 mA

DVDD

Nominal Power Dissipation 380 410 mW

5

1.75 W

in PWDN 6.0 mW

driving a virtual ground.

OUTA

with f

DAC

OUT

, f

= 50 MSPS, fS/2 modulation, PLL enabled.

DAC

DATA

, is 32× the I

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

current.

REF

Rev. D | Page 5 of 60

AD9773

DYNAMIC SPECIFICATIONS

T

to T

MIN

transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f Output Settling Time (tST) (to 0.025%) 11 ns Output Rise Time (10% to 90%)1 0.8 ns Output Fall Time (10% to 90%)1 0.8 ns Output Noise (I

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Spurious-Free Dynamic Range Within a 1 MHz Window

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

1

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

) 400 MSPS

DAC

= 20 mA) 50 pA√Hz

OUTFS

= 0 dBFS)

OUT

f

= 100 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 0 dBFS, f

OUT

f

= 65 MSPS, f

DATA

f

= 65 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 160 MSPS, f

DATA

f

= 100 MSPS, f

DATA

f

= 78 MSPS, f

DATA

f

= 160 MSPS, f

DATA

= 1 MHz 70 84.5 dBc

OUT

= 1 MHz 83 dBc

OUT

= 15 MHz 79 dBc

OUT

= 1 MHz 83 dBc

OUT

= 15 MHz 77 dBc

OUT

= 1 MHz 75 dBc

OUT

= 15 MHz 77 dBc

OUT

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz; 0 dBFS −70 −82.4 dB

OUT

= 5 MHz; 0 dBFS 70 dB

OUT

= 5 MHz; 0 dBFS 69 dB

OUT

= 1 MHz 72 92.6 dBc

OUT

= f

OUT1

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, interpolation = 2×, differential

OUTFS

WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing

IF = Baseband, f IF = 19.2 MHz, f

21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f

201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f

= 76.8 MSPS 69 dBc

DATA

= 76.8 MSPS 69 dBc

DATA

= MSPS, Missing Center) 73 dBFS

DATA

= 160 MSPS, f

DATA

= 320 MHz) 69 dBFS

DAC

Rev. D | Page 6 of 60

AD9773

DIGITAL SPECIFICATIONS

T

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V

SERIAL CONTROL BUS

Maximum SCLK Frequency (f Minimum Clock Pulse Width High (t Minimum Clock Pulse Width Low (t

) 15 MHz

SLCK

) 30 ns

PWH

) 30 ns

PWL

Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (tDS) 25 ns Minimum Data Hold Time (tDH) 0 ns Maximum Data Valid Time (tDV) 30 ns RESET Pulse Width 1.5 ns Inputs (SDI, SDIO, SCLK, CSB)

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF

SDIO Output

Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA

= 20 mA, unless otherwise noted.

OUTFS

Rev. D | Page 7 of 60

AD9773

DIGITAL FILTER SPECIFICATIONS

20

Table 4. Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8 2, 42 0 3, 41 −29 4, 40 0 5, 39 67 6, 38 0 7, 37 −134 8, 36 0 9, 35 244 10, 34 0 11, 33 −414 12, 32 0 13, 31 673 14, 30 0 15, 29 −1079 16, 28 0 17, 27 1772 18, 26 0 19, 25 −3280 20, 24 0 21, 23 10,364 22 16,384

ATTENUATION (dBFS)

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

0

0.50 1.0 1.5 2.0

f

(NORMALIZED TO INPUT DATA RATE)

OUT

02857-002

Figure 2. 2× Interpolating Filter Response

20

0

Table 5. Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19 2, 18 0 3, 17 −120 4, 16 0 5, 15 438 6, 14 0 7, 13 −1288 8, 12 0 9, 11 5047 10 8192

Table 6. Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7 2, 10 0 3, 9 −53 4, 8 0 5, 7 302 6 512

ATTENUATION (dBFS)

–120

–20

–40

–60

–80

–100

–120

0.50 1.0 1.5 2.0

f

(NORMALIZED TO INPUT DATA RATE)

OUT

02857-003

Figure 3. 4× Interpolating Filter Response

20

0

2046

f

(NORMALIZED TO INPUT DATA RATE)

OUT

8

02857-004

Figure 4. 8× Interpolating Filter Response

Rev. D | Page 8 of 60

AD9773

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter With Respect To Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V I

, I

OUTA

P1B11 to P1B0, P2B11 to P2B0, RESET DGND −0.3 DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK− CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C

AGND −1.0 AVDD + 0.3 V

OUTB

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

80-lead thin quad flat package, exposed pad (TQFP_EP)

= 23.5°C/W (with thermal pad soldered to PCB)

θ

JA

ESD CAUTION

Rev. D | Page 9 of 60

AD9773

2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1

AVDD79AGND78AVDD77AGND76AVDD75AGND74AGND73I

80

72

OUTB1

I

AGND70AGND69I

71

OUTA

68

OUTB

I

67

AGND66AGND65AVDD64AGND63AVDD62AGND61AVDD

CLKVDD

LPF

CLKVDD

CLKGND

CLK+ CLK–

CLKGND

DATACLK/PLL_LOCK

DGND

DVDD

P1B11 (MSB)

P1B10

P1B9 P1B8 P1B7 P1B6

DGND

DVDD

P1B5 P1B4

NC = NO CONNECT

1

PIN 1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21

P1B322P1B223P1B1

24

25

26

DGND

AD9773

TxDAC+

TOP VIEW

(Not to Scale)

27NC28NC29NC30NC31

DVDD

32

33

35

36

37

P2B934P2B8

DVDD

DGND

P2B738P2B639P2B540P2B4

60

FSADJ1

59

FSADJ2

58

REFIO

57

RESET

56

SPI_CSB

55

SPI_CLK

54

SPI_SDIO

53

SPI_SDO

52

DGND

51

DVDD

50

NC

49

NC

48

NC

47

NC

46

P2B0 (LSB)

45

P2B1

44

DGND

43

DVDD

42

P2B2

41

P2B3

P1B0 (LSB)

IQSEL/P2B11 (MSB)

ONEPORTCLK/P2B10

02857-005

Figure 5. Pin Configuration

Rev. D | Page 10 of 60

AD9773

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK

9, 17, 25,

DGND Digital Common.

35, 44, 52 10, 18, 26,

DVDD Digital Supply Voltage.

36, 43, 51 11 to 16,

P1B11 (MSB) to P1B0 (LSB) Port 1 Data Inputs.

19 to 24, 27 to 30,

NC No Connect.

47 to 50 31 IQSEL/P2B11 (MSB)

32 ONEPORTCLK/P2B10

33, 34, 37 to

P2B9 to P2B0 (LSB) Port 2 Data Inputs.

42, 45, 46 53 SPI_SDO

54 SPI_SDIO

55 SPI_CLK

56 SPI_CSB

57 RESET

58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65,

AVDD Analog Supply Voltage.

76, 78, 80 62, 64, 66,

AGND Analog Common. 67, 70, 71, 74, 75, 77, 79

68, 69 I 72, 73 I

OUTB2

OUTB1

, I

Differential DAC Current Outputs, Q Channel.

OUTA2

, I

Differential DAC Current Outputs, I Channel.

OUTA1

With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin can also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate.

In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB.

With the PLL disabled and the AD9773 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9773 to accept and demux interleaved I and Q data to the I and Q input registers.

In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a high-Z state. This pin can also be used as an output for the data rate clock. For more information, see the

Two-Port Data Input Mode section.

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle.

Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h.

Rev. D | Page 11 of 60

AD9773

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I 50 Ω doubly terminated, unless otherwise noted.

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 65 130

FREQUENCY (MHz)

Figure 6. Single-Tone Spectrum @ f

90

= 65 MSPS with f

DATA

OUT

= f

DATA

/3

= 20 mA, interpolation = 2×, differential transformer-coupled output,

OUTFS

02857-006

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 10050 150

FREQUENCY (MHz)

Figure 9. Single-Tone Spectrum @ f

90

= 78 MSPS with f

DATA

OUT

= f

DATA

/3

02857-009

85

80

75

70

SFDR (dBc)

65

60

55

50

02010 30

–12dBFS

FREQUENCY (MHz)

Figure 7. In-Band SFDR vs. f

90

0dBFS

85

80

75

70

SFDR (dBc)

65

60

–6dBFS

–12dBFS

–6dBFS

0dBFS

OUT

@ f

= 65 MSPS

DATA

02857-007

85

80

75

70

SFDR (dBc)

65

60

55

50

–12dBFS

02010 30

Figure 10. In-Band SFDR vs. f

90

85

0dBFS

80

75

70

SFDR (dBc)

65

60

–6dBFS

–12dBFS

0dBFS

–6dBFS

FREQUENCY (MHz)

OUT

@ f

= 78 MSPS

DATA

02857-010

55

50

02010 30

FREQUENCY (MHz)

Figure 8. Out-of-Band SFDR vs. f

OUT

@ f

= 65 MSPS

DATA

02857-008

Rev. D | Page 12 of 60

55

50

02010 30

FREQUENCY (MHz)

Figure 11. Out-of-Band SFDR vs. f

OUT

@ f

= 78 MSPS

DATA

02857-011

AD9773

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 200100 300

FREQUENCY (MHz)

Figure 12. Single-Tone Spectrum @ f

90

85

–12dBFS

80

75

70

–6dBFS

SFDR (dBc)

65

60

55

50

01020304050

0dBFS

FREQUENCY (MHz)

Figure 13. In-Band SFDR vs. f

90

= 160 MSPS with f

DATA

@ f

OUT

= 160 MSPS

DATA

OUT

= f

DATA

02857-012

/3

02857-013

90

85

80

75

70

IMD (dBc)

65

60

55

50

02010 30

–3dBFS

0dBFS

FREQUENCY (MHz)

Figure 15. Third-Order IMD Products vs. f

90

85

80

75

70

IMD (dBc)

65

60

55

50

02010 30

–6dBFS

–3dBFS

FREQUENCY (MHz)

Figure 16. Third-Order IMD Products vs. f

90

–6dBFS

@ f

OUT

0dBFS

@ f

OUT

= 65 MSPS

DATA

= 78 MSPS

DATA

02857-015

02857-016

85

80

–6dBFS

75

70

SFDR (dBc)

65

60

–12dBFS

55

50

01020304050

Figure 14. Out-of-Band SFDR vs. f

0dBFS

FREQUENCY (MHz)

OUT

@ f

= 160 MSPS

DATA

IMD (dBc)

02857-014

Rev. D | Page 13 of 60

85

80

75

70

65

60

55

50

04020 60

–3dBFS

0dBFS

FREQUENCY (MHz)

Figure 17. Third-Order IMD Products vs. f

–6dBFS

@ f

OUT

= 160 MSPS

DATA

02857-017

AD9773

90

85

80

75

70

IMD (dBc)

65

90

8×

4×

1×

2×

–3dBFS –6dBFS

85

80

75

70

SFDR (dBc)

65

0dBFS

60

55

50

04020 60

FREQUENCY (MHz)

Figure 18. Third-Order IMD Products vs. f

= 160 MSPS, 2× f

1× f

DATA

90

85

80

75

70

IMD (dBc)

65

60

55

50

–15 –5–10 0

= 160 MSPS, 4× f

DATA

= 50 MSPS

8× f

DATA

4×

2×

(dBFS)

A

OUT

Figure 19. Third-Order IMD Products vs. A

= 50 MSPS for All Cases, 1× f

f

DATA

4× f

= 200 MSPS, 8× f

DAC

90

DAC

and Interpolation Rate,

OUT

DATA

8×

1×

and Interpolation Rate,

OUT

= 50 MSPS, 2× f

= 400 MSPS

DAC

= 80 MSPS,

= 100 MSPS,

DAC

02857-018

02857-019

60

55

50

3.23.1 3.3 3.4 3.5 AVDD (V)

Figure 21. Third-Order IMD Products vs. AVDD @ f

= 320 MSPS, f

f

DAC

90

85

80

75

70

SNR (dB)

65

60

55

50

0 10050 150

0 150

PLL OFF

PLL ON

INPUT DATA RATE (MSPS)

Figure 22. SNR vs. Data Rate for f

90

= 160 MSPS

DATA

OUT

= 5 MHz

= 10 MHz,

02857-021

02857-022

85

80

75

70

SFDR (dBc)

65

60

55

50

–12dBFS

–6dBFS

3.23.1 3.3 3.4 3.5 AVDD (V)

Figure 20. SFDR vs. AVDD @ f

= 320 MSPS, f

f

DAC

0dBFS

OUT

= 160 MSPS

DATA

= 10 MHz,

02857-020

85

80

f

= 65MSPS

DATA

75

70

SFDR (dBc)

65

60

55

50

–50 500 100

160MSPS

TEMPERATURE (

Figure 23. SFDR vs. Temperature @ f

°

C)

78MSPS

= f

OUT

DATA

/11

02857-023

Rev. D | Page 14 of 60

AD9773

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 10050

FREQUENCY (MHz)

Figure 24. Single-Tone Spurious Performance, f

= 150 MSPS, No Interpolation

f

DATA

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Figure 25. Two-Tone IMD Performance, f

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 50 100 150 200 250

1002030

FREQUENCY (MHz)

= 150 MSPS, No Interpolation

DATA

FREQUENCY (MHz)

Figure 26. Single-Tone Spurious Performance, f

f

= 150 MSPS, Interpolation = 2×

DATA

= 10 MHz,

OUT

= 10 MHz,

OUT

02857-024

40

02857-025

02857-026

0

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

Figure 27. Two-Tone IMD Performance, f

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 50 100 150 200 250

2015510025303

FREQUENCY (MHz)

= 150 MSPS, Interpolation = 4×

DATA

FREQUENCY (MHz)

Figure 28. Single-Tone Spurious Performance, f

= 80 MSPS, Interpolation = 4×

f

DATA

0

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

0 5 10 15 20 25

FREQUENCY (MHz)

Figure 29. Two-Tone IMD Performance, f

= 10 MHz, f

OUT

Interpolation = 8×

540

= 10 MHz,

OUT

= 50 MSPS,

DATA

02857-027

02857-028

02857-029

Rev. D | Page 15 of 60

AD9773

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 200100 300

FREQUENCY (MHz)

Figure 30. Single-Tone Spurious Performance, f

= 50 MSPS, Interpolation = 8×

f

DATA

= 10 MHz,

OUT

02857-030

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

04020 60

FREQUENCY (MHz)

Figure 31. Eight-Tone IMD Performance, f

DATA

Interpolation = 8×

= 160 MSPS,

02857-031

Rev. D | Page 16 of 60

AD9773

TERMINOLOGY

Adjacent Channel Power Ratio (ACPR)

A ratio, in dBc, between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Complex Modulation

The process of passing the real and imaginary components of a

jωt

signal through a complex modulator (transfer function = e

= cosωt + jsinωt) and realizing real and imaginary components on the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.

Group Delay

Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of f

(interpolation rate), a digital filter can be constructed with

DATA

a sharp transition band near f appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that would typically

DATA

Linearity Error

Also called integral nonlinearity (INL), linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of 0 is called offset error. For I are all 0s. For I

, 0 mA output is expected when the inputs

OUTA

, 0 mA output is expected when all inputs are

OUTB

set to 1.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Tem p er at u re Dr i ft

It is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

. For offset and gain

MAX

drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

Rev. D | Page 17 of 60

AD9773

MODE CONTROL (VIA SPI PORT)

Table 9. Mode Control via SPI Port

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h

SDIO Bidirectional 0 = Input 1 = I/O

01h

Filter Interpolation Rate (1×, 2×, 4×, 8×)

02h

0 = Signed Input Data

1 = Unsigned

03h

Data Rate

2

Output Clock

04h

0 = PLL OFF2

1 = PLL ON

05h

IDAC Fine Gain Adjustment

06h

07h

IDAC Offset Adjustment Bit 9

08h

IDAC I

OFFSET

Direction

09h

0 = I on I

1 = I on I

QDAC

OFFSET

OUTA

OFFSET

OUTB

Fine Gain Adjustment

1

LSB, MSB First 0 = MSB 1 = LSB

Software Reset on Logic 1

Sleep Mode Logic 1 Shuts Down the DAC Output

Power-Down Mode Logic 1 Shuts Down All Digital and Analog Func tions

1R/2R Mode DAC Output Current Set by One or Two External Resistors 0 = 2R, 1 = 1R

Currents

/2,

S

Modulation Mode (None, f f

S

/4, fS/8)

/2,

S

0 = No Zero Stuffing on Interpolation Filters, Logic 1

1 = Real Mix Mode

0 = Complex Mix Mode

Filter Interpolation Rate (1×, 2×, 4×, 8×)

Modulation Mode (None, f

/4, fS/8)

f

S

Enables Zero Stuffing

0 = Two-Port Mode

1 = One-Port Mode

DATACLK Driver Strength

DATACLK Invert

0 = No Invert

ONEPORTCLK Invert 0 = No Invert 1 = Invert

1 = Invert

0 = Automatic Charge Pump Control

PLL Charge Pump

Control 1 = Programmable

IDAC Fine Gain Adjustment

IDAC Offset Adjustment Bit 8

IDAC Fine Gain Adjustment

IDAC Offset Adjustment Bit 7

IDAC Fine Gain Adjustment

IDAC Offset Adjustment Bit 6

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 5

IDAC

Fine Gain

Adjustment

IDAC

Coarse Gain

Adjustment

IDAC Offset

Adjustment

Bit 4

QDAC Fine Gain Adjustment

QDAC

Fine Gain

Adjustment

PLL_LOCK Indicator

–jωt

+jωt

0 = e

1 = e

IQSEL Invert

0 = No Invert

1 = Invert PLL Divide

(Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 3

IDAC Offset Adjustment Bit 1

QDAC Fine Gain Adjustment

DATACLK/ PLL_LOCK Select

0 = PLLLOCK

1 = DATACLK

Q First 0 = I First 1 = Q First

PLL Divide (Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 2

IDAC Offset Adjustment Bit 0

QDAC Fine Gain Adjustment

2

Rev. D | Page 18 of 60

ANALOG DEVICES AD9773 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

DIGITAL FILTER SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

MODE CONTROL (VIA SPI PORT)