Analog Devices AD9772AAST Datasheet

14-Bit, 160 MSPS TxDAC+

®

a

FEATURES
Single 3.0 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
160 MSPS Input Data Rate

67.5 MHz Reconstruction Passband @ 160 MSPS
74 dBc SFDR @ 25 MHz
2 Interpolation Filter with High- or Low-Pass Response

73 dB Image Rejection with 0.005 dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF

Performance
Internal 2/4 Clock Multiplier
250 mW Power Dissipation; 13 mW with Power-Down

Mode
48-Lead LQFP Package

APPLICATIONS
Communication Transmit Channel

W-CDMA Base Stations, Multicarrier Base Stations,

Direct IF Synthesis, Wideband Cable Systems
Instrumentation

PRODUCT DESCRIPTION

The AD9772A is a single-supply, oversampling, 14-bit digital­to-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2⫻
digital interpolation filter and clock multiplier. The on-chip
PLL clock multiplier provides all the necessary clocks for the
digital filter and the 14-bit DAC. A flexible differential clock
input allows for a single-ended or differential clock driver for
optimum jitter performance.

For baseband applications, the 2⫻ digital interpolation filter
provides a low-pass response, hence providing up to a threefold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper in-band
image by more than 73 dB. For direct IF applications, the 2⫻
digital interpolation filter response can be reconfigured to select
the upper in-band image (i.e., high-pass response) while suppress­ing the original baseband image. To increase the signal level of
the higher IF images and their passband flatness in direct IF
applications, the AD9772A also features a “zero stuffing” option
in which the data following the 2⫻ interpolation filter is upsampled
by a factor of two by inserting midscale data samples.

The AD9772A can reconstruct full-scale waveforms with band­widths as high as 67.5 MHz while operating at an input data rate of
160 MSPS. The 14-bit DAC provides differential current outputs
to support differential or single-ended applications. A segmented

TxDAC+ is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

with 2 Interpolation Filter

AD9772A

FUNCTIONAL BLOCK DIAGRAM

DIV1

DIV0

PLL CLOCK

MULTIPLIER



14-BIT DAC

REFLO

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

CLK+

CLK–

DATA
INPUTS
(DB13...

DB0)

SLEEP

CLKCOM

CLKVDD MOD0 MOD1 RESET

AD9772A

CLOCK DISTRIBUTION

AND MODE SELECT

1

CONTROL

FILTER

2 FIR
INTER-

POLATION

FILTER

CONTROL

1/2

EDGE-

TRIGGERED

LATCHES

DCOM DVDD ACOM AVDD

PLLLOCK

MUX

2/4

ZERO

STUFF

MUX

+1.2V REFERENCE

AND CONTROL AMP

current source architecture is combined with a proprietary
switching technique to reduce spurious components and enhance
dynamic performance. Matching between the two current outputs
ensures enhanced dynamic performance in a differential output
configuration. The differential current outputs may be fed into a
transformer or a differential op amp topology to obtain a single­ended output voltage using an appropriate resistive load.

The on-chip bandgap reference and control amplifier are config­ured for maximum accuracy and flexibility. The AD9772A can
be driven by the on-chip reference or by a variety of external
reference voltages. The full-scale current of the AD9772A can
be adjusted over a 2 mA to 20 mA range, thus providing addi­tional gain ranging capabilities.

The AD9772A is available in a 48-lead LQFP package and
specified for operation over the industrial temperature range
of –40°C to +85°C.

PRODUCT HIGHLIGHTS

1. A flexible, low power 2⫻ interpolation filter supporting
reconstruction bandwidths of up to 67.5 MHz can be config­ured for a low- or high-pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.

2. A “zero-stuffing” option enhances direct IF applications.

3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.

4. The AD9772A digital interface, consisting of edge­triggered latches and a flexible differential or single-ended
clock input, can support input data rates up to 160 MSPS.

5. On-chip PLL clock multiplier generates all of the inter­nal high-speed clocks required by the interpolation filter
and DAC.

6. The current output(s) of the AD9772A can easily be config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD9772A–SPECIFICATIONS

DC SPECIFICATIONS

(T

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.)

OUTFS

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL) ±3.5 LSB
Differential Nonlinearity (DNL) ±2.0 LSB
Monotonicity (12-Bit) Guaranteed Over Specified Temperature Range

ANALOG OUTPUT

Offset Error –0.025 +0.025 % of FSR
Gain Error (Without Internal Reference) –2 ±0.5 +2 % of FSR
Gain Error (With Internal Reference) –5 ±1.5 +5 % of FSR
Full-Scale Output Current

2

20 mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 200 kΩ
Output Capacitance 3 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

1 µA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (REFLO = 3 V) 10 mΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

AVDD

Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I
Analog Supply Current in SLEEP Mode (I

)3437mA

AVDD

) 4.3 6 mA

AVDD

DVDD1, DVDD2

Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I

CLKVDD, PLLVDD

4

(PLLVDD = 3.0 V)

DVDD1

+ I

)3740mA

DVDD2

Voltage Range 3.1 3.3 3.5 V
Clock Supply Current (I

CLKVDD

+ I

)2530mA

PLLVDD

CLKVDD (PLLVDD = 0 V)

Voltage Range 3.1 3.3 3.5 V

Clock Supply Current (I
Nominal Power Dissipation
Power Supply Rejection Ratio (PSRR)

) 6.0 mA

CLKVDD

5

6

– AVDD –0.6 +0.6 % of FSR/V

253 272 mW

Power Supply Rejection Ratio (PSRR)6 – DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

Measured at f

5

Measured with PLL enabled at f

6

Measured over a 3.0 V to 3.6 V range.

Specifications subject to change without notice.

driving a virtual ground.

OUTA

= 100 MSPS and f

DATA

OUTFS

DATA

, is 32⫻ the I

OUT

= 50 MSPS and f

current.

REF

= 1 MHz, DIV1, DIV0 = 0 V.

OUT

= 1 MHz.

–2–

REV. A

AD9772A

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

differential transformer coupled output, 50  doubly terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f
Output Settling Time (t
Output Propagation Delay
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I

OUTFS

) (to 0.025%) 11 ns

ST

1

(tPD)17ns

2

2

= 20 mA) 50 pA√Hz

) 400 MSPS

DAC

0.8 ns

0.8 ns

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

f

= 65 MSPS; f

DATA

= 65 MSPS; f

f

DATA

= 65 MSPS; f

f

DATA

f

= 160 MSPS; f

DATA

= 160 MSPS; f

f

DATA

f

= 160 MSPS; f

DATA

Two-Tone Intermodulation (IMD) to Nyquist (f

= 65 MSPS; f

f

DATA

f

= 65 MSPS; f

DATA

f

= 65 MSPS; f

DATA

= 160 MSPS; f

f

DATA

f

= 160 MSPS; f

DATA

f

= 160 MSPS; f

DATA

= 1.01 MHz 82 dBc

OUT

= 10.01 MHz 75 dBc

OUT

= 25.01 MHz 73 dBc

OUT

= 5.02 MHz 82 dBc

OUT

= 20.02 MHz 75 dBc

OUT

= 50.02 MHz 65 dBc

OUT

= 5.01 MHz; f

OUT1

= 15.01 MHz; f

OUT1

= 24.1 MHz; f

OUT1

= 10.02 MHz; f

OUT1

= 30.02 MHz; f

OUT1

= 48.2 MHz; f

OUT1

OUT1

= 6.01 MHz 85 dBc

OUT2

= 17.51 MHz 75 dBc

OUT2

= 26.2 MHz 68 dBc

OUT2

= 12.02 MHz 85 dBc

OUT2

= 35.02 MHz 70 dBc

OUT2

= 52.4 MHz 65 dBc

OUT2

= 0 dBFS)

OUT

= f

OUT2

= –6 dBFS)

Total Harmonic Distortion (THD)

= 65 MSPS; f

f

DATA

f

= 78 MSPS; f

DATA

= 1.0 MHz; 0 dBFS –80 dB

OUT

= 10.01 MHz; 0 dBFS –74 dB

OUT

Signal-to-Noise Ratio (SNR)

= 65 MSPS; f

f

DATA

= 100 MSPS; f

f

DATA

= 16.26 MHz; 0 dBFS 71 dB

OUT

= 25.1 MHz; 0 dBFS 71 dB

OUT

Adjacent Channel Power Ratio (ACPR)

WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing

IF = 16 MHz, f
IF = 32 MHz, f

= 65.536 MSPS 78 dBc

DATA

= 131.072 MSPS 68 dBc

DATA

Four-Tone Intermodulation

15.6 MHz, 15.8 MHz, 16.2 MHz and 16.4 MHz at –12 dBFS 88 dBFS
f

= 65 MSPS, Missing Center

DATA

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 70 MHz

68.1 MHz, 69.3 MHz, 71.2 MHz and 72.0 MHz at –20 dBFS 77 dBFS
f

= 52 MSPS, f

DATA

NOTES

1

Propagation delay is delay from CLK input to DAC update.

2

Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

= 208 MHz

DAC

OUTFS

= 20 mA,

REV. A

–3–

AD9772A–SPECIFICATIONS

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL SPECIFICATIONS

MIN

otherwise noted.)

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic “1” Voltage 2.1 3 V
Logic “0” Voltage 0 0.9 V
Logic “1” Current

*

–10 +10 µA

Logic “0” Current –10 +10 µA
Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

PLL CLOCK ENABLED—FIGURE 1a

Input Setup Time (tS), TA = 25°C 0.5 ns
Input Hold Time (t
Latch Pulsewidth (t

), TA = 25°C 1.0 ns

H

), TA = 25°C 1.5 ns

LPW

PLL CLOCK DISABLED—FIGURE 1b

Input Setup Time (tS), TA = 25°C –1.2 ns
Input Hold Time (t
Latch Pulsewidth (t
CLK/PLLLOCK Delay (t
PLLLOCK (V

), TA = 25°C 3.2 ns

H

), TA = 25°C 1.5 ns

LPW

), TA = 25°C 3.0 V

OH

), TA = 25°C 2.8 3.2 ns

OD

PLLLOCK (VOL), TA = 25°C 0.3 V

*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 µA.

Specifications subject to change without notice.

= 20 mA, unless

OUTFS

DB0–DB13

t

H

S

t

LPW

t

PD

t

ST

0.025%

0.025%

CLK+ – CLK–

IOUTA

OR

IOUTB

t

Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled

DB0–DB13

t

H

t

OD

t

LPW

t

PD

t

ST

0.025%

0.025%

PLLLOCK

CLK+ – CLK–

IOUTA

OR

IOUTB

t

S

Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled

–4–

REV. A

AD9772A

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL FILTER SPECIFICATIONS

MIN

differential transformer coupled output, 50  doubly terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

MAXIMUM INPUT DATA RATE (f

) 150 MSPS

DATA

DIGITAL FILTER CHARACTERISTICS

Passband Width1: 0.005 dB 0.401 f
Passband Width: 0.01 dB 0.404 f
Passband Width: 0.1 dB 0.422 f
Passband Width: –3 dB 0.479 f

LINEAR PHASE (FIR IMPLEMENTATION)

STOPBAND REJECTION

0.606 f

GROUP DELAY

CLOCK

to 1.394 f

2

CLOCK

73 dB

21 Input Clocks

IMPULSE RESPONSE DURATION

–40 dB 36 Input Clocks
–60 dB 42 Input Clocks

NOTES

1

Excludes sin(x)/x characteristic of DAC.

2

Defined as the number of data clock cycles between impulse input and peak of output response.

Specifications subject to change without notice.

= 20 mA,

OUTFS

OUT/fDATA

OUT/fDATA

OUT/fDATA

OUT/fDATA

0

–20

–40

–60

–80

OUTPUT – dB

–100

–120

–140

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

FREQUENCY – DC TO f

DATA

10.1

Figure 2a. FIR Filter Frequency Response—Baseband Mode

1

0.8

0.6

0.4

0.2

Table I. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)

Lower Upper Integer
Coefficient Coefficient Value

H(1) H(43) 10
H(2) H(42) 0
H(3) H(41) –31
H(4) H(40) 0
H(5) H(39) 69
H(6) H(38) 0
H(7) H(37) –138
H(8) H(36) 0
H(9) H(35) 248
H(10) H(34) 0
H(11) H(33) –419
H(12) H(32) 0
H(13) H(31) 678
H(14) H(30) 0
H(15) H(29) –1083
H(16) H(28) 0
H(17) H(27) 1776
H(18) H(26) 0
H(19) H(25) –3282
H(20) H(24) 0
H(21) H(23) 10364
H(22) 16384

NORMALIZED OUTPUT

0

–0.2

–0.4

0

10 15 20 25 30 35 40 45

5

TIME – Samples

Figure 2b. FIR Filter Impulse Response—Baseband Mode

REV. A

–5–

AD9772A

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect to Min Max Unit

AVDD, DVDD1-2, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM –0.3 +4.0 V
AVDD, DVDD1-2, CLKVDD, PLLVDD AVDD, DVDD1-2, CLKVDD, PLLVDD –4.0 +4.0 V
ACOM, DCOM1-2, CLKCOM, PLLCOM ACOM, DCOM1-2, CLKCOM, PLLCOM –0.3 +0.3 V
REFIO, REFLO, FSADJ, SLEEP ACOM –0.3 AVDD + 0.3 V

, I

I

OUTA

OUTB

DB0–DB13, MOD0, MOD1, PLLLOCK DCOM1-2 –0.3 DVDD + 0.3 V
CLK+, CLK– CLKCOM –0.3 CLKVDD + 0.3 V
DIV0, DIV1, RESET CLKCOM –0.3 CLKVDD + 0.3 V
LPF PLLCOM –0.3 PLLVDD + 0.3 V
Junction Temperature 125 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) 300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.

ACOM –1.0 AVDD + 0.3 V

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9772AAST –40°C to +85°C 48-Lead LQFP ST-48

THERMAL CHARACTERISTIC
Thermal Resistance

48-Lead LQFP

= 91°C/W

θ

JA

θ

= 28°C/W

JC

AD9772EB Evaluation Board

*ST = Thin Plastic Quad Flatpack.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9772A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. A

PIN CONFIGURATION

AD9772A

AVDD

AVDD

AD9772A

(Not to Scale)

DB1

(LSB) DB0

OUTAIOUTB

ACOM

I

TOP VIEW

MOD0

MOD1

DCOM

ACOM

FSADJ

DVDD

DCOM

REFIO

REFLO

NC

DVDD

ACOM

NC

36

SLEEP

35

LPF

34

PLLVDD

33

PLLCOM

32

CLKVDD

31

CLKCOM

30

CLK–

29

CLK+

28

DIV0

27

DIV1

26

RESET

25

PLLLOCK

1

DCOM

2

DCOM

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

3

4

5

6

7

8

9

10

11

12

(MSB) DB13

NC = NO CONNECT

DVDD

DVDD

48 47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

13 14 15 16 17 18 19 20 21 22 23 24

DB3

DB2

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1, 2, 19, 20 DCOM Digital Common
3 DB13 Most Significant Data Bit (MSB)
4–15 DB12–DB1 Data Bits 1–12
16 DB0 Least Significant Data Bit (LSB)
17 MOD0 Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High.
18 MOD1 Invokes “Zero-Stuffing” Mode. Active High. Note, “quarter-wave” digital mixing occurs with MOD0

also set HIGH.
23, 24 NC No Connect, Leave Open
21, 22, 47, 48 DVDD Digital Supply Voltage (2.8 V to 3.2 V)
25 PLLLOCK Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is locked to

input clock. Provides 1× clock output when PLL clock multiplier is disabled. Maximum fanout is one

(i.e., <10 pF).
26 RESET Resets internal divider by bringing momentarily high when PLL is disabled to synchronize internal

1× clock to the input data and/or multiple AD9772A devices.
27, 28 DIV1, DIV0 DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III.)
29 CLK+ Noninverting Input to Differential Cock. Bias to midsupply (i.e., CLKVDD/2).
30 CLK– Inverting Input to Differential Clock. Bias to midsupply (i.e., CLKVDD/2).
31 CLKCOM Clock Input Common
32 CLKVDD Clock Input Supply Voltage (2.8 V to 3.2 V)
33 PLLCOM Phase Lock Loop Common
34 PLLVDD Phase Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable PLL clock multiplier, connect

PLLVDD to PLLCOM.
35 LPF PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is

less than 10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated on

the evaluation board schematic.
36 SLEEP Power-Down Control Input. Active High. Connect to ACOM if not used.
37, 41, 44 ACOM Analog Common
38 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
39 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO

to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to

ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.
40 FSADJ Full-Scale Current Output Adjust
42 I
43 I

OUTB

OUTA

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.
45, 46 AVDD Analog Supply Voltage (2.8 V to 3.2 V)

REV. A

–7–

AD9772A

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).

Signal-to-Noise Ratio (SNR)

S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

Passband

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Stopband Rejection

The amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current.

Impulse Response

Response of the device to an impulse applied to the input.

Adjacent Channel Power Ratio (or ACPR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

FROM HP8644A
SIGNAL GENERATOR

AWG2021

OR

DG2020

EXT.

CLOCK

1k

1k

DIGITAL

DATA

CLKVDD

CLKCOM

CLK+

CLK–

SLEEP

3.3V

1

EDGE-

TRIGGERED

LATCHES

AD9772A

1/2

INTERPOLATION

CH1

CH2

MOD0

CLOCK DISTRIBUTION

AND MODE SELECT

FILTER
CONTROL

2 FIR

FILTER

CONTROL

3.3V3.3V

HP8130

PULSE GENERATOR

EXT. INPUT

MOD1

RESET

PLLLOCK

MUX

2/4

ZERO

STUFF

MUX

+1.2V REFERENCE

AND CONTROL AMP

REFLOAVDDACOMDVDDDCOM

DIV0

PLLCLOCK

MULTIPLIER

14-BIT DAC

Figure 3. Basic AC Characterization Test Setup

–8–

DIV1

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

0.1F

1.91k

50

MINI-CIRCUITS

T1–1T

100

20pF

TO FSEA30
SPECTRUM
ANALYZER

20pF50

REV. A

AD9772A

Typical AC Characterization Curves

90

0

–20

–40

–60

AMPLITUDE – dBm

–80

–100

IN-BAND

OUT-OF-

BAND

40 60 80 100

f

– MHz

OUT

120200

TPC 1. Single-Tone Spectral Plot @
f

= 65 MSPS with f

DATA

0

IN-BAND

–20

–40

–60

AMPLITUDE – dBm

–80

–100

OUT-OF-

BAND

50 100

FREQUENCY – MHz

OUT

= f

DATA

/3

TPC 4. Single-Tone Spectral Plot @
f

= 78 MSPS with f

DATA

OUT

= f

DATA

/3

1500

85

80

75

70

SFDR – dBc

65

60

55

50

TPC 2. In-Band SFDR vs. f
@ f

90

85

80

75

70

SFDR – dBc

65

60

55

50

TPC 5. In-Band SFDR vs. f
@ f

(AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
PLL Disabled.)

0dBFS

–12dBFS

= 65 MSPS

DATA

–6dBFS

–12dBFS

= 78 MSPS

DATA

–6dBFS

0dBFS

f

f

OUT

OUT

– MHz

20 25105

– MHz

OUT

30150

OUT

301502025105

35

70

65

60

0dBFS

55

50

SFDR – dBc

45

40

35

30

–12dBFS

TPC 3. Out-of-Band SFDR vs.
f

@ f

70

65

60

55

50

45

AMPLITUDE – dBm

40

35

30

OUT

DATA

0dBFS

0

5 101520253035

TPC 6. Out-of-Band SFDR vs.
f

@ f

OUT

DATA

OUTFS

–6dBFS

f

– MHz

OUT

= 65 MSPS

–6dBFS

–12dBFS

f

– MHz

OUT

= 78 MSPS

= 20 mA,

20 25105

30150

0

–20

–40

–60

AMPLITUDE – dBm

–80

–100

IN-BAND

OUT-OF-

BAND

100 150 200 250

FREQUENCY – MHz

TPC 7. Single-Tone Spectral Plot
@ f

= 160 MSPS with f

DATA

OUT

= f

REV. A

300500

DATA

/3

90

85

80

75

70

65

AMPLITUDE – dBm

60

55

50

0dBFS

–6dBFS

–12dBFS

0

10 20 30 40 50 60

f

– MHz

OUT

TPC 8. In-Band SFDR vs. f
@ f

= 160 MSPS

DATA

–9–

OUT

70

65

60

55

–6dBFS

50

45

AMPLITUDE – dBm

40

–12dBFS

35

30

0

10 20 30 40 50 60 70

0dBFS

f

– MHz

OUT

TPC 9. Out-of-Band SFDR vs.
f

OUT

@ f

= 160 MSPS

DATA

AD9772A

90

85

80

75

70

IMD – dBc

65

60

55

50

–3dBFS

0dBFS

0

51015202530

f

– MHz

OUT

–6dBFS

TPC 10. Third Order IMD Products
vs. f

IMD – dBc

@ f

OUT

90

85

f

DATA

80

75

70

65

60

–20

DATA

= 65MSPS

–15

= 65 MSPS

f

= 160MSPS

DATA

f

= 78MSPS

DATA

–10 –50

A

– dBFS

OUT

TPC 13. Third Order IMD Products
vs. A

OUT

@ f

OUT

= f

DAC

/11

90

85

80

75

70

IMD – dBc

65

60

55

50

0dBFS

0

5 1015202530

f

OUT

–6dBFS

–3dBFS

– MHz

TPC 11. Third Order IMD Products
vs. f

IMD – dBc

90

85

80

75

70

65

60

55

50

OUT

–20

@ f

f

DATA

DATA

–15

= 160MSPS

= 78 MSPS

f

= 78MSPS

DATA

f

= 65MSPS

DATA

–10 –50

A

– dBFS

OUT

TPC 14. Third Order IMD Products
vs. A

OUT

@ f

OUT

= f

DAC

/5

90

f

OUT

–6dBFS

–3dBFS

0dBFS

– MHz

85

80

75

70

IMD – dBc

65

60

55

35

50

0

10 20 30 40 50 60 70

TPC 12. Third Order IMD Products

90

85

80

75

70

SFDR – dBc

65

60

55

50

OUT

@ f

vs. f

TPC 15. SFDR vs. AVDD @ f
10 MHz, f

= 160 MSPS

DATA

–3dBFS

0dBFS

3.1 3.2 3.4 3.5
AVDD – Volts

= 320 MSPS

DAC

–6dBFS

OUT

3.63.33.0

=

90

85

80

75

70

IMD – dBc

65

60

55

50

0dBFS

3.1 3.2 3.4 3.5
AVDD – Volts

–3dBFS

–6dBFS

TPC 16. Third Order IMD Products
vs. AVDD @ f

= 10 MHz, f

OUT

DAC

=

320 MSPS

3.63.33.0

TPC 17. SNR vs. f

90

85

SNR – dBc

80

75

70

65

60

55

50

PLL OFF

PLL ON, OPTIMUM DIV0/1 SETTINGS

25

75

f

DAC

DAC

–10–

125 175

– MHz

@ f

OUT

= 10 MHz

90

f

DATA

= 65MSPS

SFDR – dBc

55

50

85

80

75

70

65

60

–40

f

= 78MSPS

DATA

TEMPERATURE – C

f

DATA

080–20

= 160MSPS

20 40 60

TPC 18. In-Band SFDR vs. Tempera­ture @ f

OUT

= f

DATA

/11

REV. A