ANALOG DEVICES AD9772A Service Manual

14-Bit, 160 MSPS TxDAC+

FEATURES

Single 3.1 V to 3.5 V supply
14-bit DAC resolution and input data width
160 MSPS input data rate

67.5 MHz reconstruction pass band @ 160 MSPS
74 dBc SFDR @ 25 MHz
2× interpolation filter with high- or low-pass response

73 dB image rejection with 0.005 dB pass-band ripple

Zero-stuffing option for enhanced direct IF performance
Internal 2×/4× clock multiplier
250 mW power dissipation; 13 mW with power-down mode
48-lead LQFP package

APPLICATIONS

Communication transmit channel

W-CDMA base stations, multicarrier base stations,

direct IF synthesis, wideband cable systems
Instrumentation

GENERAL DESCRIPTION

The AD9772A is a single-supply, oversampling, 14-bit digital­to-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2×
digital interpolation filter and clock multiplier. The on-chip PLL
clock multiplier provides all the necessary clocks for the digital
filter and the 14-bit DAC. A flexible differential clock input
allows for a single-ended or differential clock driver for
optimum jitter performance.

For baseband applications, the 2× digital interpolation filter
provides a low-pass response, thus providing as much as a
threefold reduction in the complexity of the analog reconstruc­tion filter. It does so by multiplying the input data rate by a
factor of 2 while suppressing the original upper in-band image
by more than 73 dB. For direct IF applications, the 2× digital
interpolation filter response can be reconfigured to select the
upper in-band image (that is, the high-pass response) while
suppressing the original baseband image. To increase the signal
level of the higher IF images and their pass-band flatness in
direct IF applications, the AD9772A also features a zero-stuffing
option in which the data following the 2× interpolation filter is
upsampled by a factor of 2 by inserting midscale data samples.

with 2× Interpolation Filter

AD9772A

FUNCTIONAL BLOCK DIAGRAM

CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0

CLK+

CLK–

DATA

INPUTS

(DB13 TO

DB0)

SLEEP

AD9772A

1×

EDGE-

TRIGGERED

LATCHES

DCOM DVDD ACOM AVDD REFLO

CLOCK DISTRI BUTION

AND MODE SELE CT

FILTER

1×/2× 2×/4×

CONTROL

2× FIR

INTER-

POLATION

FILTER

CONTROL

Figure 1.

MUX

ZERO­STUFF

MUX

1.2V REF ERENCE

AND CONTROL AMP

The AD9772A can reconstruct full-scale waveforms with band­widths of up to 67.5 MHz while operating at an input data rate
of 160 MSPS. The 14-bit DAC provides differential current
outputs to support differential or single-ended applications.

A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current
outputs can be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an
appropriate resistive load.

The on-chip band gap reference and control amplifier are con­figured for maximum accuracy and flexibility. The AD9772A
can be driven by the on-chip reference or by a variety of
external reference voltages. The full-scale current of the
AD9772A can be adjusted over a 2 mA to 20 mA range, thus
providing additional gain-ranging capabilities.

The AD9772A is available in a 48-lead LQFP package and is
specified for operation over the industrial temperature range of
–40°C to +85°C.

DIV1

PLL CLOCK
MULTIPLIER

14-BIT DAC

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

2253-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD9772A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Product Highlights........................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Dynamic Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Digital Filter Specifications ......................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Te r mi n ol o g y ....................................................................................12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 17

Functional Description .............................................................. 17

Digital Modes of Operation ...................................................... 17

PLL Clock Multiplier Operation .............................................. 19

Synchronization of Clock/Data

Using Reset with PLL Disabled................................................. 21

DAC Operation ........................................................................... 22

REVISION HISTORY

2/08—Rev. B to Rev. C

Changes to DVDD Parameter......................................................... 4

Changes to PLL Clock Enabled Parameter ................................... 7

Changes to PLL Clock Disabled Parameter.................................. 7

Changes to Table 8.......................................................................... 10

Changes to Functional Description .............................................17

Change to Power Dissipation Section.......................................... 25

Changes to Power and Grounding Considerations Section ..... 27

Change to Figure 53 ....................................................................... 29

Change to Direct IF Section.......................................................... 30

Changes to Figure 61...................................................................... 34

Updated Outline Dimensions....................................................... 38

Changes to Ordering Guide.......................................................... 38

6/03—Rev. A to Rev. B

Change to Features .......................................................................... 1

Change to DC Specifications .......................................................... 2

DAC Transfer Function ............................................................. 22

Reference Operation .................................................................. 22

Reference Control Amplifier .................................................... 23

Analog Outputs .......................................................................... 23

Digital Inputs/Outputs .............................................................. 24

Sleep Mode Operation ............................................................... 25

Power Dissipation....................................................................... 25

Applying the AD9772A ................................................................. 26

Output Configurations.............................................................. 26

Differential Coupling Using a Transformer ............................... 26

Differential Coupling Using an Op Amp................................ 26

Single-Ended, Unbuffered Voltage Output............................. 26

Single-Ended, Buffered Voltage Output.................................. 27

Power and Grounding Considerations.................................... 27

Applications Information.............................................................. 29

Multicarrier ................................................................................. 29

Baseband Single-Carrier Applications .................................... 30

Direct IF....................................................................................... 30

AD9772A Evaluation Board ......................................................... 32

Schematics................................................................................... 33

Evaluation Board Layout ........................................................... 35

Outline Dimensions ....................................................................... 38

Ordering Guide .......................................................................... 38

Change to Digital Filter Specifications...........................................5

Ordering Guide Updated .................................................................6

Change to Pin Function Descriptions ............................................7

Change to Figure 13a and Figure 13b.......................................... 15

Change to Digital Inputs/Outputs................................................ 18

Change to Sleep Mode Operation................................................ 19

Change to Figure 22....................................................................... 19

Change to Figure 23....................................................................... 19

Change to Power and Ground Considerations .......................... 21

Change to Figure 29....................................................................... 21

Update to Outline Dimensions..................................................... 30

3/02—Rev. 0 to Rev. A

Edits to Digital Specifications..........................................................4

Edits to Absolute Maximum Ratings..............................................6

Change to TPC 11 .......................................................................... 10

Change to Figure 9 Caption.......................................................... 14

Change to Figure 13a and Figure 13b.......................................... 15

Rev. C | Page 2 of 40

AD9772A

PRODUCT HIGHLIGHTS

1. A flexible, low power 2× interpolation filter supporting

reconstruction bandwidths of up to 67.5 MHz can be
configured for a low- or high-pass response with 73 dB
of image rejection for traditional baseband or direct IF
applications.

2. A zero-stuffing option enhances direct IF applications.

3. A low glitch, fast settling 14-bit DAC provides exceptional

dynamic range for both baseband and direct IF waveform
reconstruction applications.

4. The AD9772A digital interface, consisting of edge-triggered

latches and a flexible differential or single-ended clock input,
can support input data rates up to 160 MSPS.

5. An on-chip PLL clock multiplier generates all of the

internal high speed clocks required by the interpolation
filter and DAC.

6. The current output(s) of the AD9772A can easily be

configured for various single-ended or differential circuit
topologies.

Rev. C | Page 3 of 40

AD9772A

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits
DC ACCURACY

Integral Linearity Error (INL) ±3.5 LSB

Differential Nonlinearity (DNL) ±2.0 LSB

Monotonicity (12-Bit) Guaranteed over specified temperature range
ANALOG OUTPUT

Offset Error −0.025 +0.025 % of FSR

Gain Error

Full-Scale Output Current

Output Compliance Range −1.0 +1.25 V

Output Resistance 200 kΩ

Output Capacitance 3 pF
REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V

Reference Output Current
REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance (REFLO = 3 V) 10 MΩ

Small-Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS

Unipolar Offset Drift 0 ppm of FSR/°C

Gain Drift

Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY

AVDD

DVDD

CLKVDD, PLLVDD4 (PLLVDD = 3.3 V)

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

1

= 20 mA, unless otherwise noted.

OUTFS

Without Internal Reference −2 ±0.5 +2 % of FSR
With Internal Reference −5 ±1.5 +5 % of FSR

2

3

20 mA

1 A

Without Internal Reference ±50 ppm of FSR/°C
With Internal Reference ±100 ppm of FSR/°C

Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I
Analog Supply Current in Sleep Mode (I

) 34 37 mA

AVDD

) 4.3 6 mA

AVDD

Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I

) 37 40 mA

DVDD

Voltage Range 3.1 3.3 3.5 V
Clock Supply Current (I

CLKVDD

+ I

) 25 30 mA

PLLVDD

Rev. C | Page 4 of 40

AD9772A

Parameter Min Typ Max Unit

CLKVDD (PLLVDD = 0 V)

Voltage Range 3.1 3.3 3.5 V

Clock Supply Current (I
Nominal Power Dissipation
Power Supply Rejection Ratio (PSRR)

PSRR − AVDD −0.6 +0.6 % of FSR/V
PSRR − DVDD −0.025 +0.025 % of FSR/V

OPERATING RANGE −40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

Measured at f

5

Measured with PLL enabled at f

6

Measured over a 3.0 V to 3.6 V range.

driving a virtual ground.

OUTA

= 100 MSPS and f

DATA

OUTFS

) 6.0 mA

CLKVDD

5

6

, is 32× the I

OUT

= 50 MSPS and f

DATA

current.

REF

= 1 MHz with DIV1 and DIV0 = 0 V.

= 1 MHz.

OUT

253 272 mW

Rev. C | Page 5 of 40

AD9772A

DYNAMIC SPECIFICATIONS

T

to T

MIN

output, 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f
Output Settling Time (tST) (to 0.025%) 11 ns
Output Propagation Delay1 (tPD) 17 ns
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%) 0.8 ns
Output Noise (I

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 70 MHz

1

Propagation delay is delay from the CLK+/CLK− input to the DAC update.

2

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

) 400 MSPS

DAC

2

= 20 mA) 50 pA√Hz

OUTFS

= 0 dBFS)

OUT

f

= 65 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 160 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 78 MSPS; f

DATA

f

= 65 MSPS; f

DATA

f

= 100 MSPS; f

DATA

= 1.01 MHz 82 dBc

OUT

= 10.01 MHz 75 dBc

OUT

= 25.01 MHz 73 dBc

OUT

= 5.02 MHz 82 dBc

OUT

= 20.02 MHz 75 dBc

OUT

= 50.02 MHz 65 dBc

OUT

= f

OUT1

= 5.01 MHz; f

OUT1

= 15.01 MHz; f

OUT1

= 24.1 MHz; f

OUT1

= 10.02 MHz; f

OUT1

= 30.02 MHz; f

OUT1

= 48.2 MHz; f

OUT1

= 1.0 MHz; 0 dBFS −80 dB

OUT

= 10.01 MHz; 0 dBFS −74 dB

OUT

= 16.26 MHz; 0 dBFS 71 dB

OUT

= 25.1 MHz; 0 dBFS 71 dB

OUT

= 6.01 MHz 85 dBc

OUT2

= 17.51 MHz 75 dBc

OUT2

= 26.2 MHz 68 dBc

OUT2

= 12.02 MHz 85 dBc

OUT2

= 35.02 MHz 70 dBc

OUT2

= 52.4 MHz 65 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, differential transformer-coupled

OUTFS

0.8 ns

WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing

IF = 16 MHz, f
IF = 32 MHz, f

= 65.536 MSPS 78 dBc

DATA

= 131.072 MSPS 68 dBc

DATA

15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at −12 dBFS 88 dBFS
f

= 65 MSPS, Missing Center

DATA

68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at −20 dBFS 77 dBFS
f

= 52 MSPS, f

DATA

= 208 MHz

DAC

Rev. C | Page 6 of 40

AD9772A

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

PLL CLOCK ENABLED (SEE Figure 2)

Input Setup Time (tS)

Input Hold Time (tH)

Latch Pulse Width (t

PLL CLOCK DISABLED (SEE Figure 3)

Input Setup Time (tS)

Input Hold Time (tH)

Latch Pulse Width (t
CLK+/CLK− to PLLLOCK Delay (tOD)

PLLLOCK (VOH), TA = 25°C 3.0 V
PLLLOCK (VOL), TA = 25°C 0.3 V

1

MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 A.

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

1

= 20 mA, unless otherwise noted.

OUTFS

−10 +10 µA

TA = 25°C 1.5 ns
TA = −40 to +85°C 2.1 ns

TA = 25°C 1.3 ns
TA = −40 to +85°C 1.6 ns

), TA = 25°C 1.5 ns

LPW

TA = 25°C −0.7 ns
TA = −40 to +85°C −0.4 ns

TA = 25°C 3.3 ns
TA = −40 to +85°C 3.7 ns

), TA = 25°C 1.5 ns

LPW

TA = 25°C 1.9 2.8 ns
TA = −40 to +85°C 1.8 3.3 ns

DB0 TO DB13

CLK+ – CLK–

I

OUTA

I

OUTB

t

H

t

LPW

t

PD

t

ST

0.025%

0.025%

OR

t

S

Figure 2. Timing Diagram—PLL Clock Multiplier Enabled

DB0 TO DB13

CLK+ – CLK–

02253-002

Rev. C | Page 7 of 40

t

H

t

OD

t

LPW

t

PD

t

ST

0.025%

PLLLOCK

I

OUTA

OR

I

OUTB

t

S

Figure 3. Timing Diagram—PLL Clock Multiplier Disabled

0.025%

02253-003

AD9772A

DIGITAL FILTER SPECIFICATIONS

T

to T

MIN

50 Ω doubly terminated, unless otherwise noted.

Table 4.

Parameter Min Typ Max Unit

MAXIMUM INPUT DATA RATE (f
DIGITAL FILTER CHARACTERISTICS

Pass-Bandwidth1: 0.005 dB 0.401 f
Pass-Bandwidth: 0.01 dB 0.404 f
Pass-Bandwidth: 0.1 dB 0.422 f

Pass-Bandwidth: −3 dB 0.479 f
LINEAR PHASE (FIR IMPLEMENTATION)
STOP BAND REJECTION 73 dB

0.606 f
GROUP DELAY
IMPULSE RESPONSE DURATION

−40 dB 36 Input clocks

−60 dB 42 Input clocks

1

Excludes sin(x)/x characteristic of DAC.

2

Defined as the number of data clock cycles between impulse input and peak of output response.

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

) 150 MSPS

DATA

to 1.394 f

OUTPUT (dB)

–100

–120

–140

CLOCK

2

0

–20

–40

–60

–80

0

CLOCK

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FREQUENCY (DC TO

f

DATA

)

1.00. 1

2253-004

Figure 4. FIR Filter Frequency Response—Baseband Mode

1.0

0.8

0.6

0.4

0.2

NORMALIZE D OUTPUT

0

–0.2

–0.4

0

5

10 15 20 25 30 35 40 45

TIME (Samples)

02253-005

Figure 5. FIR Filter Impulse Response—Baseband Mode

= 20 mA, differential transformer-coupled output,

OUTFS

OUT/fDATA

OUT/fDATA

OUT/fDATA

OUT/fDATA

11 Input clocks

Table 5. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)

Lower
Coefficient

Upper
Coefficient

Integer
Value

H(1) H(43) 10
H(2) H(42) 0
H(3) H(41) −31
H(4) H(40) 0
H(5) H(39) 69
H(6) H(38) 0
H(7) H(37) −138
H(8) H(36) 0
H(9) H(35) 248
H(10) H(34) 0
H(11) H(33) −419
H(12) H(32) 0
H(13) H(31) 678
H(14) H(30) 0
H(15) H(29) −1083
H(16) H(28) 0
H(17) H(27) 1776
H(18) H(26) 0
H(19) H(25) −3282
H(20) H(24) 0
H(21) H(23) 10,364
H(22) 16,384

Rev. C | Page 8 of 40

AD9772A

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter With Respect to Rating

AVDD, DVDD, CLKVDD,

PLLVDD

AVDD, DVDD, CLKVDD,

PLLVDD

ACOM, DCOM,

CLKCOM, PLLCOM

REFIO, REFLO, FSADJ,

SLEEP

I

, I

OUTA

OUTB

DB0 to DB13, MOD0,

MOD1, PLLLOCK

CLK+, CLK− CLKCOM

DIV0, DIV1, RESET CLKCOM

LPF PLLCOM

Junction Temperature 125°C
Storage Temperature −65°C to +150°C
Lead Temperature

(10 sec)

ACOM, DCOM,
CLKCOM, PLLCOM

AVDD, DVDD,
CLKVDD, PLLVDD

ACOM, DCOM,
CLKCOM, PLLCOM

ACOM

ACOM

DCOM

300°C

−0.3 V to +4.0 V

−4.0 V to +4.0 V

−0.3 V to +0.3 V

−0.3 V to
AVDD + 0.3 V

−1.0 V to
AVDD + 0.3 V

−0.3 V to
DVDD + 0.3 V

−0.3 V to
CLKVDD + 0.3 V

−0.3 V to
CLKVDD + 0.3 V

−0.3 V to
PLLVDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θ

48-Lead LQFP 91 28 °C/W

JA

θ

JC

Unit

ESD CAUTION

Rev. C | Page 9 of 40

AD9772A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

AVDD

ACOM

AD9772A

TOP VIEW

(Not to Scale)

DB1

MOD0

(LSB) DB0

I

MOD1

OUTAIOUTB

ACOM

FSADJ

REFIO

REFLOACOM

36

SLEEP

35

LPF

34

PLLVDD

33

PLLCOM

32

CLKVDD

31

CLKCOM

30

CLK–

29

CLK+

28

DIV0

27

DIV1

26

RESET

25

PLLLOCK

NC

NC

DVDD

DVDD

DCOM

DCOM

2253-006

1

DCOM

2

DCOM

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

3

4

5

6

7

8

9

10

11

12

(MSB) DB13

NC = NO CONNECT

DVDD

DVDD

48 47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

13 14 15 16 17 18 19 20 21 22 23 24

DB3

DB2

Figure 6. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 19, 20 DCOM Digital Common.
3 DB13 Most Significant Data Bit (MSB).
4 to 15 DB12 to DB1 Data Bit 1 to Data Bit 12.
16 DB0 Least Significant Data Bit (LSB).
17 MOD0

Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is,
half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin
are set high.

18 MOD1

Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing

occurs if this pin and the MOD0 pin are set high.
23, 24 NC No Connect. Leave open.
21, 22, 47, 48 DVDD Digital Supply Voltage (3.1 V to 3.5 V).
25 PLLLOCK

Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL

clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High

indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF).
26 RESET

Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input

data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when

PLL is disabled.
27, 28 DIV1, DIV0 PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Tabl e 10 ).
29 CLK+ Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
30 CLK− Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
31 CLKCOM Clock Input Common.
32 CLKVDD Clock Input Supply Voltage (3.1 V to 3.5 V).
33 PLLCOM Phase-Lock Loop Common.
34 PLLVDD

Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to

PLLCOM.
35 LPF

PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than

10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in

Figure 61.
36 SLEEP Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM.
37, 41, 44 ACOM Analog Common.
38 REFLO

Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal
reference.

Rev. C | Page 10 of 40

AD9772A

Pin No. Mnemonic Description

39 REFIO

40 FSADJ Full-Scale Current Output Adjust.
42 I
43 I

B Complementary DAC Current Output. Full-scale current is selected when all data bits are 0s.

OUTB

OUTA

45, 46 AVDD Analog Supply Voltage (3.1 V to 3.5 V).

Reference Input/Output. This pin serves as the reference input when the internal reference is disabled (that
is, when REFLO is tied to AVDD), or it serves as the 1.2 V reference output when the internal reference is
activated (that is, when REFLO is tied to ACOM). If the internal reference is activated, a 0.1 µ F capacitor to
ACOM is required.

DAC Current Output. Full-scale current is selected when all data bits are 1s.

Rev. C | Page 11 of 40

AD9772A

TERMINOLOGY

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output and is determined by
a straight line drawn from zero to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to
full scale that is associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant as the digital input increases.

Offset Error

Offset error is the deviation of the output current from the ideal
of zero. For I
0s. For I

OUTB

, 0 mA output is expected when the inputs are all

OUTA

, 0 mA output is expected when all inputs are set to 1s. B

Gain Error

Gain error is the difference between the actual and ideal output
span. The actual span is determined by the output when all inputs
are set to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The output compliance range is the range of allowable voltage
at the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown, resulting in nonlinear performance.

Tem p er at u re Dr i ft

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

. For offset

MAX

and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.

Power Supply Rejection

Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.

Settling Time

Settling time is the time required for the output to reach and
remain within a specified error band about its final value. It is
measured from the start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

Spurious-free dynamic range is the difference, in decibels,
between the rms amplitude of the output signal and the peak
spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

Pass Band

Pass band is the frequency band in which any input applied
therein passes unattenuated to the DAC output.

Stop-Band Rejection

Stop-band rejection is the amount of attenuation of a frequency
outside the pass band applied to the DAC relative to a full-scale
signal applied at the DAC input within the pass band.

Group Delay

Group delay is the number of input clocks between an impulse
applied at the device input and the peak DAC output current.

Impulse Response

Impulse response is the response of the device to an impulse
applied to the input.

Adjacent-Channel Power Ratio (ACPR)

ACPR is a ratio, in dBc, between the measured power within a
channel relative to its adjacent channel.

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