Ultrafast
a
FEATURES
4.5 ns Propagation Delay
200 ps Maximum Propagation Delay Dispersion
Single +5 V or 65 V Supply Operation
Complementary Matched TTL Outputs
APPLICATIONS
High Speed Line Receivers
Peak Detectors
Window Comparators
High Speed Triggers
Ultrafast Pulse Width Discriminators
GENERAL DESCRIPTION
The AD9696 and AD9698 are ultrafast TTL-compatible voltage comparators able to achieve propagation delays previously
possible only in high performance ECL devices. The AD9696 is
a single comparator providing 4.5 ns propagation delay, 200 ps
maximum delay dispersion and 1.7 ns setup time. The AD9698
is a dual comparator with equally high performance; both devices are ideal for critical timing circuits in such applications as
ATE, communications receivers and test instruments.
TTL Comparators
AD9696/AD9698
Both devices allow the use of either a single +5 V supply or
±5 V supplies. The choice of supplies determines the common
mode input voltage range available: –2.2 V to +3.7 V for ±5 V
operation, +1.4 V to +3.7 V for single +5 V supply operation.
The differential input stage features high precision, with offset
voltages that are less than 2 mV and offset currents less than
1 µA. A latch enable input is provided to allow operation in ei-
ther sample-and-hold or track-and-hold applications.
The AD9696 and AD9698 are both available as commercial
temperature range devices operating from ambient temperatures
of 0°C to +70°C, and as extended temperature range devices for
ambient temperatures from –55°C to +125°C. Both versions are
available qualified to MIL-STD-883 class B.
Package options for the AD9696 include a 10-pin TO-100 metal
can, an 8-pin ceramic DIP, an 8-pin plastic DIP, and an 8-lead
small outline plastic package. The AD9698 is available in a
16-pin ceramic DIP, a 16-lead ceramic gullwing, a 16-pin plastic
DIP and a 16-lead small outline plastic package. Military qualified versions of the AD9696 come in the TO-100 can and
ceramic DIP; the dual AD9698 comes in ceramic DIP.
FUNCTIONAL BLOCK DIAGRAM
AD9696/AD9698 Architecture
LATCH
GAIN
LEVEL
SHIFT
OUTPUTINPUT
AD9698
NONINVERTING
INPUT
INVERTING
INPUT
#1
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD9696
NONINVERTING
INPUT
INVERTING
INPUT
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
#2
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
NONINVERTING
INPUT
INVERTING
INPUT
AD9696/AD9698–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage (+VS/–VS) . . . . . . . . . . . . . . . . . . . .+7 V/–7 V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.4 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range
AD9696/AD9698KN/KQ/KR . . . . . . . . . . . . 0°C to +70°C
AD9696/AD9698TQ . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature
S
KQ/TQ Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
KN/KR Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
2
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . +300°C
(Supply Voltages = –5.2 V and +5.0 V; load as specified in Note 4,
ELECTRICAL CHARACTERISTICS
unless otherwise noted)
08C to +708C –558C to +1258C
AD9696/AD9698 AD9696/AD9698
Test KN/KQ/KR TQ
Parameter Temp Level Min Typ Max Min Typ Max Units
INPUT CHARACTERISTICS
Input Offset Voltage
4
+25°C I 1.0 2.0 1.0 2.0 mV
Full VI 3.0 3.0 mV
Input Offset Voltage Drift Full V 10 10 µV/°C
Input Bias Current +25°C I 16 55 16 55 µA
Full VI 110 110 µA
Input Offset Current +25°C I 0.4 1.0 0.4 1.0 µA
Full VI 1.3 1.3 µA
Input Capacitance +25°CV 3 3 pF
Input Voltage Range
±5.0 V Full VI –2.2 +3.7 –2.2 +3 7 V
+5.0 V Full VI +1.4 +3.7 +1.4 +3.7 V
Common Mode Rejection Ratio
±5.0 V Full VI 80 85 80 85 dB
+5.0 V Full VI 57 63 57 63 dB
LATCH ENABLE INPUT
Logic “1” Voltage Threshold Full VI 2.0 2.0 V
Logic “0” Voltage Threshold Full VI 0.8 0.8 V
Logic “1” Current Full VI 10 10 µA
Logic “0” Current Full VI 1 1 µA
DIGITAL OUTPUTS
Logic “1” Voltage (Source 4 mA) Full VI 2.7 3.5 2.7 3.5 V
Logic “0” Voltage (Sink 10 mA) Full VI 0.4 0.5 0.4 0.5 V
SWITCHING PERFORMANCE
Propagation Delay (t
PD
5
)
Input to Output HIGH Full IV 4.5 7.0 4.5 7.0 ns
Input to Output LOW Full IV 4.5 7.0 4.5 7.0 ns
Latch Enable to Output HIGH +25°C IV 6.5 8.5 6.5 8.5 ns
Latch Enable to Output LOW +25°C IV 6.5 8.5 6.5 8.5 ns
Delta Delay Between Outputs +25°C IV 0.5 1.5 0.5 1.5 ns
Propagation Delay Dispersion
20 mV to 100 mV Overdrive +25°C V 100 100 ps
100 mV to 1.0 V Overdrive +25°C IV 100 200 100 200 ps
Rise Time
Fall Time
10
10
+25°C V 1.85 1.85 ns
+25°C V 1.35 1.35 ns
Latch Enable
Pulse Width [t
Setup Time (t
] +25°C IV 3.5 2.5 3.5 2.5 ns
PW(E)
) +25°C IV 3 1.7 3 1.7 ns
S
Hold Time (tH) +25°C IV 3 1.9 3 1.9 ns
–2–
REV. B
AD9696/AD9698
08C to +708C –558C to +1258C
AD9696/AD9698 AD9696/AD9698
Test KN/KQ/KR TQ
Parameter Temp Level Min Typ Max Min Typ Max Units
POWER SUPPLY
Positive Supply Current
AD9696 Full VI 26 32 26 32 mA
AD9698 Full VI 52 64 52 64 mA
Negative Supply Current
AD9696 Full VI 2.5 4.0 2.5 4.0 mA
AD9698 Full VI 5.0 8.0 5.0 8.0 mA
Power Dissipation
AD9696 +5.0 V Full V 130 130 mW
AD9696 ±5.0 V Full V 146 146 mW
AD9698 +5.0 V Full V 260 260 mW
AD9698 ±5.0 V Full V 292 292 mW
Power Supply Rejection Ratio
NOTES
1
Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances:
AD9696 Metal Can θJA = 170°C/W θJC = 50°C/W
AD9696 Ceramic DIP θJA = 110°C/W θJC = 20°C/W
AD9696 Plastic DIP θJA = 160°C/W θJC = 30°C/W
AD9696 Plastic SOIC θJA = 180°C/W θJC = 30°C/W
AD9698 Ceramic DIP θJA = 90°C/W θJC = 25°C/W
AD9698 Plastic DIP θJA = 100°C/W θJC = 20°C/W
AD9698 Plastic SOIC θJA = 120°C/W θJC = 20°C/W
6
7
8
9
+25°CVI 70 70 dB
(+5.0 V)
(–5.2 V)
Full VI 65 65 dB
3
Load circuit has 420 Ω from +VS to output; 460 Ω from output to ground.
4
RS ≤100 Ω.
5
Propagation delays measured with 100 mV pulse; 10 mV overdrive.
6
Supply voltages should remain stable within ±5% for normal operation.
7
Specification applies to both +5 V and ±5 V supply operation.
8
Specification applies to only ±5 V supply operation.
9
Measured with nominal values ±5% of +VS and –VS.
10
Although fall time is faster than rise time, the complementary outputs cross at
midpoint of logic swing because of delay on start of falling edge.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temp-
erature extremes for commercial/industrial devices.
ORDERING GUIDE
Package
Model Package Temperature Option
1
AD9696KN Plastic DIP 0°C to +70°C N-8
AD9696KR SOIC 0°C to +70°C R-8
AD9696KQ Cerdip 0°C to +70°C Q-8
AD9696TQ Cerdip –55°C to +125°C Q-8
AD9696TZ/883B
2
Gullwing –55°C to +125°C Z-8A
AD9698KN Plastic DIP 0°C to +70°C N-16
AD9698KR SOIC 0°C to +70°C R-16A
AD9698KQ Cerdip 0°C to +70°C Q-16
AD9698TQ Cerdip –55°C to +125°C Q-16
AD9698TZ/883B3Gullwing –55°C to +125°C Z-16
NOTES
1
N = Plastic DIP, Q = Cerdip, R = Small Outline (SOIC), Z = Ceramic Leaded
Chip Carrier.
2
Refer to AD9696TZ/883B military data sheet.
3
Refer to AD9698TZ/883B military data sheet.
REV. B
–3–
AD9696/AD9698
LATCH ENABLE 1 (+IN
Q1
(N/C)
OUT
(–VS)
Q1
OUT
GROUND (–IN1)
N/C (+IN
(–IN2)
–V
S
(+VS)
–IN
1
+IN1 (N/C)
)
1
)
2
1
2
3
4
(Not to Scale)
5
6
7
8
PIN CONFIGURATIONS
Q2
(LATCH ENABLE 1)
16
OUT
15
Q2
(GROUND)
OUT
14
GROUND (Q1
13
TOP VIEW
LATCH ENABLE 2 (Q1
N/C (Q2
12
11
10
+VS (Q2
(GROUND)
–IN
2
+IN
(LATCH ENABLE 2)
9
2
OUT
OUT
)
OUT
)
OUT
+V
S
)
)
1
+IN
2
TOP VIEW
(Not to Scale)
–IN
3
4
–V
S
8
7
6
5
Q
OUT
Q
OUT
GROUND
LATCH
ENABLE
AD9698KN/KQ/TQ
[AD9698KR/TZ PINOUTS SHOWN IN ( )]
AD9696KN/KR/KQ/TQ/TZ
Name Function
Q1
Q1
OUT
OUT
One of two complementary outputs. Q1
–IN
and LATCH ENABLE 1 is at logic LOW.
1
One of two complementary outputs. Q1
+IN
and LATCH ENABLE 1 is at logic LOW.
1
will be at logic HIGH if voltage at +IN1 is greater than voltage at
OUT
will be at logic HIGH if voltage at –IN1 is greater than voltage at
OUT
GROUND Analog and digital ground return. All GROUND pins should be connected together and to a low impedance
ground plane near the comparator.
LATCH Output at Q1
ENABLE 1 When LATCH ENABLE 1 is at logic HIGH, the output at Q1
the latch command, delayed by the Latch Enable Setup Time (t
will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW.
OUT
will reflect the input state at the application of
OUT
). Since the architecture of the input stage (see
S
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (t
); for guaranteed performance, tS must be 3 ns.
S
N/C No internal connection to comparator.
–V
S
–IN
1
+IN
1
+IN
2
–IN
2
+V
S
LATCH Output at Q2
ENABLE 2 When LATCH ENABLE 2 is at logic HIGH, the output at Q2
Negative power supply connection; nominally –5.2 V.
Inverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #2.
Inverting input of differential input stage for Comparator #2.
Positive power supply connection; nominally +5 V.
will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW.
OUT
will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (t
OUT
). Since the architecture of the input stage (see
S
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
Q2
Q2
OUT
OUT
within 1.7 ns after the latch. This is the Setup Time (t
One of two complementary outputs. Q2
+IN
and LATCH ENABLE 2 is at logic LOW.
2
One of two complementary outputs. Q2
will be at logic HIGH if voltage at –IN2 is greater than voltage at
OUT
will be at logic HIGH if voltage at +IN2 is greater than voltage at
OUT
); for guaranteed performance, tS must be 3 ns.
S
–IN2 and LATCH ENABLE 2 is at logic LOW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
LATCH
ENABLE
LATCH
COMPARE
AD9696/AD9698
TWO DIODES
V
t
H
OS
t
PW (E)
ABOVE GROUND
t
S
DIFFERENTIAL
INPUT VOLTAGE
Q
Q
t
t
PD (E)
V
IN
V
OD
50%
t
PD
50%
t
S
– MINIMUM SETUP TIME (Typically 1.7ns)
t
– MINIMUM HOLD TIME (Typically 1.9ns)
H
– INPUT TO OUTPUT DELAY
PD
– LATCH ENABLE TO OUTPUT DELAY
AD9696/AD9698 Timing Diagram
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions AD9696 . . . . . . . . . . . . . 59×71×15 (±2) mils
AD9698 . . . . . . . . . . . . 79×109×15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4×4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
t
PD (E)
t
– MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns)
PW (E)
V
– INPUT OFFSET VOLTAGE
OS
– OVERDRIVE VOLTAGE
V
OD
THEORY OF OPERATION
Refer to the block diagram of the AD9696/AD9698 comparators. The AD9696 and AD9698 TTL voltage comparator architecture consists of five basic stages: input, latch, gain, level shift
and output. Each stage is designed to provide optimal performance and make it easy to use the comparators.
The input stage operates with either a single +5-volt supply, or
S
with a +5-volt supply and a –5.2-volt supply. For optimum
power efficiency, the remaining stages operate with only a single
+5-volt supply. The input stage is an input differential pair
without the customary emitter follower buffers. This configuration increases input bias currents but maximizes the input voltage range.
A latch stage allows the most recent output state to be retained
as long as the latch input is held high. In this way, the input to
the comparator can be changed without any change in the output state. As soon as the latch enable input is switched to LOW,
the output changes to the new value dictated by the signal applied to the input stage.
The gain stage assures that even with small values of input voltage, there will be sufficient levels applied to the following stages
to cause the output to switch TTL states as required. A level
shift stage between the gain stage and the TTL output stage
guarantees that appropriate voltage levels are applied from the
gain stage to the TTL output stage.
Only the output stage uses TTL logic levels; this minimum use
of TTL circuits maximizes speed and minimizes power consumption. The outputs are clamped with Schottky diodes to assure that the rising and falling edges of the output signal are
closely matched.
The AD9696 and AD9698 represent the state of the art in high
speed TTL voltage comparators. Great care has been taken to
optimize the propagation delay dispersion performance. This assures that the output delays will remain constant despite varying
levels of input overdrive. This characteristic, along with closely
matched rising and falling outputs, provides extremely consistent results at previously unattainable speeds.
REV. B
–5–
AD9696/AD9698
APPLICATIONS
General
Two characteristics of the AD9696 and AD9698 should be considered for any application. First is the fact that all TTL comparators are prone to oscillate if the inputs are close to equal for
any appreciable period of time. One instance of this happening
would be slow changes in the unknown signal; the probability of
oscillation is reduced when the unknown signal passes through
the threshold at a high slew rate. Another instance is if the unknown signal does not overdrive the comparator logic. Unless
they are overdriven, TTL comparators have undershoot when
switching logic states. The smaller the overdrive, the greater the
undershoot; when small enough, the comparator will oscillate,
not being able to determine a valid logic state. For the AD9696
and AD9698, 20 mV is the smallest overdrive which will assure
crisp switching of logic states without significant undershoot.
The second characteristic to keep in mind when designing
threshold circuits for these comparators is twofold: (1) bias currents change when the threshold is exceeded; and (2) ac input
impedance decreases when the comparator is in its linear region.
During the time both transistors in the differential pair are conducting, the ac input impedance drops by orders of magnitude.
Additionally, the input bias current switches from one input to
the other, depending upon whether or not the threshold is exceeded. As a result, the input currents follow approximately the
characteristic curves shown below.
LINEAR
{
SIGNAL
VOLTAGE
AT +INPUT
+INPUT
CURRENT
– INPUT
CURRENT
REGION
Threshold Input Currents
This characteristic will not cause problems unless a high impedance threshold circuit or drive circuit is employed. A circuit
similar to that shown in the window comparator application can
eliminate this possible problem.
Window Comparator
Many applications require determining when a signal’s voltage
falls within, above, or below a particular voltage range. A simple
tracking window comparator can provide this data. Figure 1
shows such a window comparator featuring high speed, TTL
compatibility, and ease of implementation.
Two comparators are required to establish a “window” with upper and lower threshold voltages. The circuit shown uses the
AD9698 dual ultrafast TTL comparator. In addition to the cost
and space savings over a design using two single comparators,
the dual comparator on a single die produces better matching of
both dc and dynamic characteristics.
R
R
A1
+V
V
IN
V
SIGNAL
–V
REF
REF
+IN
–IN
+IN
–IN
R
1
1
1
2
2
A2
R
2
AD9698
R = 10kΩ
R
+ R2 >5kΩ
1
A
,A2 = AD708 or OP– 290
1
(±5V) (+5V)
Q
1 OUT
Q
1 OUT
Q
2 OUT
Q
2 OUT
Q
1 OUT
+Q
2 OUT
Figure 1. AD9698 Used as Window Detector
When configured as shown, the op amps generate reference levels for the comparators that are equally spaced above and below
the applied V
ratio of R1 and R2. For a given ratio of R1 and R2, +V
–V
will be fixed percentages above and below VIN. As an ex-
REF
. The width of the window is established by the
IN
REF
and
ample, using 2.2 kΩ for R1 and 10 kΩ for R2 creates a ±10%
window. When V
–V
will be +2.7 V. Likewise, for a –2 V input, the thresholds
REF
equals +3 V, +V
IN
will be +3.3 V and
REF
will be –1.8 V and –2.2 V. Windows of differing percentage
width can be calculated with the equation:
(1–X)/2X = R2/R1
where:
X = % window
Additionally, the low impedance of the op amp outputs assures
that the threshold voltages will remain constant when the input
currents change as the signal passes through the threshold voltage levels.
The output of the AND gate will be high while the signal is inside the window. Q1
+V
, and Q2
REF
OUT
will be high when the signal is above
OUT
will be high when the signal is below –V
REF
.
Crystal Oscillator
Oscillators are used in a wide variety of applications from audio
circuits to waveform generators, from ATE triggers and telecommunications transceivers to radar. Figure 2 shows a versatile
and inexpensive oscillator. The circuit uses the AD9696, in a
positive feedback mode, and is capable of generating accurate
and stable oscillations with frequencies ranging from 1 MHz to
more than 40 MHz.
To generate oscillations from 1 to 25 MHz, a fundamental
mode crystal is used without the dc blocking capacitor and
choke. The parallel capacitor on the inverting input is selected
for stability (0.1 µF for 1–10 MHz; 220 pF for frequencies
above 10 MHz).
–6–
REV. B
+V
S
2kΩ
0.1µF
(VALUE
DEPENDS
ON FREQ.)
FOR USE WITH
OVERTONE
CRYSTAL
(220pF for Freq. > 10MHz)
2kΩ
0.1µF
AD9696
+IN
–IN
1– 40MHz
LATCH
6
GROUND
ENABLE
Q
OUT
7
8
Q
OUT
OSCILLATOR
OUTPUT
+V
S
1 5
+
2
–
3
4
–V
S
2kΩ
Figure 2. AD9696 Oscillator Circuit (Based on DIP Pinouts)
When generating frequencies using a nonfundamental mode
crystal, a choke and dc blocking capacitor are added. As an example, a 36 MHz oscillator can be achieved by using a 12 MHz
crystal operating on its third overtone. To suppress oscillation at
the 12 MHz fundamental, the value of the choke is chosen to
provide a low reactive impedance at the fundamental frequency
while maintaining a high reactive impedance at the desired output frequency (for 36 MHz operation, L = 1.8 µH). The shunt
capacitor at the inverting input has a value of 220 pF for a stable
36 MHz frequency.
AD9696/AD9698
LAYOUT CONSIDERATIONS
When working with high speed circuits, proper layout is critical.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. In addition, digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. All analog signals
should be kept as far away from digital signal paths as possible;
this reduces the amount of digital switching noise that might be
capacitively coupled into the analog section of the circuit.
In high speed circuits, layout of the ground circuit is the most
important factor. A single, low impedance ground plane, on the
component side of the board, will reduce noise in the circuit
ground. It is especially important to maintain continuity of the
ground plane under and around the AD9696 or AD9698.
Sockets limit the dynamic performance of the device and should
be used only for prototypes or evaluation.
AD1
AD2
GND
AD1
AD2
– V
0.1µF
4
2
3
5
RESISTORS ARE 1kΩ ±5%
–0.9V
–1.7V
–0.9 V
–1.7V
S
AD9696
(8-PIN DIP)
5µs
0.1µF
+V
S
1
7
8
6
REV. B
Burn-In Circuit
–7–
AD9696/AD9698
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1320a–10–2/91
–8–
PRINTED IN U.S.A.
REV. B
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