1.5 ns Rise/2.0 ns Fall Times
Output Current: 180 mA @ 3 V, 200 mA @ 2.5 V
Bias Current: 90 mA @ 3 V
Modulation Current: 60 mA @ 3 V
Offset Current: 30 mA @ 3 V
Single +5 V Power Supply
Switching Rate: 200 MHz
Onboard Light Power Control Loops
APPLICATIONS
Laser Printers and Copiers
Optical Disk Drives
FO Datacomm
GENERAL DESCRIPTION
The AD9660 is a highly integrated driver for laser diode applications such as optical disk drives, printers, and copiers. The
AD9660 gets feedback from an external photo detector and includes two analog feedback loops to allow users to set “bias”
and “write” (for optical disk drives) power levels of the laser,
and switch between the two power levels at up to 200 MHz.
Output rise and fall times are typically 1.5 ns and 2.0 ns to
complement printer applications that use image enhancing techniques such as pulse width modulation to achieve gray scale,
and allow disk drive applications to improve density and take
advantage of pulsed write formats. Control signals are TTL/
CMOS compatible.
with Light Power Control
AD9660
FUNCTIONAL BLOCK DIAGRAM
WRITE
PULSE
WRITE
CALIBRATE
WRITE
LEVEL
BIAS
LEVEL
BIAS
CAL
TRANSIMPEDANCE
BIAS
T/H
V:1T/H
AMPLIFIER
V:1
OUTPUT
DRIVER
OUTPUT
DRIVER
AD9660
The driver output provides up to 180 mA of current @ 3 V,
90 mA of BIAS current, 60 mA of modulation current, and
30 mA of offset current. The onboard disable circuit turns off
the output drivers and returns the light power control loops to a
safe state.
The AD9660 can also be used in closed loop applications in
which the output power level follows an analog WRITE LEVEL
voltage input. By optimizing the external hold capacitor, and
the photo detector, the write loop can achieve bandwidths as
high as 25 MHz.
The AD9660 is offered in a 28-pin plastic SOIC for operation
over the commercial temperature range (0°C to +70°C).
OUTPUT
SENSE
INPUT
PHOTO
DETECTOR
DIODE
LASER
DIODE
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Maximum Pulse RateIV+25°C200250MHz3 dB Reduction in I
OUT
Output Propagation Delay (tPD), Rising1IVFull1.63.0ns
Output Propagation Delay (t
Output Current Rise Time
Output Current Fall Time
WRITE CAL Aperture Delay
Disable Time
I+25°C1.551.751.90V
Temperature CoefficientV–0.2mV/°C
Output CurrentV+25°C–0.51.0mA
SENSE IN
Current GainV+25°C1.85mA/mA
VoltageI+25°C3.74.04.3VI
MONITOR
= 2 mA
Input ResistanceV+25°C<150Ω
POWER SUPPLY (DISABLE = HIGH)
+V
VoltageI+25°C4.755.005.25VDISABLE = HIGH
S
CurrentI+25°C75110150mA
+V
S
Power DissipationI+25°C550mW
OFFSET CURRENT
OFFSET SET VoltageI+25°C1.11.41.7VI
NOTES
1
Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to 50% point of the rising/falling edge of the output modulation current.
2
Rise time measured between the 10% and 90% points of the rising transition of the modulation current.
3
Fall time measured between the 10% and 90% points of the falling transition of the modulation current.
4
Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is
held during this test.
5
Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable
is similar to fall time during normal operation.
Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
2
Typical thermal impedance is θJA = 45°C/W, θJC = 41°C/W.
ORDERING GUIDE
ModelTemperature RangePackage Option
AD9660KR0°C to +70°CR-28
AD9660KR-REEL 0°C to +70°CR-28 (1000/reel)
PIN ASSIGNMENTS
EXPLANATION OF TEST LEVELS
Test Level
I.100% Production Tested.
II. 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample Tested Only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at +25°C, sample
tested at temperature extremes.
WRITE CAL
WRITE PULSE
WRITE LEVEL
V
REF
WRITE HOLD
GROUND
+V
SENSE IN
GAIN
POWER MONITOR
+V
GROUND
BIAS HOLD
BIAS LEVEL
S
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9660KR
TOP VIEW
(Not to Scale)
28
OFFSET PULSE
27
OFFSET SET
26
GROUND
25
+V
S
24
OUTPUT
23
+V
S
22
OUTPUT
21
+V
S
20
OUTPUT
+V
19
S
OUTPUT
18
17
GROUND
DISABLE
16
15
BIAS CAL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Equivalent Circuits
REV. 0
–3–
AD9660
PIN DESCRIPTIONS
PinFunction
OUTPUTAnalog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally.
BIAS LEVELAnalog voltage input, V
tion as follows:
BIAS CALTTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop
T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold
mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH.
BIAS HOLDExternal hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic
LOW is:
±∆I
BIAS
=
WRITE PULSETTL/CMOS compatible, current control signal. Logic HIGH supplies I
LOW turns I
MODULATION
WRITE CALTTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling
calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration
mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no delay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immediately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write
loop T/H and places it in hold mode. Floats logic HIGH.
WRITE LEVELAnalog voltage input, V
I
tion as follows:
MONITOR
REF
18 ×10
C
to V
+ 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibra-
REF
I
MONITOR
–9
t
BIAS HOLD
BIAS HOLD
off. Floats logic HIGH.
REF
to V
=
+1.6 V. Write current is set proportional to the input voltage during calibra-
REF
V
WRITE LEVEL−VREF
1. 85 ×(R
GAIN
V
BIAS LEVEL−VREF
=
1. 85 × R
+50 Ω
()
GAIN
. Bandwidth of the loop is:
+ 50 Ω)
BW =
2π (550 Ω)C
MODULATION
1
BIAS HOLD
to the laser diode. Logic
WRITE HOLDExternal hold capacitor for the write loop T/H. Approximate droop in I
−9
±∆I
logic LOW is:
MODULATED
BW =
2π (550 Ω) C
1
BIAS HOLD
SENSE INAnalog current input, I
MONITOR
18 ×10
=
, from PIN photo detector diode. SENSE IN should be connected to the cathode
t
WRITE HOLD
C
WRITE HOLD
. Bandwidth of the loop is:
MODULATION
current while WRITE CAL is
of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN varies slightly with temperature and current, but is typically 4.0 V.
GAINExternal connection for the feedback network of the transimpedance amplifier. External feedback network, R
and C
, should be connected between GAIN and POWER MONITOR. See text for choosing values.
GAIN
GAIN
POWEROutput voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo
MONITORdiode.
OFFSETSet resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +V
S
CURRENT SET determines offset current level. The input voltage at this node varies slightly with temperature and current, but is
typically 1.4 V. See curves. Can also be driven with a current out DAC.
OFFSETTTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds I
PULSEturns off I
. Floats logic HIGH.
OFFSET
OFFSET
to I
. Logic LOW
OUT
DISABLETTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables
the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V
(minimizes the
REF
output current when the device is re-enabled). DISABLE floats logic HIGH.
V
+V
REF
S
Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset.
Positive Power Supply. Nominally +5 V, pin connections should be tied together externally.
GROUNDGround Reference. All grounds should be tied together externally.
–4–
REV. 0
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