ANALOG DEVICES AD9653 Service Manual

Analog-to-Digital Converter

AD9653

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

AVDD PDWN DRVDD

SENSE

Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

Data Sheet

FEATURES

1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced

range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Multichip sync and clock divider

Programmable output clock and data alignment

Standby mode

APPLICATIONS

Medical ultrasound and MRI
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment

GENERAL DESCRIPTION

The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital con­verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such

FUNCTIONAL BLOCK DIAGRAM

VIN+A
VIN–A

VIN+B
VIN–B

RBIAS

VREF

AGND
VIN+C

VIN–C

VIN+D
VIN–D

VCM

PIPELINE

ADC

PIPELINE

ADC

REF

SELECT

PIPELINE

ADC

PIPELINE

ADC

SERIAL PORT

INTERFACE

CSB

SDIO/OLM

16

DIGITAL

SERIALIZER

16

DIGITAL

SERIALIZER

1V

AD9653

16

DIGITAL

SERIALIZER

16

DIGITAL

SERIALIZER

CLOCK

MANAGEMENT

CLK+

SYNC

SCLK/DTP

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

CLK–

Figure 1.

as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).

The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.

D0+A
D0–A

D1+A
D1–A

D0+B
D0–B

D1+B
D1–B

FCO+
FCO–
D0+C
D0–C
D1+C
D1–C

D0+D
D0–D

D1+D
D1–D
DCO+
DCO–

10538-001

PRODUCT HIGHLIGHTS

1. Small Footprint.

Four ADCs are contained in a small, space-saving package.

2. Low power of 164 mW/channel at 125 MSPS with scalable

power options.

3. Pin compatible to the AD9253 14-bit quad and the AD9633

12-bit quad ADC.

4. Ease of Use.

A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.

5. User Flexibility.

The SPI control offers a wide range of flexible features to
meet specific system requirements.

responsi bility is as sumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD9653 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications .......................................................................... 5

Digital Specifications ................................................................... 7

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution ................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 14

V

= 1.0 V ................................................................................. 14

REF

V

= 1.3 V ................................................................................. 17

REF

Equivalent Circuits ......................................................................... 21

Theory of Operation ...................................................................... 22

Analog Input Considerations .................................................... 22

Voltage Reference ....................................................................... 23

Clock Input Considerations ...................................................... 25

Power Dissipation and Power-Down Mode ........................... 27

Digital Outputs and Timing ..................................................... 27

Output Test Modes ..................................................................... 30

Serial Port Interface (SPI) .............................................................. 31

Configuration Using the SPI ..................................................... 31

Hardware Interface ..................................................................... 32

Configuration Without the SPI ................................................ 32

SPI Accessible Features .............................................................. 32

Memory Map .................................................................................. 33

Reading the Memory Map Register Table ............................... 33

Memory Map Register Table ..................................................... 34

Memory Map Register Descriptions ........................................ 37

Applications Information .............................................................. 39

Design Guidelines ...................................................................... 39

Power and Ground Recommendations ................................... 39

Exposed Pad Thermal Heat Slug Recommendations ............ 39

VCM ............................................................................................. 39

Reference Decoupling ................................................................ 39

SPI Por t ........................................................................................ 39

Crosstalk Performance .............................................................. 39

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

5/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet AD9653

−

−

REF

REF

REF

AVDD

DRVDD

DRVDD

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V

Table 1.

Parameter1 Temperature Min Typ Max Unit

RESOLUTION 16 Bits
ACCURACY

No Missing Codes Full Guaranteed

Offset Error Full −0.49 −0.3 0.17 % FSR

Offset Matching Full −0.14 +0.2 0.39 % FSR

Gain Error Full −12.3 −5 2.37 % FSR

Gain Matching Full 1.0 1.1 5.8 % FSR

Differential Nonlinearity (DNL) Full

25°C ±0.7 LSB

Integral Nonlinearity (INL) Full

25°C ±3.5
TEMPERATURE DRIFT

Offset Error Full 3.5 ppm/°C
INTERNAL VOLTAGE REFERENCE

Output Voltage (1.0 V Mode) Full 0.98 1.0 1.01 V

Load Regulation at 1.0 mA (V

= 1.0 V) Full 2 mV

Input Resistance 25°C 7.5 kΩ
INPUT-REFERRED NOISE

V

= 1.0 V 25°C 2.7 LSB rms

ANALOG INPUTS

Differential Input Voltage (V

= 1.0 V) Full 2 V p-p
Common-Mode Voltage Full 0.9 V
Common-Mode Range 25°C 0.5 1.3 V
Differential Input Resistance 25°C 2.6 kΩ
Differential Input Capacitance 25°C 7 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V

2

I

Full 305 330 mA

I

(ANSI-644 Mode)2 Full 60 64 mA

I

(Reduced Range Mode)2 25°C 45

TOTAL POWER CONSUMPTION

DC Input Full 607 649 mW
Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) Full 657 708 mW
Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) 25°C 630 mW
Power-Down 25°C 2 mW
Standby3 Full 356 392 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on all four channels.

3

Can be controlled via the SPI.

= 1.0 V, DCS off, unless otherwise noted.

REF

0.77

0.95 LSB

7.26

8.18 LSB
LSB

mA

Rev. 0 | Page 3 of 40

AD9653 Data Sheet

INTERNAL VOLTAGE REFERENCE

REF

REF

REF

AVDD

25°C 1.8 V

DRVDD

25°C 1.8 V

AVDD

2

DRVDD

DRVDD

AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V

Table 2.

Parameter1 Temperature Min Ty p Max Unit

RESOLUTION 16 Bits
ACCURACY

No Missing Codes 25°C Guaranteed
Offset Error 25°C −0.3 % FSR
Offset Matching 25°C +0.2 % FSR
Gain Error 25°C −5 % FSR
Gain Matching 25°C 1.1 % FSR
Differential Nonlinearity (DNL) 25°C
Integral Nonlinearity (INL) 25°C

TEMPERATURE DRIFT

Offset Error 25°C 3.5 ppm/°C

Output Voltage (1.3 V Programmable Mode) 25°C 1.3 V
Load Regulation at 1.0 mA (V

= 1.3 V) 25°C 6.5 mV

Input Resistance 25°C 7.5 kΩ

INPUT-REFERRED NOISE

V

= 1.3 V 25°C 2.1 LSB rms

ANALOG INPUTS

Differential Input Voltage (V

= 1.3 V) 25°C 2.6 V p-p
Common-Mode Voltage 25°C 0.9 V
Common-Mode Range 25°C 0.6 1.3 V
Differential Input Resistance 25°C 2.6 kΩ
Differential Input Capacitance 25°C 7 pF

POWER SUPPLY

= 1.3 V; 0°C to 85°C, DCS off, unless otherwise noted.

REF

±0.8 LSB
±5.0 LSB

I

25°C 314 mA

I

(ANSI-644 Mode)2 25°C 60 mA

I

(Reduced Range Mode)2 25°C 45 mA

TOTAL POWER CONSUMPTION

DC Input 25°C 614 mW
Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) 25°C 673 mW
Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) 25°C 646 mW
Power-Down 25°C 2 mW
Standby3 25°C 371 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on all four channels.

3

Can be controlled via the SPI.

Rev. 0 | Page 4 of 40

Data Sheet AD9653

fIN = 128 MHz

25°C 73.9 dBFS

fIN = 200 MHz

25°C 71.5 dBFS

fIN = 70 MHz

Full

12.1

12.4 Bits

fIN = 128 MHz

25°C 11.9 Bits

fIN = 70 MHz

Full

−78

−89 dBc

IN1

IN2

87

AVDD

25°C 31 dB

ANALOG INPUT BANDWIDTH, FULL POWER

25°C 650 MHz

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V

Table 3.

Parameter1 Temperature Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 78 dBFS
fIN = 15 MHz 25°C 77.8 dBFS
fIN = 70 MHz Full 75.5 76.5 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 78 dBFS
fIN = 15 MHz 25°C 77.7 dBFS
fIN = 70 MHz Full 74.6 76.1 dBFS
fIN = 128 MHz 25°C 73.6 dBFS
fIN = 200 MHz 25°C 70.3 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.7 Bits
fIN = 15 MHz 25°C 12.6 Bits

= 1.0 V, DCS off, unless otherwise noted.

REF

fIN = 200 MHz 25°C 11.4 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 96 dBc
fIN = 15 MHz 25°C 93 dBc
fIN = 70 MHz Full 78 89 dBc
fIN = 128 MHz 25°C 87 dBc
fIN = 200 MHz 25°C 77 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −98 dBc
fIN = 15 MHz 25°C −93 dBc

fIN = 128 MHz 25°C −87 dBc
fIN = 200 MHz 25°C −77 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 9.7 MHz 25°C −96 dBc
fIN = 15 MHz 25°C −98
fIN = 70 MHz Full −85 −94 dBc
fIN = 128 MHz 25°C −89 dBc
fIN = 200 MHz 25°C −83 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS

f

= 70.5 MHz, f
CROSSTALK2 25°C
CROSSTALK (OVERRANGE CONDITION)3 25°C

= 72.5 MHz 25°C −90 dBc

91

dB
dB

POWER SUPPLY REJECTION RATIO (PSRR)4

dBc

DRVDD 25°C 79 dB

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is defined as the input being 3 dB above full scale.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitudes of the spur voltage over the pin voltage, expressed in decibels.

Rev. 0 | Page 5 of 40

AD9653 Data Sheet

IN1

IN2

AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V
noted.

Table 4.

Parameter1 Temperature Min Ty p Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 80 dBFS
fIN = 15 MHz 25°C 79.4 dBFS
fIN = 70 MHz 25°C 77.5 dBFS
fIN = 128 MHz 25°C 74.4 dBFS
fIN = 200 MHz 25°C 71.7 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 79.8 dBFS
fIN = 15 MHz 25°C 79.2 dBFS
fIN = 70 MHz 25°C 76.1 dBFS
fIN = 128 MHz 25°C 74 dBFS
fIN = 200 MHz 25°C 69.9 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 13 Bits
fIN = 15 MHz 25°C 12.9 Bits
fIN = 70 MHz 25°C 12.3 Bits
fIN = 128 MHz 25°C 12 Bits
fIN = 200 MHz 25°C 11.3 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 94 dBc
fIN = 15 MHz 25°C 94 dBc
fIN = 70 MHz 25°C 82 dBc
fIN = 128 MHz 25°C 86 dBc
fIN = 200 MHz 25°C 75 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −94 dBc
fIN = 15 MHz 25°C −94 dBc
fIN = 70 MHz 25°C −82 dBc
fIN = 128 MHz 25°C −87 dBc
fIN = 200 MHz 25°C −75 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 9.7 MHz 25°C −100 dBc
fIN = 15 MHz 25°C −99 dBc
fIN = 70 MHz 25°C −96 dBc
fIN = 128 MHz 25°C −86 dBc
fIN = 200 MHz 25°C −84 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS

f

= 70.5 MHz, f

= 72.5 MHz 25°C −90 dBc
CROSSTALK2 25°C 91 dB
CROSSTALK (OVERRANGE CONDITION)3 25°C 87 dB
POWER SUPPLY REJECTION RATIO (PSRR)4

AVDD 25°C 31 dB
DRVDD 25°C 79 dB

ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is defined as the input being 3 dB above full scale.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitudes of the spur voltage over the pin voltage, expressed in decibels.

= 1.3 V; 0 °C to 85°C, DCS off, unless otherwise

REF

Rev. 0 | Page 6 of 40

Data Sheet AD9653

Logic 1 Voltage

Full

1.2 AVDD + 0.2

V

Logic 0 Voltage

Full 0

0.8

V

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 5.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V

Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644

Logic Compliance LVDS
Differential Output Voltage (VOD) Full 290 345 400 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,

REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 160 200 230 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO/OLM pins sharing the same connection.

Rev. 0 | Page 7 of 40

AD9653 Data Sheet

1, 2

Fall Time (tF) (20% to 80%)

Full 300 ps

FCO

CPD

FCO

SAMPLE

DAT A

SAMPLE

SAMPLE

SAMPLE

FRAME

SAMPLE

SAMPLE

SAMPLE

DATA -MAX

DATA -MIN

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 6.

Parameter

CLOCK3

Input Clock Rate Full 20 1000 MHz
Conversion Rate Full 20 125 MSPS
Clock Pulse Width High (tEH) Full 4.00 ns
Clock Pulse Width Low (tEL) Full 4.00 ns

OUTPUT PARAMETERS3

Propagation Delay (tPD) Full 2.3 ns
Rise Time (tR) (20% to 80%) Full 300 ps

Temp Min Ty p Max Unit

FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t

) Full 1.5 2.3 3.1 ns

)4 Full t

)4 Full (t

) 4 Full (t

/16) − 300 (t
/16) − 300 (t

+ (t

/16) ns
/16) (t
/16) (t

/16) + 300 ps

/16) + 300 ps
Lane Delay (tLD) 90 ps
Data to Data Skew (t

− t

) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 250 ns
Wake-Up Time (Power-Down)5 25°C 375 μs
Pipeline Latency Full 16

APERTURE

Aperture Delay (tA) 25°C 1 ns
Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms
Out-of-Range Recovery Time 25°C 1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

t

/16 is based on the number of bits in two LVDS data lanes. t

SAMPLE

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

SAMPLE

= 1/fS.

Clock cycles

Clock cycles

Rev. 0 | Page 8 of 40

Data Sheet AD9653

SSYNC

HSYNC

CLK

HIGH

LOW

D0–A

D0+A
D1–A

D1+A

FCO–

BYTEWISE

MODE

FCO+

D0–A

D0+A
D1–A

D1+A

FCO–

DCO

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

10538-002

MSB

N – 17

D14

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

D12

N – 16

D11

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 17

D06

N – 17

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

D07

N – 16

D06

N – 16

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

MSB

N – 17

D13

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

MSB

N – 16

D13

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D14

N – 17

D12

N – 17

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D14

N – 16

D12

N – 16

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

t

A

t

DATA

t

LD

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

N + 1

TIMING SPECIFICATIONS

Table 7.

Parameter Description Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

SPI TIMING REQUIREMENTS See Figure 75

tDS Setup time between the data and the rising edge of SCLK 2 ns min
tDH Hold time between the data and the rising edge of SCLK 2 ns min
t

Period of the SCLK 40 ns min
tS Setup time between CSB and SCLK 2 ns min
tH Hold time between CSB and SCLK 2 ns min
t

SCLK pulse width high 10 ns min

t

SCLK pulse width low 10 ns min

t

Time required for the SDIO pin to switch from an input to an output relative to the

EN_SDIO

10 ns min

SCLK falling edge (not shown in Figure 75)

t

Time required for the SDIO pin to switch from an output to an input relative to the

DIS_SDIO

10 ns min

SCLK rising edge (not shown in Figure 75)

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.

Unit

Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

Rev. 0 | Page 9 of 40

AD9653 Data Sheet

D0–A

D0+A

D1–A

D1+A

FCO–

BYTEWISE

MODE

FCO+

D0–A

D0+A

D1–A

D1+A

FCO–

DCO

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

MSB

N – 17

D14

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

D12

N – 16

D11

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 17

D06

N – 17

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

D07

N – 16

D06

N – 16

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

MSB

N – 17

D13

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

MSB

N – 16

D13

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D14

N – 17

D12

N – 17

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D14

N – 16

D12

N – 16

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

t

A

t

DATA

t

LD

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N + 1

N

10538-003

D0–x

D0+x

FCO–

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

D14

N – 17

MSB

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17D9N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17

LSB

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

t

A

t

DATA

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

10538-004

SYNC

CLK+

t

HSYNC

t

SSYNC

10538-005

Figure 3. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode

Figure 4. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode

Figure 5. SYNC Input Timing Requirements

Rev. 0 | Page 10 of 40

Data Sheet AD9653

AVDD to AGND

−0.3 V to +2.0 V

CLK+, CLK− to AGND

−0.3 V to +2.0 V

REF

REF

JA

JB θJC

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating
Electrical

DRVDD to AGND −0.3 V to +2.0 V
Digital Outputs

−0.3 V to +2.0 V
(D0±x, D1±x, DCO+, DCO−, FCO+,
FCO−) to AGND

VIN+x, VIN−x to AGND −0.3 V to +2.0 V
SCLK/DTP, SDIO/OLM, CSB to AGND −0.3 V to +2.0 V
SYNC, PDWN to AGND −0.3 V to +2.0 V
RBIAS to AGND −0.3 V to +2.0 V
VREF, SENSE to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature

Range (Ambient, V

Operating Temperature

Range (Ambient, V

Maximum Junction

= 1.0 V)

= 1.3 V)

−40°C to +85°C

0°C to 85°C

150°C

Temperature

Lead Temperature

300°C

(Soldering, 10 sec)

Storage Temperature

−65°C to +150°C
Range (Ambient)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

Table 9. Thermal Resistance

Air Flow

Package Type

Velocity
(m/sec)

θ

1

θ

Unit

48-Lead LFCSP 0.0 23.7 7.8 7.1 °C/W

7 mm × 7 mm 1.0 20.0 N/A N/A °C/W
(CP-48-13) 2.5 18.7 N/A N/A °C/W

1

θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

ESD CAUTION

Rev. 0 | Page 11 of 40

AD9653 Data Sheet

21, 22

D1−B, D1+B

Channel B Digital Outputs.

35

VIN−A

ADC A Analog Input Complement.

36 VIN+A

ADC A Analog Input True.

SENSE

D

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+C
48

1

VIN+D

2

VIN–D

3

AVDD

4

AVDD

5

CLK–

6

CLK+

7

AVDD

8

RVDD

9

D1–D

10

D1+D

11

D0–D

12

D0+D

13

D1–C

PACKAGE PROV IDES THE ANALOG GROUND FOR THE PART.
THIS EXP OSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OP E RATION.

VIN–C

AVDD

AVDD

SYNC

47

46

45

44

AD9653

TOP VIEW

(Not to S cale)

17

16

14

15

D0–C

D0+C

D1+C

DCO–

VCM
43

18

DCO+

Figure 6. 48-Lead LFCSP Pin Configuration, Top View

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND,

Exposed Pad
1
2

VIN+D ADC D Analog Input True.

VIN−D ADC D Analog Input Complement.

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground for proper operation.

3, 4, 7, 34, 39, 45, 46 AVDD 1.8 V Analog Supply Pins.
5, 6
8, 29
9, 10

CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

DRVDD Digital Output Driver Supply.

D1−D, D1+D Channel D Digital Outputs.
11, 12 D0−D, D0+D Channel D Digital Outputs.
13, 14
15, 16
17, 18
19, 20

D1−C, D1+C Channel C Digital Outputs.

D0−C, D0+C Channel C Digital Outputs.

DCO−, DCO+ Data Clock Outputs.

FCO−, FCO+ Frame Clock Outputs.

VREF
42

19

FCO–

41

20

FCO+

AVDD

RBIAS

39

40

22

21

D1–B

D1+B

VIN+B

VIN–B

37

38

24

23

D0–B

D0+B

36

VIN+A
VIN–A

35

AVDD

34

PDWN

33
32

CSB
SDIO/OLM

31

SCLK/DTP

30

DRVDD

29
28

D0+A
D0–A

27

D1+A

26
25

D1–A

10538-006

23, 24

D0−B, D0+B Channel B Digital Outputs.
25, 26 D1−A, D1+A Channel A Digital Outputs.
27, 28 D0−A, D0+A Channel A Digital Outputs.
30
31
32
33

37
38 VIN−B ADC B Analog Input Complement.
40
41
42
43

SCLK/DTP SPI Clock Input/Digital Test Pattern.

SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.

CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.

PDWN Digital Input, 30 kΩ Internal Pull-Down.

VIN+B ADC B Analog Input True.

RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

SENSE Reference Mode Selection.

VREF Voltage Reference Input and Output.

VCM Analog Input Common-Mode Voltage.

PDWN high = power-down device.
PDWN low = run device, normal operation.

Rev. 0 | Page 12 of 40