ANALOG DEVICES AD9649 Service Manual

14-Bit, 20/40/65/80 MSPS,

A

V

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply SNR

74.3 dBFS at 9.7 MHz input

71.5 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input 80 dBc at 200 MHz input

Low power

45 mW at 20 MSPS

87 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.35 LSB Serial port control options

Offset binary, gray code, or twos complement data format

Integer 1, 2, or 4 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out (DCO) with programmable clock and data

alignment

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR

1.8 V Analog-to-Digital Converter AD9649

FUNCTIONAL BLOCK DIAGRAM

DD GND SDIO SCLK CSB

RBIAS

VCM

VIN+ VIN–

VREF

SENSE

REF

SELECT

CLK+ CLK–

DIVIDE BY

1, 2, 4

SPI

PROGRAMMING DATA

ADC

CORE

PDWN

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9649 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.

3. A standard serial port interface (SPI) supports various

product features and functions, such as data output formatting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes.

4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP

that is pin compatible with the AD9629 12-bit ADC and the AD9609 10-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

DRVDD

AD9649

MODE

CONTROLS

DFS MODE

OR

D13 (MSB)

CMOS

D0 (LSB)

OUTPUT BUFF E R

DCO

08539-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No

rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

AD9649

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9649

GENERAL DESCRIPTION

The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.

The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and

3.3 V CMOS levels are supported.

The AD9649 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Rev. 0 | Page 3 of 32

AD9649

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted.

Table 1.

AD9649-20/AD9649-40 AD9649-65 AD9649-80

Parameter Temp

RESOLUTION Full 14 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.40 +0.05 +0.50 −0.40 +0.05 +0.50 −0.40 +0.05 +0.50 % FSR Gain Error Differential Nonlinearity (DNL)

1

Full −1.5 −1.5 −1.5 % FSR

2

Full ±0.50 +0.55 ±0.65 LSB

25°C ±0.25 ±0.3 ±0.35 LSB Integral Nonlinearity (INL)

2

Full ±1.30 ±1.30 ±1.75 LSB

25°C ±0.50 ±0.50 ±0.60 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.984 0.996 1.008 0.984 0.996 1.008 0.984 0.996 1.008 V Load Regulation Error at 1.0 mA Full 2 2 2 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 0.98 0.98 0.98 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance

3

Full 6 6 6 pF

Input Common-Mode Voltage Full 0.9 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V

Supply Current

2

IAVDD

Full 25.0/31.3 27.3/33.7 41.0 44.0 47.0 50.0 mA

IDRVDD2 (1.8 V) Full 1.6/2.9 4.7 5.6 mA IDRVDD2 (3.3 V) Full 3.0/5.3 8.4 10.2 mA

POWER CONSUMPTION

DC Input Full 45.2/57.2 75.2 86.8 mW

Sine Wave Input2 (DRVDD = 1.8 V) Full 47.9/61.6 51.8/65.8 82.3 87.5 94.7 100 mW

Sine Wave Input2 (DRVDD = 3.3 V) Full 54.9/73.8 101.5 118.3 mW

Standby Power

4

Full 34/34 34 34 mW

Power-Down Power Full 0.5 0.5 0.5 mW

1

Measured with 1.0 V external reference.

2

Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and ground.

4

Standby power is measured with a dc input and the CLK+, CLK− active.

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 4 of 32

AD9649

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted.

Table 2.

1

Parameter

Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 74.7 74.5 74.3 dBFS fIN = 30.5 MHz 25°C 74.4 74.3 74.1 dBFS Full 73.1 73.6 dBFS fIN = 70 MHz 25°C 73.7 73.7 73.6 dBFS Full 72.7 dBFS fIN = 200 MHz 25°C 71.5 71.5 71.5 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 74.6 74.4 74.1 dBFS fIN = 30.5 MHz 25°C 74.3 74.2 74.0 dBFS Full 73.0 73.5 dBFS fIN = 70 MHz 25°C 73.6 73.6 73.5 dBFS Full 72.6 dBFS fIN = 200 MHz 25°C 70.0 70.0 70.0 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.0 12.0 12.0 Bits fIN = 30.5 MHz 25°C 12.0 12.0 12.0 Bits fIN = 70 MHz 25°C 11.9 11.9 11.9 Bits fIN = 200 MHz 25°C 11.3 11.3 11.3 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25°C −95 −95 −93 dBc fIN = 30.5 MHz 25°C −95 −95 −93 dBc Full −82 −83 dBc fIN = 70 MHz 25°C −94 −94 −92 dBc Full −82 dBc fIN = 200 MHz 25°C −80 −80 −80 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 94 94 93 dBc Full 82 83 dBc fIN = 70 MHz 25°C 93 93 92 dBc Full 82 dBc fIN = 200 MHz 25°C 80 80 80 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25°C −100 −100 −100 dBc fIN = 30.5 MHz 25°C −100 −100 −100 dBc Full −90 −90 dBc fIN = 70 MHz 25°C −100 −100 −100 dBc Full −90 dBc fIN = 200 MHz 25°C −95 −95 −95 dBc

TWO-TONE SFDR

fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc

ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

AD9649-20/AD9649-40 AD9649-65 AD9649-80

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 5 of 32

AD9649

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted.

Table 3.

AD9649-20/AD9649-40/AD9649-65/AD9649-80

Parameter Temp

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Internal Common-Mode Bias Full 0.9 V

Differential Input Voltage Full 0.2 3.6 V p-p

Input Voltage Range Full GND − 0.3 AVDD + 0.2 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 8 10 12 kΩ

Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −50 −75 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 30 kΩ

Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full 40 135 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 2 pF DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (IOH)

IOH = 50 μA Full 3.29 V IOH = 0.5 mA Full 3.25 V

Low Level Output Voltage (IOL)

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (IOH)

IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage (IOL)

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

1

Internal 30 kΩ pull-down.

2

Internal 30 kΩ pull-up.

Unit Min Typ Max

Rev. 0 | Page 6 of 32

AD9649

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted.

Table 4.

AD9649-20/AD9649-40 AD9649-65 AD9649-80

Parameter Temp

CLOCK INPUT PARAMETERS

Input Clock Rate Full 80/160 260 320 MHz Conversion Rate CLK Period, Divide-by-1 Mode (t

1

Full 3 20/40 3 65 3 80 MSPS

) Full

CLK

50/25

15.38 12.5 ns CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full DCO Propagation Delay (t DCO to Data Skew (t

SKEW

) Full 3

DCO

) Full 0.1

3

3 3

0.1

3 ns 3 ns

0.1 ns Pipeline Delay (Latency) Full 8 8 8 Cycles Wake-Up Time

2

Full 350 350 350 μs

Standby Full 600/400 300 260 ns

OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles

1

Conversion rate is the clock rate after the CLK divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

VIN

CLK+ CLK–

DCO

DATA

N – 1

t

A

N

N + 1

t

CH

t

CLK

t

DCO

t

SKEW

N – 8 N – 7 N – 6 N – 5 N – 4

t

PD

N + 2

N + 3

Figure 2. CMOS Output Data Timing

N + 4

N + 5

08539-002

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 7 of 32

AD9649

TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

SCLK pulse width high 10 ns

HIGH

t

SCLK pulse width low 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

10 ns

Rev. 0 | Page 8 of 32

AD9649

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND1 −0.3 V to +2.0 V DRVDD to AGND1 −0.3 V to +3.9 V VIN+, VIN− to AGND1 −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND1 −0.3 V to AVDD + 0.2 V VREF to AGND1 −0.3 V to AVDD + 0.2 V SENSE to AGND1 −0.3 V to AVDD + 0.2 V VCM to AGND1 −0.3 V to AVDD + 0.2 V RBIAS to AGND1 −0.3 V to AVDD + 0.2 V CSB to AGND1 −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND1 −0.3 V to DRVDD + 0.3 V SDIO/PDWN to AGND1 −0.3 V to DRVDD + 0.3 V MODE/OR to AGND1 −0.3 V to DRVDD + 0.3 V D0 through D13 to AGND1 DCO to AGND1

−0.3 V to DRVDD + 0.3 V

−0.3 V to DRVDD + 0.3 V Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C

1

AGND refers to the analog ground of the customer’s PCB.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip and must be soldered to the analog ground plane of the user’s PCB. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Package Type

32-Lead LFCSP 5 mm × 5 mm

1

Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Airflow Velocity (m/sec)

1, 2

1, 3

θ

JA

JC

1, 4

θ

JB

1,2

Ψ

Unit

JT

0 37.1 3.1 20.7 0.3 °C/W

1.0 32.4 0.5 °C/W

2.5 29.1 0.8 °C/W

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Ta b l e 7 , airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 9 of 32

AD9649

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RBIAS

AVDD 32

VCM

VIN–

AVDD

SENSE

VIN+ 31

30

VREF

29

28

27

26

25

14 D6

15

16 8

D7

D

24 AVDD 23 MODE/OR 22 DCO 21 D13 (MSB) 20 D12 19 D11 18 D10 17 D9

08539-003

1CLK+

PIN 1

2CLK–

INDICATOR

3AVDD 4CSB

AD9649

5SCLK/DFS

TOP VIEW

6SDIO/PDWN

(Not to Scale)

7D0 (LSB) 8D1

9

11

10

12

13

D2

D3

D4

D5

DRVDD

NOTES

1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND PLANE OF THE PCB TO ENS URE PROPER FUNCTI ONALITY AND M AX IMIZE THE HEAT DIS S IPATION, NOISE, AND M E CHANI CAL STRENGT H BE NEFITS.

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

0 (EP) GND

Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise,

and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for the ADC CORE Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS

SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.

DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN

SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.

Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.

See Tab le 14 for details. 7 to 12, 14 to 21

D0 (LSB) to

ADC Digital Outputs.

D13 (MSB) 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input in SPI Mode (MODE). Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100). Chip stand-by (SPI Register 0x08, Bits[7:5] = 101). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111). In non-SPI mode, the pin operates only as an out-of-range (OR) digital output. 25 VREF 1.0 V Voltage Reference Input/Output. See Table 10. 26 SENSE Reference Mode Selection. See Table 10. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs.

Rev. 0 | Page 10 of 32

ANALOG DEVICES AD9649 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS