ANALOG DEVICES AD9648 Service Manual

14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual

AD9648

VIN+A
VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B
VIN+B

ORA

D0A

D13A

DCOA

DRVDD

ORB

D13B

D0B

DCOB

SDIOAGNDAVDD SCLK

SPI

PROGRAMMI NG DATA

MUX OPTION

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DCS

DUTY CYCLE

STABILIZER

SYNC

DIVIDE

1 TO 8

OEB

CSB

REF

SELECT

ADC

CMOS/LVDS

OUTPUT BUFFER

ADC

CMOS/LVDS

OUTPUT BUFFER

AD9648

09975-001

NOTES

1. PIN NAMES ARE F OR THE CMOS P IN CONFIG URATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS @ 70 MHz
SFDR = 91 dBc @ 70 MHz
Low power: 78 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options

Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data

alignment

Analog-to-Digital Converter

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

Communications
Diversity radio systems
Multimode digital receivers

GSM, EDGE, W-CDMA, LT E,

CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR

1

This product is protected by a U.S patent.

Rev.

0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9648

power supply and features a separate digital output
driver supply to accommodate 1.8 V CMOS or LVDS
logic families.

2. The patented sample-and-hold circuit maintains

excellent performance for input frequencies up to
200 MHz and is designed for low cost, low power, and
ease of use.

3. A standard serial port interface supports various

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©

product features and functions, such as data output
formatting, internal clock divider, power-down,
DCO/data timing and offset adjustments.

4. The AD9648 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9650/

AD9269/AD9268 16-bit ADC, the AD9258 14-bit

ADC, the AD9628/AD9231 12-bit ADCs, and the
AD9608/AD9204 10-bit ADCs, enabling a simple
migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.

1

operates from a single 1.8 V analog

2011 Analog Devices, Inc. All rights reserved.

www.analog.com

AD9648

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

DC Specifications ........................................................................... 4

AC Specifications ........................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications ................................................................ 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 12

Thermal Characteristics ............................................................ 12

ESD Caution ................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 19

AD9648-125 ................................................................................ 20

AD9648-105 ................................................................................ 22

Equivalent Circuits ......................................................................... 24

Theory of Operation ...................................................................... 25

ADC Architecture ...................................................................... 25

Analog Input Considerations .................................................... 25

Voltage Reference ....................................................................... 27

Clock Input Considerations ...................................................... 28

Channel/Chip Synchronization ................................................ 30

Power Dissipation and Standby Mode .................................... 30

Digital Outputs ........................................................................... 31

Timing ......................................................................................... 31

Built-In Self-Test (BIST) and Output Test .................................. 32

Built-In Self-Test (BIST) ............................................................ 32

Output Test Modes ..................................................................... 32

Serial Port Interface (SPI) .............................................................. 33

Configuration Using the SPI ..................................................... 33

Hardware Interface ..................................................................... 34

Configuration Without the SPI ................................................ 34

SPI Accessible Features .............................................................. 34

Memory Map .................................................................................. 35

Reading the Memory Map Register Table ............................... 35

Memory Map Register Table ..................................................... 36

Memory Map Register Descriptions ........................................ 39

Applications Information .............................................................. 41

Design Guidelines ...................................................................... 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD9648

GENERAL DESCRIPTION

The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit,
105 MSPS/125 MSPS analog-to-digital converter (ADC). It
features a high performance sample-and-hold circuit and on­chip voltage reference.

The product uses multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
125 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.

The digital output data is presented in offset binary, Gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. Output logic levels of 1.8 V CMOS or LVDS are supported.
Output data can also be multiplexed onto a single output bus.

The AD9648 is available in a 64-lead RoHS compliant LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C). This product is protected by a U.S. patent.

Rev. 0 | Page 3 of 44

AD9648

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.

Table 1.

AD9648-105 AD9648-125
Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −0.8 −0.3 +0.2 −0.8 −0.3 +0.2 % FSR
Gain Error Full −4.20 ±1.3 +4.2 −5.1 ±1.3 +5.1 % FSR
Differential Nonlinearity (DNL)1 Full −0.5 +1.2 −0.5 +1.2 LSB

25°C ±0.5 ±0.5 LSB

Integral Nonlinearity (INL)1 Full −2.3 +2.3 −2.3 +2.3 LSB
25°C ±1.0 ±1.0 LSB
MATCHING CHARACTERISTIC

Offset Error Full ±0.01

Gain Error Full ±0.5 ±4.0 ±0.5 ±4.0 % FSR
TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error Full ±50 ±50 ppm/°C
INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V

Load Regulation Error at 1.0 mA Full 2 2 mV
INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.98 0.98 LSB rms
ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p

Input Capacitance2 Full 5 5 pF

Input Resistance (Differential) Full 7.5 7.5 kΩ

Input Common-Mode Voltage Full 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V
POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

I

Full 81 86 95 100 mA

AVDD

I

(1.8 V CMOS)1 Full 19.2 22.5 mA

DRVDD

I

(1.8 V LVDS)1 Full 63.5 65.0 mA

DRVDD

±0.58

±0.01 ±0.58 % FSR

Rev. 0 | Page 4 of 44

AD9648

69.6

70.3

25°C 12.0

11.9 Bits

Full

dBc

AD9648-105 AD9648-125
Parameter Temp Min Typ Max Min Typ Max Unit

POWER CONSUMPTION

DC Input Full 135.4 155.5 mW
Sine Wave Input (DRVDD = 1.8 V CMOS

Output Mode)

Sine Wave Input (DRVDD = 1.8 V LVDS

Output Mode)
Standby Power3 Full 108 120 mW
Power-Down Power Full 2.0 2.0 mW

1

Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.

Table 2.

AD9648-105 AD9648-125
Parameter1 Temp Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 9.7 MHz 25°C 75.4 75.0 dBFS
fIN = 30.5 MHz 25°C 75.2 74.7 dBFS
fIN = 70 MHz 25°C 74.8 74.5 dBFS
Full 73.8 73.0 dBFS
fIN = 100 MHz
fIN = 200 MHz 25°C 71.0 71.5 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 74.3 73.9 dBFS
fIN = 30.5 MHz 25°C 74.0 73.4 dBFS
fIN = 70 MHz 25°C 73.4 73.3 dBFS
Full 73.0 72.8 dBFS
fIN = 100 MHz 25°C 72.8 72.8 dBFS
fIN = 200 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 200 MHz

Full 172.3 181.3 202.5 211.5 mW

Full 180.4 189.4 211.5 220.5 mW

25°C 73.8 73.9 dBFS

25°C

12.0

11.9

dBFS

Bits

25°C
25°C
25°C

25°C
25°C
25°C

−98 −96

−90 −90

−93 −91

11.8

11.8

11.3

11.8

11.8

11.4

Bits
Bits
Bits

dBc
dBc
dBc

−86 −82
25°C
25°C

−92 −90

−81 −84

dBc
dBc

Rev. 0 | Page 5 of 44

AD9648

AD9648-105 AD9648-125
Parameter1 Temp Min Typ Max Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 200 MHz

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 200 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

25°C
25°C
25°C
Full
25°C
25°C

25°C
25°C
25°C
Full
25°C
25°C

25°C
Full
25°C

98 96
90 90
93 91
86 82
92 90
81 84

−98 −97

−96 −97

−96 −97

−91 −90

−92 −92

−90 −90

dBc
dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc
dBc

84 84

−95 −95
650 650

dBc
dB
MHz

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS dierential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.

Table 3.

AD9628-105/125
Parameter Temp Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Internal Common-Mode Bias Full 0.9 V

Differential Input Voltage Full 0.3 3.6 V p-p

Input Voltage Range Full AGND - 0.3 AVDD + 0.2 V

Input Common-Mode Range Full 0.9 1.4 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full −10 +10 μA

Input Capacitance Full 4 pF

Input Resistance Full 8 10 12 kΩ
LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V

Low Level Input Voltage Full 0 0.6 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full 40 132 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 2 pF

Rev. 0 | Page 6 of 44

AD9648

AD9628-105/125
Parameter Temp Min Typ Max Unit

LOGIC INPUT (SCLK/DFS/SYNC)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −92 −135 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUT/OUTPUT (SDIO/DCS)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 38 128 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −90 −134 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 V
IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V
IOL = 50 μA Full 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV
Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V
Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV
Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

Rev. 0 | Page 7 of 44

AD9648

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.

Table 4.

AD9648-105 AD9648-125
Parameter Temp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 1000 1000 MHz

Conversion Rate1

DCS Enabled Full 20 105 20 125 MSPS

DCS Disabled Full 10 105 10 125 MSPS
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (tCH) Full 4.76 4 ns
Aperture Delay (tA) Full 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 ps rms

DATA OUTPUT PARAMETERS

CMOS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns
DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

LVDS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 2.4

DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles
LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 16/16.5 Cycles
Wake-Up Time (Power Down)3 Full 350 350 µs
Wake-Up Time (Standby) Full 250 250 ns
Out-of-Range Recovery Time Full 2 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18).

3

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 9.52 8 ns

CLK

)2 Full 2.0 3.1 4.4 2.0 3.1 4.4 ns

DCO

) Full −1.2

)2 Full

DCO

2.4 2.4

−0.1

+1.0 −1.2

−0.1

+1.0 ns

2.4 ns
ns

) Full −0.20 +0.03 +0.25 −0.20 +0.03 +0.25 ns

Rev. 0 | Page 8 of 44

AD9648

SSYNC

HIGH

t

PD

t

SKEW

t

CH

t

DCO

t

CLK

N – 16N – 17

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

N – 15 N – 14 N – 13 N – 12

VIN

CLK+
CLK–

CH A/CH B D ATA

DCOA/DCOB

t

A

09975-002

TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit

SYNC TIMING
REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING
REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min
tDH Hold time between the data and the rising edge of SCLK 2 ns min
t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min
tH Hold time between CSB and SCLK 2 ns min
t

SCLK pulse width high 10 ns min

t

SCLK pulse width low 10 ns min

LOW

t

Time required for the SDIO pin to switch from an input to an output relative

EN_SDIO

10 ns min

to the SCLK falling edge

t

Time required for the SDIO pin to switch from an output to an input relative

DIS_SDIO

10 ns min

to the SCLK rising edge

Timing Diagrams

Unit

Figure 2. CMOS Default Output Mode Data Output Timing

Rev. 0 | Page 9 of 44

AD9648

t

PD

t

SKEW

t

CH

t

DCO

t

CLK

CH A

N – 16

CH B

N – 15

CH A

N – 14

CH B

N – 13

CH A

N – 12

CH B

N – 11

CH A

N – 10

CH B
N – 9

CH A
N – 8

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

VIN

CLK+
CLK–

CH A DATA

DCOA/DCOB

t

A

CH B DATA

CH B

N – 16

CH A

N – 15

CH B

N – 14

CH A

N – 13

CH B

N – 12

CH A

N – 11

CH B

N – 10

CH A
N – 9

CH B
N – 8

09975-003

t

PD

t

SKEW

t

CH

t

DCO

t

CLK

CH A

N – 12

CH B

N – 12

CH A

N – 11

CH B

N – 11

CH A

N – 10

CH B

N – 10

CH A
N – 9

CH B
N – 9

CH A
N – 8

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

VIN

CLK+

CLK–

DCO+
DCO–

D0+ (LSB)

PARALLEL

INTERLEAVED

MODE

D0– (LSB)

D13+ (MSB)
D13– (MSB)

t

A

CH A

N – 12

CH B

N – 12

CH A

N – 11

CH B

N – 11

CH A

N – 10

CH B

N – 10

CH A
N – 9

CH B
N – 9

CH A
N – 8

CH A0
N – 12

CH A1
N – 12

CH A0
N – 11

CH A1
N – 11

CH A0
N – 10

CH A1
N – 10

CH A0

N – 9

CH A1

N – 9

CH A0

N – 8

D1+/0+ (L S B)

CHANNEL

MULTIPLEXED

MODE

CHANNEL A

D1–/D0– (LSB)

D13+/D12+ (MS B)
D13–/D12– (MSB)

CH A12

N – 12

CH A13

N – 12

CH A12

N – 11

CH A13

N – 11

CH A12

N – 10

CH A13

N – 10

CH A12

N – 9

CH A13

N – 9

CH A12

N – 8

CH B0
N – 12

CH B1
N – 12

CH B0
N – 11

CH B1
N – 11

CH B0
N – 10

CH B1
N – 10

CH B0

N – 9

CH B1

N – 9

CH B0

N – 8

D1+/D0+ (L S B)

CHANNEL

MULTIPLEXED

MODE

CHANNEL B

D1–/D0– (LSB)

D13+/D12+ (MS B)
D13–/D12– (MSB)

CH B12

N – 12

CH B13

N – 12

CH B12

N – 11

CH B13

N – 11

CH B12

N – 10

CH B13

N – 10

CH A12

N – 9

CH A13

N – 9

CH A12

N – 8

09975-004

Figure 3. CMOS Interleaved Output Mode Data Output Timing

Figure 4. LVDS Modes for Data Output Timing

Rev. 0 | Page 10 of 44

AD9648

SYNC

CLK+

t

HSYNC

t

SSYNC

09975-005

Figure 5. SYNC Input Timing Requirements

Rev. 0 | Page 11 of 44

AD9648

Ψ

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

1

AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
RBIAS to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V
SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V
OEB −0.3 V to DRVDD + 0.2 V
PDWN −0.3 V to DRVDD + 0.2 V
D0A/D0B through D13A/D13B to

AGND

DCOA/DCOB to AGND

−0.3 V to DRVDD + 0.2 V

−0.3 V to DRVDD + 0.2 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

1

The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +

0.2 V but should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.

Table 7. Thermal Resistance

Airflow
Velocity

Package Type

64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 22.3 1.4 N/A 0.1 °C/W

1.0 19.5 N/A 11.8 0.2 °C/W

2.5 17.5 N/A N/A 0.2 °C/W

1, 2

JA

θ

1, 3

JC

θ

1, 4

JB

1,2

JT

Unit

Typ i c a l θJA is specified for a 4-layer PCB with a solid ground
plane. As shown Table 7, airflow improves heat dissipation,
which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and
power planes reduces θ

.

JA

ESD CAUTION

Rev. 0 | Page 12 of 44

AD9648

PIN 1
INDICATOR

171819202122232425262728293031

32

D10B

D11B

DRVDD

D12B

D13B (MSB)

ORB

DCOB

DCOA

NC

NC

D0A (LSB)

DRVDD

D1A

D2A

D3A

D4A

646362616059585756555453525150

49

AVDD

AVDD

VIN+B

VIN–B

AVDD

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

AVDD

VIN–A

VIN+A

AVDD

AVDD

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16

CLK+
CLK–

SYNC

NC
NC

D0B (LSB)

D1B
D2B
D3B

DRVDD

D4B
D5B
D6B
D7B
D8B
D9B

PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

AD9648

PARALLEL CMOS

TOP VIEW

(Not to S cale)

NOTES

1. NC = NO CO NNE CT. DO NO T CONNECT TO THI S P IN.

2. T HE E X P OSED THERM AL PAD ON THE BOTTO M OF THE P ACKAGE PROVIDES

THE ANALO G GROUND F OR THE PART . THIS E X P OSED PAD MUST BE
CONNECTED TO GRO UND FOR PROP E R OPERATI ON.

09975-006

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Typ e Description

ADC Power Supplies
10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,

59, 60, 63, 64
4, 5, 25, 26 NC No Connect. Do not connect to these pins.
0 AGND,

ADC Analog
51 VIN+A Input Differential Analog Input Pin (+) for Channel A.
52 VIN−A Input Differential Analog Input Pin (−) for Channel A.
62 VIN+B Input Differential Analog Input Pin (+) for Channel B.
61 VIN−B Input Differential Analog Input Pin (−) for Channel B.
55 VREF Input/Output Voltage Reference Input/Output.
56 SENSE Input Reference Mode Selection.
58 RBIAS Input/Output External Reference Bias Resistor.
57 VCM Output Common-Mode Level Bias Output for Analog Inputs.
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.

AVDD Supply Analog Power Supply (1.8 V Nominal).

Ground The exposed thermal pad on the bottom of the package provides the analog

Exposed Pad

ground for the part. This exposed pad must be connected to ground for proper
operation.

Digital Input
3 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. 0 | Page 13 of 44

AD9648

Pin No. Mnemonic Typ e Description

Digital Outputs
27 D0A (LSB) Output Channel A CMOS Output Data.
29 D1A Output Channel A CMOS Output Data.
30 D2A Output Channel A CMOS Output Data.
31 D3A Output Channel A CMOS Output Data.
32 D4A Output Channel A CMOS Output Data.
33 D5A Output Channel A CMOS Output Data.
34 D6A Output Channel A CMOS Output Data.
35 D7A Output Channel A CMOS Output Data.
36 D8A Output Channel A CMOS Output Data.
38 D9A Output Channel A CMOS Output Data.
39 D10A Output Channel A CMOS Output Data.
40 D11A Output Channel A CMOS Output Data.
41 D12A Output Channel A CMOS Output Data.
42 D13A (MSB) Output Channel A CMOS Output Data.
43 ORA Output Channel A Overrange Output.
6 D0B (LSB) Output Channel B CMOS Output Data.
7 D1B Output Channel B CMOS Output Data.
8 D2B Output Channel B CMOS Output Data.
9 D3B Output Channel B CMOS Output Data.
11 D4B Output Channel B CMOS Output Data.
12 D5B Output Channel B CMOS Output Data.
13 D6B Output Channel B CMOS Output Data.
14 D7B Output Channel B CMOS Output Data.
15 D8B Output Channel B CMOS Output Data.
16 D9B Output Channel B CMOS Output Data.
17 D10B Output Channel B CMOS Output Data.
18 D11B Output Channel B CMOS Output Data.
20 D12B Output Channel B CMOS Output Data.
21 D13B (MSB) Output Channel B CMOS Output Data.
22 ORB Output Channel B Overrange Output
24 DCOA Output Channel A Data Clock Output.
23 DCOB Output Channel B Data Clock Output.
SPI Control
45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46 CSB Input SPI Chip Select (Active Low).
ADC Configuration
47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.
48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured

as power-down or standby.

Rev. 0 | Page 14 of 44