ANALOG DEVICES AD9643 Service Manual

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V

V

A

V

Dual Analog-to-Digital Converter (

Data Sheet

FEATURES

SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS

−151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS

Total power consumption: 785 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal ADC voltage reference Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes User-configurable, built-in self-test (BIST) capability

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G)

TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

GENERAL DESCRIPTION

The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The ADC output data is routed directly to the two external 14-bit LVDS output ports and formatted as either interleaved or channel multiplexed.

Flexible power-down options allow significant power savings, when desired.

ADC)

AD9643

FUNCTIONAL BLOCK DIAGRAM

DD AGND DRVDD

VIN+A

VIN–A

VCM

IN+B

VIN–B

NOTES

1. THE D0± TO D13± PI NS REPRESENT BOTH THE CHANNE L A

AD9643

REFERENCE

SCLK SDIO CSB CLK+ CLK– SYNC

AND CHANNEL B LVDS OUTPUT DATA.

Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

The AD9643 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.

2. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating LVDS outputs.

3. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 400 MHz.

4. SYNC input allows synchronization of multiple devices.

5. 3-pin, 1.8 V SPI port for register programming and register

readback.

6. Pin compatibility with the AD9613, allowing a simple

migration down from 14 bits to 12 bits. This part is also pin compatible with the AD6649 and the AD6643.

PIPELINE

14-BIT

ADC

PIPELINE

14-BIT

ADC

SERIAL PORT

14

PARALLEL

14

Figure 1.

DDR LVDS

AND

DRIVERS

1TO 8

CLOCK

DIVIDER

D0±

D13±

DCO±

OR±

OEB

PDWN

. . . . .

09636-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9643 Data Sheet

REVISION HISTORY

9/11—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Table 2, .......................................................................... 4

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 8

Changes to Table 8.......................................................................... 12

Changes to Table 9.......................................................................... 14

Changes to Typical Performance Characterisitics Section........ 16

Added ADC Overrange (OR) Section ......................................... 27

Changes to Channel/Chip Synchronization Section ................. 28

Changes to Reading the Memory Map Register Table

Section.............................................................................................. 31

Changes to Table 14........................................................................ 32

Changes to Memory Map Resgister Description Section ......... 34

5/11—Rev. 0 to Rev. A

Changes to Table 2, Worst Other (Harmonic or Spur)

Max Values......................................................................................... 4

4/11—Revision 0: Initial Version

Rev. B | Page 2 of 36

Data Sheet AD9643

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, unless otherwise noted.

Table 1.

AD9643-170 AD9643-210 AD9643-250

Parameter Temperature

Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±10 ±10 ±10 mV Gain Error Full +2/−6 +3/−5 ±4 %FSR Differential Nonlinearity (DNL) Full ±0.75 ±0.75 ±0.75 LSB 25°C ±0.25 ±0.25 ±0.25 LSB Integral Nonlinearity (INL)1 Full ±1.8 ±2 ±3.5 LSB 25°C ±1.5 ±1.5 ±1.5 LSB

MATCHING CHARACTERISTIC

Offset Error Full ±13 ±13 ±13 mV Gain Error Full ±2.5/

+3.5

−2/

−2.5/

+3.5

TEMPERATURE DRIFT

Offset Error Full ±5 ±5 ±5 ppm/°C Gain Error Full ±70 ±80 ±100 ppm/°C

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.33 1.33 1.33 LSB rms

ANALOG INPUT

Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

I

Full 196 250 217 265 256 275 mA

AVDD

1

I

Full 145 160 160 185 180 210 mA

DRVDD

POWER CONSUMPTION

Sine Wave Input (DRVDD = 1.8 V) Full 614 680 785 mW Standby Power4 Full 90 90 90 mW Power-Down Power Full 10 10 10 mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and its complement.

3

Input resistance refers to the effective resistance between one differential input pin and its complement.

4

Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).

%FSR

Rev. B | Page 3 of 36

AD9643 Data Sheet

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted.

Table 2.

AD9643-170 AD9643-210 AD9643-250 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 30 MHz 25°C 72.2 72.2 72.0 dBFS fIN = 90 MHz 25°C 72.0 72.0 71.7 dBFS

fIN = 140 MHz

fIN = 185 MHz

fIN = 220 MHz 25°C 71.1 70.9 70.5 dBFS

SIGNAL-TO-NOISE AND DISTORTION

(SINAD) fIN = 30 MHz 25°C 71.2 71.2 71.0 dBFS fIN = 90 MHz 25°C 71.0 71.0 70.7 dBFS Full 70.4 69.9 dBFS fIN = 140 MHz 25°C 70.8 70.6 70.4 dBFS

fIN = 185 MHz

fIN = 220 MHz 25°C 70.1 69.9 69.5 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 30 MHz 25°C 11.5 11.5 11.5 Bits fIN = 90 MHz 25°C 11.5 11.5 11.5 Bits fIN = 140 MHz 25°C 11.5 11.5 11.4 Bits

fIN = 185 MHz fIN = 220 MHz 25°C 11.4 11.3 11.3 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 30 MHz 25°C −95 −90 −90 dBc fIN = 90 MHz 25°C −92 −90 −88 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −88 −88 −86 dBc fIN = 185 MHz 25°C −83 −87 −85 dBc Full −80 dBc fIN = 220 MHz 25°C −83 −85 −85 dBc

SPURIOUS-FREE DYNAMIC RANGE

(SFDR) fIN = 30 MHz 25°C 95 90 90 dBc fIN = 90 MHz 25°C 92 90 88 dBc Full 78 80 dBc fIN = 140 MHz 25°C 88 88 86 dBc fIN = 185 MHz 25°C 83 87 85 dBc Full 80 dBc fIN = 220 MHz 25°C 83 85 85 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 30 MHz 25°C −98 −95 −94 dBc fIN = 90 MHz 25°C −97 −95 −93 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −97 −93 −92 dBc fIN = 185 MHz 25°C −96 −92 −92 dBc Full −80 dBc fIN = 220 MHz 25°C −94 −90 −88 dBc

TWO-TONE SFDR

fIN = 184.12 MHz (−7 dBFS ), 187.12

MHz (−7 dBFS )

Full 70.4 69.9 dBFS

25°C 71.8 71.6 71.4 dBFS

25°C 71.4 71.2 70.9 dBFS

Full 68.8 dBFS

25°C 70.4 70.2 69.9 dBFS

Full 67.5 dBFS

25°C 11.4 11.4 11.3 Bits

25°C 88 88 88 dBc

Rev. B | Page 4 of 36

Data Sheet AD9643

AD9643-170 AD9643-210 AD9643-250 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit

CROSSTALK2 Full 95 95 95 dB FULL POWER BANDWIDTH3 25°C 400 400 400 MHz NOISE BANDWIDTH4 25°C 1000 1000 1000 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

3

Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.

4

Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally.

Rev. B | Page 5 of 36

AD9643 Data Sheet

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted.

Table 3.

Parameter Te mp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Full −10 +22 µA Low Level Input Current Full −22 −10 µA Input Capacitance Full Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −80 −45 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK)2

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO)1

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)2

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

CMOS/LVDS/LVPECL Full 0.9 V Full 0.3 3.6 V p-p Full AGND AVDD V Full 0.9 1.4 V

4

pF

Rev. B | Page 6 of 36

Data Sheet AD9643

Parameter Te mp Min Typ Max Unit DIGITAL OUTPUTS

LVDS Data and OR Outputs

Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS),

ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS),

Reduced Swing Mode

1

Pull-up.

2

Pull-down.

Full 1.15 1.22 1.35 V

Rev. B | Page 7 of 36

AD9643 Data Sheet

SWITCHING SPECIFICATIONS

Table 4.

AD9643-170 AD9643-210 AD9643-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 40 170 40 210 40 250 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through

Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS

LVDS Mode

Data Propagation Delay (tPD) Full DCO Propagation Delay (t DCO-to-Data Skew (t

SKEW

Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 10 µs Wake-Up Time (from Power-Down) Full 250 250 250 µs Out-of-Range Recovery Time Full 3 3 3 Cycles

1

Conversion rate is the clock rate after the divider.

) Full 5.8 4.8 4 ns

CLK

Full 0.8

) Full

DCO

4.8 4.8 4.8 ns

5.5 5.5 5.5 ns

0.8

ns

) Full 0.3 0.7 1.1 0.3 0.7 1.1 0.3 0.7 1.1 ns

Rev. B | Page 8 of 36

Data Sheet AD9643

TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SYNC to the rising edge of CLK setup time 0.3 ns

SSYNC

t

SYNC to the rising edge of CLK hold time 0.4 ns

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

Minimum period that SCLK should be in a logic high state 10 ns

HIGH

t

Minimum period that SCLK should be in a logic low state 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

10 ns

Rev. B | Page 9 of 36

AD9643 Data Sheet

Timing Diagrams

t

A

t

N

DCO

PD

t

CLK

CH A

N – 10

CH A

N – 10

t

SKEW

N + 1

CH B

N – 10

CH B

N – 10

CH A N – 9

N + 2

CH B N – 9

CH A N – 8

N + 3

CH B N – 8

CH A N – 7

N + 4

CH B N – 7

CH A N – 6

N + 5

PARALLEL INTERLEAVED

CHANNEL A AND

CHANNEL B

VIN

CLK+

CLK–

DCO–

DCO+

D0±

(LSB)

D13±

(MSB)

N – 1

t

CH

. . .

CHANNEL MUL TIPL EXED

(EVEN/O DD) MO DE

CHANNEL A

CHANNEL MUL TIPL EXED

(EVEN/O DD) MO DE

CHANNEL B

D0±/D1±

(LSB)

D12±/D13±

(MSB)

D0±/D1±

(LSB)

D12±/D13±

(MSB)

CH A0

CH A1

CH A0

CH A1

CH A0

CH A1

CH A0

CH A1

N – 10

CH B0 N – 10

N – 10

CH A13

N – 10

CH B1 N – 10

CH B13

N – 10

. . .

CH A12

. . .

CH B12

N – 9

CH A12

N – 9

CH B0

N – 9

CH B12

N – 9

CH A13

N – 9

CH B1

N – 9

CH B13

N – 9

N – 8

CH A12

N – 8

CH B0

N – 8

CH B12

N – 8

CH A13

N – 8

CH B1

N – 8

CH B13

N – 8

N – 7

CH A12

N – 7

CH B0

N – 7

CH B12

N – 7

CH A13

CH B13

N – 7

CH B1

N – 7

CH A0

N – 6

CH A12

N – 6

CH B0

N – 6

CH B12

N – 6

09636-002

Figure 2. LVDS Modes for Data Output Timing

CLK+

SYNC

t

SSYNC

t

HSYNC

09636-003

Figure 3. SYNC Timing Inputs

Rev. B | Page 10 of 36

Data Sheet AD9643

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V SDIO to AGND −0.3 V to DRVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to DRVDD + 0.3 V OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V

D0−/D0+ Through D13−/D13+

−0.3 V to DRVDD + 0.3 V

to AGND

DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +125°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. This increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Veloc ity

Packa ge Type

64-Lead LFCSP

9 mm × 9 mm (CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 26.8 1.14 10.4 °C/W

1.0 21.6 °C/W

2.0 20.2 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Ta b le 7 , airflow increases heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. B | Page 11 of 36

ANALOG DEVICES AD9643 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION