ANALOG DEVICES AD9641 Service Manual

14-Bit, 80 MSPS/155 MSPS, 1.8 V

A

Serial Output Analog-to-Digital Converter (ADC)

FEATURES

JESD204A coded serial digital outputs SNR = 73.7 dBFS at 70 MHz/80 MSPS SNR = 72.8 dBFS at 70 MHz and 155 MSPS SFDR = 94 dBc at 70 MHz and 80 MSPS SFDR = 90 dBc at 70 MHz and 155 MSPS Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS

1.8 V supply operation Integer 1-to-8 input clock divider IF sampling frequencies to 250 MHz

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS Programmable internal ADC voltage reference Flexible analog input range: 1.4 V p-p to 2.1 V p-p ADC clock duty cycle stabilizer (DCS) Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

GENERAL DESCRIPTION

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The

AD9641 is designed to support communications applications

where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9641

FUNCTIONAL BLOCK DIAGRAM

VDD

AD9641

VIN+

VIN–

VCM

REFERENCE

MULTICHIP

AGND

The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.

The flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. An on-chip PLL allows users to provide a single ADC

sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock.

2. The configurable JESD204A output block coded data rate

supports up to 1.6 Gbps.

3. A proprietary differential input maintains excellent SNR

performance for input frequencies of up to 250 MHz.

4. Operation is from a single 1.8 V power supply.

5. The standard serial port interface (SPI) supports various

product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

SDIO SCLK CSB

PROGRAMMING DATA

ADC

SYNC

SPI

DATA RATE

MULTIPLIER

DUTY CYCLE STABILIZER

DIVIDE-BY-1

TO

DIVIDE-BY-8

PDWN DRGND

Figure 1.

DRVDD

ENCODER,

DATA SERIALIZ ER,

AND CML DRIVERS

DOUT+

DOUT–

DSYNC+

DSYNC–

CLK+

CLK–

09210-001

AD9641

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Added Model -155......................................................... Throughout

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 4............................................................................ 6

Changes to Figure 11 to Figure 14 Captions............................... 11

Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13

Changes to Clock Input Considerations Section........................ 19

Changes to Digital Outputs and Timing Section ....................... 23

Moved Figure 65 and Figure 66 .................................................... 23

Added Figure 68.............................................................................. 24

Changes to Output Test Modes Section ...................................... 25

Changes to SPI Accessible Features Section ............................... 28

Changes to Addr (Hex) 0x02, Table 17........................................ 29

Changes to Ordering Guide.......................................................... 36

7/10—Revision 0: Initial Version

Rev. A | Page 2 of 36

AD9641

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS dierential input, DCS enabled, unless otherwise noted.

Table 1.

AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±2 ±10 ±2 ±11 mV Gain Error Full −7 −2.5 +1 −7.5 −2.5 +1 % FSR Differential Nonlinearity (DNL)1 Full ±0.55 ±0.55 LSB

25°C ±0.3 ±0.3 LSB

Integral Nonlinearity (INL)1 Full ±1.1 ±1.2 LSB 25°C ±0.5 ±0.5 LSB TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error Full ±35 ±35 ppm/°C INPUT REFERRED NOISE 25°C 0.7 0.7 LSB rms ANALOG INPUT

Input Span Full 1.383 1.75 2.087 1.383 1.75 2.087 V p-p

Input Capacitance2 Full 6 5 pF

Input Resistance Full 20 20 kΩ VCM OUTPUT LEVEL Full 0.88 0.9 0.92 0.87 0.9 0.92 V POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

IAVDD1 Full 96 100 121 132 mA IDRVDD1 Full 36 40 51 54 mA

POWER CONSUMPTION

Sine Wave Input1 Full 238 252 310 335 mW

Standby Power3 Full 56 56 mW

Power-Down Power Full 7 18 7 18 mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. A | Page 3 of 36

AD9641

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted.

Table 2.

AD9641-80 AD9641-155 Parameter1 Temperature Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 10 MHz 25°C 73.8 73.0 dBFS fIN = 70 MHz 25°C 73.7 72.8 dBFS

fIN = 180 MHz

fIN = 220 MHz 25°C 71.3 71.6 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 73.7 72.5 dBFS fIN = 70 MHz 25°C 73.6 72.0 dBFS fIN = 180 MHz 25°C 72.5 71.5 dBFS Full 71.4 68.7 dBFS fIN = 220 MHz 25°C 71.2 71.1 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.0 fIN = 70 MHz 25°C 11.9 fIN = 180 MHz 25°C 11.8 fIN = 220 MHz 25°C 11.5

WORST SECOND OR THIRD HARMONIC

fIN = 10 MHz 25°C −94 fIN = 70 MHz 25°C −94 fIN = 180 MHz 25°C −91 Full −80 fIN = 220 MHz 25°C −90

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 10 MHz 25°C 94 fIN = 70 MHz 25°C 94 fIN = 180 MHz 25°C 91 Full 80 80 fIN = 220 MHz 25°C 90

WORST OTHER (HARMONIC OR SPUR)

fIN = 10 MHz 25°C −98 fIN = 70 MHz 25°C −98 fIN = 180 MHz 25°C −96 Full −90 fIN = 220 MHz 25°C −90

TWO-TONE SFDR

fIN = 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS ) 25°C 93 fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 89

ANALOG INPUT BANDWIDTH2 25°C 780

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz.

25°C 72.6 72.1 dBFS Full 71.8 69.8 dBFS

11.8

11.7

11.6

11.5

−90

90 90 90

90

−95

−93

−90

90 82 780

Bits Bits Bits Bits

dBc dBc dBc

−80 dBc dBc

dBc dBc dBc dBc dBc

dBc dBc dBc

−87 dBc dBc

dBc dBc MHz

Rev. A | Page 4 of 36

AD9641

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

DSYNC INPUT

Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

LOGIC INPUT (CSB)1

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK)2

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

Rev. A | Page 5 of 36

AD9641

Parameter Temperature Min Typ Max Unit

LOGIC INPUT/OUTPUT (SDIO)1

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

Logic Compliance Full CML Differential Output Voltage (VOD) Full 0.6 0.8 1.1 V Output Offset Voltage (VOS) Full 0.75 DRVDD/2 1.05 V

1

Pull up.

2

Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted.

Table 4.

AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 640 640 MHz Conversion Rate1 Full 40 80 40 155 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 1.935 3.225 4.515 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 3.065 3.225 3.385 ns

Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay (tA) Full 0.78 0.78 ns Aperture Uncertainty (Jitter, tJ) Full 0.125 0.125 ps rms

DATA OUTPUT PARAMETERS

Data Output Period or UI (Unit Interval) Full 1/(20 × f Data Output Duty Cycle 25°C

Data Valid Time 25°C 0.8 0.75 UI

PLL Lock Time (t

) 25°C 4 4 μs

LOCK

Wake Up Time (Standby) 25°C

Wake Up Time (Power-Down)2 25°C 2.5 2.5 ms Pipeline Delay (Latency) Full 23 24 23 24 CLK cycles Data Rate (NRZ) 25°C 1.6 3.1 Gbps Deterministic Jitter 25°C 40 40 ps Random Jitter at 1.6 Gbps 25°C 9.5 ps rms Random Jitter at 3.1 Gbps 25°C 5.2 ps rms Output Rise/Fall Time 25°C 50 50 ps

TERMINATION CHARACTERISTICS

Differential Termination Resistance 25°C 100 100 Ω

OUT-OF-RANGE RECOVERY TIME 25°C 2 2 CLK cycles

1

Conversion rate is the clock rate after the divider.

2

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 12.5 6.45 ns

CLK

) 1/(20 × f

CLK

50

5

50

5

) sec

CLK

%

μs

Rev. A | Page 6 of 36

AD9641

A

TIMING SPECIFICATIONS

Table 5.

Parameter Test Conditions Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.30 ns typ

SSYNC

t

SYNC to rising edge of CLK+ hold time 0.30 ns typ

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min t

SCLK pulse width high 10 ns min

HIGH

t

SCLK pulse width low 10 ns min

LOW

t

EN_SDIO

t

DIS_SDIO

Timing Diagrams

NALOG

INPUT

SIGNAL

N – 23

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

SAMPLE

N – 22

N – 21

N – 20

N

N + 1

N – 1

10 ns min

CLK–

CLK+

CLK–

CLK+

DOUT+

DOUT–

SAMPLE N – 23 ENCODED INTO 2 8b/10b SYMBOLS

SAMPLE N – 22 ENCODED INTO 2 8b/10b SYMBOLS

SAMPLE N – 21 ENCODED INTO 2 8b/10b SY MBOLS

09210-002

Figure 2. Data Output Timing

CLK+

t

HSYNC

09210-003

SYNC

t

SSYNC

Figure 3. SYNC Input Timing Requirements

Rev. A | Page 7 of 36

AD9641

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK to AGND −0.3 V to DRVDD + 0.2 V SDIO to AGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V DOUT+, DOUT− to AGND DSYNC+, DSYNC− to AGND

−0.3 V to DRVDD + 0.2 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Veloc ity

Packa ge Type

32-Lead LFCSP

5 mm × 5 mm (CP-32-12)

1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 36 3 20 °C/W

1.0 32 °C/W

2.5 28 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Ta b le 7 , airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces θ

.

JA

ESD CAUTION

Rev. A | Page 8 of 36

AD9641

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

VIN+

VIN–

AVDD

VCM 52

6

72

82

92

13

03

2 3

AVDD

1

PIN 1

2

DNC

AVDD

CLK+

CLK– AVDD SYNC AVDD

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES T HE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECT ED TO GROUND FOR PRO PER OPERATION.

3 4 5 6 7 8

INDICATOR

AD9641

TOP VIEW

(Not to Scale)

9

01

DSYNC–

DSYNC+

Figure 4. LFCSP Pin Configuration (Top View)

11

DRGND

21

DRVDD

31

DRGND

2

24

PDWN

23

DNC

22

CSB SCLK

21 20

SDIO DRVDD

19 18

DRVDD DRGND

17

51

41

61

DOUT–

DOUT+

DRVDD

09210-004

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type Description

ADC Power Supplies

12, 16, 18, 19 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 1, 3, 6, 8, 26, 27, 30, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 2, 23 DNC Do Not Connect. 11, 13, 17 DRGND Driver ground Digital Driver Supply Ground. 0 AGND, Exposed pad Ground

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog

29 VIN+ Input Differential Analog Input Pin (+). 28 VIN− Input Differential Analog Input Pin (−). 25 VCM Output Common-Mode Level Bias Output. 4 CLK+ Input ADC Clock Input—True. 5 CLK− Input ADC Clock Input—Complement.

Digital Inputs

7 SYNC Input Input Clock Divider Synchronization Pin. 10 DSYNC+ Input

Active Low JESD204A LVDS Sync Input—True/Active Low JESD204A CMOS Sync Input.

9 DSYNC− Input Active Low JESD204A LVDS Sync Input—Complement.

Digital Outputs

15 DOUT+ Output CML Output Data—True. 14 DOUT− Output CML Output Data—Complement.

SPI Control

21 SCLK Input SPI Serial Clock. 20 SDIO Input/output SPI Serial Data I/O. 22 CSB Input SPI Chip Select (Active Low).

ADC Configuration

24 PDWN Input

Power-Down Input. Using the SPI interface, this input can be configured as power-down or standby.

Rev. A | Page 9 of 36

AD9641

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =

−1.0 dBFS, and 32k sample, T

0

–20

–40

= 25°C, unless otherwise noted.

A

80MSPS

10.1MHz @ –1dBF S SNR = 73.0dB (74. 0dBFS) SFDR = 95dBc

0

80MSPS

140.3MHz @ –1dBF S

–20

SNR = 72.2dB (73. 2dBFS) SFDR = 94.0dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 5. AD9641-80 Single-Tone FFT with f

0

80MSPS

30.1MHz @ –1dBF S

–20

SNR = 72.7dB (73. 7dBFS) SFDR = 94dBc

–40

–60

–80

AMPLITUDE (dBFS)

THIRD HARMONIC

–100

–120

–140

0 1020304

Figure 6. AD9641-80 Single-Tone FFT with f

THIRD HARMONIC

FREQUENCY (MHz )

SECOND HARMONIC

FREQUENCY (MHz )

= 10.1 MHz

IN

= 30.1 MHz

IN

0

09210-005

0

09210-006

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 8. AD9641-80 Single-Tone FFT with f

0

80MSPS

180.1MHz @ –1dBFS

–20

SNR = 71.6dB (72.6dBFS) SFDR = 93dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 9. AD9641-80 Single-Tone FFT with f

FREQUENCY (MHz )

FREQUENCY (MHz)

= 140.1 MHz

IN

SECOND HARMONIC

= 180.1 MHz

IN

0

09210-008

0

09210-009

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

SECOND HARMONIC

FREQUENCY (MHz )

Figure 7. AD9641-80 Single-Tone FFT with f

80MSPS

70.1MHz @ –1dBFS SNR = 72.5dB (73. 5dBFS) SFDR = 94.0dBc

THIRD HARMONIC

= 70.1 MHz

IN

0

09210-007

Rev. A | Page 10 of 36

0

80MSPS

220.1MHz @ –1dBF S

–20

SNR = 71.1dB (72. 1dBFS) SFDR = 92dBc

–40

–60

THIRD HARMONIC

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

FREQUENCY (MHz )

Figure 10. AD9641-80 Single-Tone FFT with f

SECOND HARMONIC

= 220.1 MHz

IN

0

09210-010

AD9641

120

100

80

0

–100

–95

SFDR (dBFS) SFDR (dBc) SNR (dBFS) SNR (dBc)

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

INPUT AMPLITUDE (dBF S)

–35

–30

–25

–5

–20

–15

–10

60

40

SNR/SFDR (d Bc/dBFS)

20

Figure 11. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 10.1 MHz, fS = 80 MSPS

with f

IN

120

100

80

SFDR (dBFS)

60

SFDR (dBc) SNR (dBFS) SNR (dBc)

40

SNR/SFDR (dBc/dBFS)

20

95

90

85

80

SNR/SFDR (dBF S/dBc)

75

70

0

09210-011

)

IN

65

Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f

–20

–40

–60

–80

SFDR/IMD3 ( dBc/dBFS )

–100

SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C

0 50 100 150 200 250

Temperature with 2.0 V p-p Full Scale, f

0

SFDR (dBc) IMD3 (dBc) SFDR (dBFS) IMD3 (dBFS)

INPUT FREQ UENCY (MHz)

= 80 MSPS

S

) and

IN

09210-014

0

–95

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

–35

–30

–25

–20

–15

–100

INPUT AMPLITUDE (dBFS)

–10

Figure 12. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 180 MHz, fS = 80 MSPS

with f

IN

100

95

90

85

80

SNR/SFDR (dBF S/dBc)

75

70

65

SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C

0 50 100 150 200 250

INPUT FREQ UENCY (MHz)

Figure 13. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 1.75 V p-p Full Scale, f

= 80 MSPS

S

0

–5

09210-012

)

IN

09210-013

) and

IN

–120

–90 –78 –66 –54 –42 –30 –18 –6

INPUT AMPLITUDE (dBFS)

Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 29.9 MHz, f

with f

IN1

0

–20

–40

–60

–80

SFDR/IMD3 ( dBc/dBFS )

–100

–120

SFDR (dBc) IMD3 (dBc) SFDR (dBFS) IMD3 (dBFS)

–90 –78 –66 –54 –42 –30 –18 –6

= 32.9 MHz, fS = 80 MSPS

IN2

INPUT AMPLITUDE (dBFS)

Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

with f

= 169.1 MHz, f

IN1

= 172.1 MHz, fS = 80 MSPS

IN2

09210-015

)

IN

09210-016

)

IN

Rev. A | Page 11 of 36

ANALOG DEVICES AD9641 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS