ANALOG DEVICES AD9637 Service Manual

Octal, 12-Bit, 40/80 MSPS, Serial LVDS,

A

V

Data Sheet

FEATURES

Low power: 60 mW per channel at 80 MSPS with scalable

power options SNR = 71.5 dBFS (to Nyquist) SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 650 MHz full power analog bandwidth 2 V p-p differential input voltage range

1.8 V supply operation Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Optical networking Test equipment

GENERAL DESCRIPTION

The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

1.8 V Analog-to-Digital Converter

AD9637

FUNCTIONAL BLOCK DIAGRAM

DD

VIN+ A VIN– A

VIN+ B VIN– B

VIN+ C VIN– C

VIN+ D VIN– D

VIN+ E VIN– E

VIN+ F VIN– F

VIN+ G VIN– G

VIN+ H VIN– H

VREF

SENSE

VCM

SYNC

AD9637

REF

SELECT

RBIAS AGND CSB CLK+ CLK–SDIO/

clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI).

The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small,

space-saving package.

2. Low Power of 60 mW/Channel at 80 MSPS with Scalable

Power Options.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 480 MHz and supports double data rate (DDR) operation.

4. User Flexibility. The SPI control offers a wide range of

flexible features to meet specific system requirements.

5. Pin Compatible with the AD9257 (14-Bit Octal ADC).

PDWN DRVDD

12

ADC

12

ADC

12

ADC

12

ADC

12

ADC

12

ADC

12

ADC

12

ADC

1.0V

SERIAL PORT

INTERFACE

DFS

Figure 1.

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SCLK/

DTP

DATA RATE

MULTIPLIER

D+ A D– A

D+ B D– B

D+ C D– C

D+ D D– D

D+ E D– E

D+ F D– F

D+ G D– G

D+ H D– H

FCO+ FCO–

DCO+ DCO–

10215-001

AD9637 Data Sheet

REVISION HISTORY

10/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet AD9637

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 1.

AD9637-40 AD9637-80

Parameter1 Temp

RESOLUTION 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.6 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full 0.0 0.2 0.6 0.0 0.2 0.6 % FSR Gain Error Full −8.0 −2.1 +2.0 −7.0 −3.2 +1.0 % FSR Gain Matching Full −1.0 +1.7 +5.0 −1.0 +2.3 +6.0 % FSR Differential Nonlinearity (DNL) Full −0.8 ±0.3 +0.8 −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL) Full −1.0 ±0.4 +1.0 −1.2 ±0.5 +1.2 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 0.99 1.01 0.98 0.99 1.01 V Load Regulation at 1.0 mA (V

= 1 V) Full 2 2 mV

REF

Input Resistance Full 7.5 7.5 kΩ

INPUT REFERRED NOISE

V

= 1.0 V 25°C 0.36 0.49 LSB rms

REF

ANALOG INPUTS

Differential Input Voltage (V

= 1 V) Full 2 2 V p-p

REF

Common-Mode Voltage Full 0.9 0.9 V Differential Input Resistance 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V I

(Eight Channels) Full 142 151 221 234 mA

AVDD

I

(Eight Channels, ANSI-644 Mode) Full 51 79 58 85 mA

DRVDD

I

(Eight Channels, Reduced Range Mode) 25°C 36 43 mA

DRVDD

TOTAL POWER CONSUMPTION

Total Power Dissipation (Eight Channels, ANSI-644 Mode) Full 347 414 502 574 mW Total Power Dissipation (Eight Channels, Reduced Range Mode) 25°C 320 475 mW Power-Down Dissipation 25°C 1 1 mW Standby Dissipation2 25°C 72 98 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Can be controlled via the SPI.

Min Typ Max Min Typ Max Unit

Rev. 0 | Page 3 of 40

AD9637 Data Sheet

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 2.

AD9637-40 AD9637-80

Parameter1 Temp

Min Typ Max Min Typ Max

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 72.0 71.5 dBFS fIN = 19.7 MHz Full 70.0 72.0 71.0 71.5 dBFS fIN = 30.5 MHz 25°C 72.0 71.5 dBFS fIN = 63.5 MHz 25°C 71.5 dBFS fIN = 69.5 MHz 25°C 71.5 dBFS fIN = 123.5 MHz 25°C 70.5 dBFS

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 71.0 70.5 dBFS fIN = 19.7 MHz Full 69.0 71.0 70.0 70.5 dBFS fIN = 30.5 MHz 25°C 71.0 70.5 dBFS fIN = 63.5 MHz 25°C 70.5 dBFS fIN = 69.5 MHz 25°C 70.5 dBFS fIN = 123.5 MHz 25°C 69.5 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 11.5 11.4 Bits fIN = 19.7 MHz Full 11.2 11.5 11.3 11.4 Bits fIN = 30.5 MHz 25°C 11.5 11.4 Bits fIN = 63.5 MHz 25°C 11.4 Bits fIN = 69.5 MHz 25°C 11.4 Bits fIN = 123.5 MHz 25°C 11.3 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 96 93 dBc fIN = 19.7 MHz Full 78 95 78 92 dBc fIN = 30.5 MHz 25°C 96 92 dBc fIN = 63.5 MHz 25°C 93 dBc fIN = 69.5 MHz 25°C 89 dBc fIN = 123.5 MHz 25°C 88 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −99 −96 dBc fIN = 19.7 MHz Full −96 −78 −92 −78 dBc fIN = 30.5 MHz 25°C −98 −92 dBc fIN = 63.5 MHz 25°C −95 dBc fIN = 69.5 MHz 25°C −89 dBc fIN = 123.5 MHz 25°C −89 dBc

WORST OTHER (EXCLUDING SECOND OR THIRD)

fIN = 9.7 MHz 25°C −98 −97 dBFS fIN = 19.7 MHz Full −98 −86 −97 −86 dBFS fIN = 30.5 MHz 25°C −98 −97 dBFS fIN = 63.5 MHz 25°C −97 dBFS fIN = 69.5 MHz 25°C −97 dBFS fIN = 123.5 MHz 25°C −92 dBFS

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS f

= 8 MHz, f

IN1

f

= 30 MHz, f

IN1

= 10 MHz 25°C 93 dBc

IN2

= 32 MHz 25°C 85 dBc

IN2

Unit

Rev. 0 | Page 4 of 40

Data Sheet AD9637

AD9637-40 AD9637-80

CROSSTALK 25°C −98 −96 dB

Crosstalk (Overrange Condition)2 25°C −89 −89 dB

ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Overrange condition is specified with 3 dB of the full-scale input range.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D± x), ANSI-644

Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 350 454 mV Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D± x), LOW POWER,

REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 200 250 mV Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO/DFS pins sharing the same connection.

Rev. 0 | Page 5 of 40

AD9637 Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

1, 2

Temp Min Typ Max Unit

CLOCK3

Input Clock Rate Full 10 640 MHz Conversion Rate Full 10 40/80 MSPS Clock Pulse Width High (tEH) Full 12.5/6.25 ns Clock Pulse Width Low (tEL) Full 12.5/6.25 ns

OUTPUT PARAMETERS3

Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (t DCO Propagation Delay (t DCO to Data Delay (t

DATA

DCO to FCO Delay (t Data to Data Skew

DATA-MAX

− t

DATA-MIN

(t

) Full 1.5 2.3 3.1 ns

FCO

)4 Full t

CPD

)4 Full (t

FRAME

/24) − 300 (t

SAMPLE

/24) − 300 (t

SAMPLE

+ (t

FCO

SAMPLE

/24) (t

SAMPLE

/24) (t

SAMPLE

/24) ns

/24) + 300 ps

SAMPLE

/24) + 300 ps

SAMPLE

Full ±50 ±200 ps

) Wake-Up Time (Standby) 25°C 35 μs Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16

Clock cycles

APERTURE

Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter) 25°C 0.1 ps rms Out-of-Range Recovery Time 25°C 1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI.

4

t

/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t

SAMPLE

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

SAMPLE

= 1/fS.

TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit Unit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

SSYNC

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING REQUIREMENTS See Figure 61

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min t

SCLK pulse width high 10 ns min

HIGH

t

SCLK pulse width low 10 ns min

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 61)

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 61)

Rev. 0 | Page 6 of 40

10 ns min

Data Sheet AD9637

Timing Diagrams

N – 1

t

VIN± x

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D– x

D+ x

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

MSB

D10

N – 17

N – 17D9N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17D0N – 17

t

EL

t

DATA

D10

MSB

N – 16

05967-002

Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)

N – 1

VIN± x

CLK–

t

A

N

t

EH

t

EL

CLK+

t

DCO–

DCO+

FCO–

FCO+

D– x

D+ x

CPD

MSB

N – 17

t

FRAME

D8

N – 17D7N – 17

D6

N – 17

D5

N – 17

t

DATA

N – 17

D4

D3

N – 17

D2

N – 17

D1

N – 17

D0

N – 17

MSB

N – 16

D8

N – 16D7N – 16

D6

N – 16

D5

N – 16

10215-003

t

FCO

t

PD

Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode

CLK+

t

HSYNC

10215-004

SYNC

t

SSYNC

Figure 4. SYNC Input Timing Requirements

Rev. 0 | Page 7 of 40

AD9637 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V Digital Outputs

−0.3 V to +2.0 V (D± x, DCO+, DCO−, FCO+, FCO−) to AGND

CLK+, CLK− to AGND −0.3 V to +2.0 V VIN+ x, VIN− x to AGND −0.3 V to +2.0 V SCLK/DTP, SDIO/DFS, CSB to AGND −0.3 V to +2.0 V SYNC, PDWN to AGND −0.3 V to +2.0 V RBIAS to AGND −0.3 V to +2.0 V VREF, SENSE to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printed circuit board (PCB) increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Package Type

64-Lead LFCSP 9 mm × 9 mm (CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Airflow Velocity (m/sec) θ

0 22.3 1.4 N/A 0.1 °C/W

1.0 19.5 N/A 11.8 0.2 °C/W

2.5 17.5 N/A

1, 2

θ

JA

1, 3

JC

θ

JB

N/A

1, 4

1, 2



Unit

JT

0.2 °C/W

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown Table 7, airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes reduces θ

.

JA

ESD CAUTION

Rev. 0 | Page 8 of 40

Data Sheet AD9637

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+ F

VIN– F

AVD D

VIN– E

VIN+ E

AVD D

SYNC

VCM

VREF

SENSE

RBIAS

VIN+ D

VIN– D

AVD D

VIN– C

VIN+ C

49

48

AVD D

47

VIN+ B

46

VIN– B

45

AVD D

44

VIN– A

43

VIN+ A

42

AVD D

41

PDWN

40

CSB

39

SDIO/DFS

38

SCLK/DTP

37

AVD D

36

DNC

35

DRVDD

34

D+ A

33

D– A

PIN 1

INDICATOR

AVD D VIN+ G VIN– G

AVD D VIN– H VIN+ H

AVD D

CLK–

CLK+ AVD D AVD D

DNC

DRVDD

D– H

D+ H

646362616059585756555453525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AD9637

TOP VIEW

(Not to Scal e)

171819202122232425262728293031

D– F

D+ F

D– E

D– G

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

D+ E

D+ G

D– D

FCO–

FCO+

DCO–

DCO+

32

D– C

D– B

D+ D

D+ C

D+ B

10215-005

Figure 5. Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

0, EP

1, 4, 7, 8, 11,

AGND, Exposed Pad

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to analog ground for proper operation.

AVDD 1.8 V Analog Supply. 12, 37, 42, 45, 48, 51, 59, 62

13, 36 DNC Do Not Connect. Do not connect to this pin. 14, 35 DRVDD 1.8 V Digital Output Driver Supply. 2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement. 5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True. 9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True. 15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True. 17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True. 19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True. 21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True. 23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True. 25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True. 27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True. 29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True. 31, 32 D− B, D+ B ADC B Digital Output Complement, ADC B Digital Output True. 33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True. 38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP). 39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS). 40 CSB Chip Select Bar. 41 PDWN Power-Down. 43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement. 46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True. 49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement.

Rev. 0 | Page 9 of 40

AD9637 Data Sheet

Pin No. Mnemonic Description

52, 53 VIN− D, VIN+ D ADC D Analog Input Complement, ADC D Analog Input True. 54 RBIAS Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 55 SENSE Reference Mode Selection. 56 VREF Voltage Reference Input/Output. 57 VCM Analog Output Voltage at Midsupply. Sets common mode of the analog inputs. 58 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 60, 61 VIN+ E, VIN− E ADC E Analog Input True, ADC E Analog Input Complement. 63, 64 VIN− F, VIN+ F ADC F Analog Input Complement, ADC F Analog Input True.

Rev. 0 | Page 10 of 40

Data Sheet AD9637

TYPICAL PERFORMANCE CHARACTERISTICS

AD9637-80

0

–15

–30

–45

–60

–75

–90

AMPLIT UDE (dBF S)

–105

–120

–135

4

8 12 16 20 24 28 32 36

FREQUENCY (MHz)

Figure 6. Single-Tone 16k FFT with f

80MSPS

9.7MHz AT –1dBF S SNR = 70.8dB (71.8d BFS) SFDR = 92.7dBc

= 9.7 MHz, f

IN

SAMPLE

= 80 MSPS

10215-006

0

80MSPS

19.7MHz AT –1dBF S

–15

SNR = 70.7dB (71.7d BFS) SFDR = 90. 1dBc

–30

–45

–60

–75

–90

AMPLIT UDE (dBF S)

–105

–120

–135

4 8 12 16 20 24 28 32 36

FREQUENCY (MHz)

Figure 9. Single-Tone 16k FFT with f

= 19.7 MHz, f

IN

SAMPLE

= 80 MSPS

10215-009

0

–15

–30

–45

–60

–75

–90

AMPLIT UDE (dBF S)

–105

–120

–135

4 8 12 16 20 24 28 32 36

FREQUENCY (MHz)

Figure 7. Single-Tone 16k FFT with f

0

–15

–30

–45

–60

–75

–90

AMPLIT UDE (dBF S)

+

F2–F1

–105

–120

–135

4 8 12 16 20 24 28 32 36

F1 + F2

2F1 + F2

2F2 + F1

FREQUENCY (MHz)

Figure 8. Two-Tone 16k FFT with f

= 80 MSPS

f

SAMPLE

80MSPS

63.5MHz AT –1dBF S SNR = 70.5dB (71.5d BFS) SFDR = 93.2dBc

= 63.5 MHz, f

IN

2F1 – F2

= 30 MHz and f

IN1

SAMPLE

IN2

= 80 MSPS

2F2 – F1

= 32 MHz,

0

80MSPS

30.5MHz AT –1dBFS

–15

SNR = 70.7dB (71. 7dBFS) SFDR = 90.7dBc

–30

–45

–60

–75

–90

AMPLIT UDE (dBF S)

–105

–120

–135

10215-007

Figure 10. Single-Tone 16k FFT with f

AMPLITUDE (dBF S)

–105

–120

–135

10215-008

Figure 11. Single-Tone 16k FFT with f

4 8 12 16 20 24 28 32 36

0

80MSPS

123.5MHz AT –1dBFS

–15

SNR = 69.6dB (70.6dBFS) SFDR = 90.3d Bc

–30

–45

–60

–75

–90

4 8 12 16 20 24 28 32 36

FREQUENCY (MHz)

= 30.5 MHz, f

IN

FREQUENCY (MHz)

= 123.5 MHz, f

IN

SAMPLE

= 80 MSPS

10215-109

10215-010

Rev. 0 | Page 11 of 40

AD9637 Data Sheet

0

–20

–40

–60

–80

SFDR/IMD3 (dBc/d BFS)

–100

–120

–90 –78 –66 –54 –42 –6–18–30

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS)

INPUT AMPLITUDE (dBFS)

Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

= 30 MHz and f

f

IN1

120

100

80

60

40

SNR/SFDR (d BFS/d Bc)

20

0 –70 –60 –50 –40 –30 –20 –10

SFDRFS

Figure 13. SNR/SFDR vs. Analog Input Level, f

= 32 MHz, f

IN2

SNRFS

SFDR

SNR

INPUT AMPLITUDE (dBFS)

SAMPLE

= 9.7 MHz, f

IN

= 80 MSPS

SAMPLE

10215-011

0

10215-012

= 80 MSPS

105

100

SFDR (dBc)

95

90

85

SNR/SFDR ( dBFS/dBc)

80

75

SNR (dBFS)

70

–40 85

Figure 15. SNR/SFDR vs. Temperature, f

110

100

90

80

70

60

50

40

SNR/SFDR (dBFS/dBc)

30

20

10

0

0 200

–15 10 35 60

Figure 16. SNR/SFDR vs. f

TEMPERATURE (°C)

IN

SFDR (dBc)

SNR (dBFS)

INPUT FREQUENCY (MHz)

10050 150

, f

IN

= 9.7 MHz, f

SAMPLE

= 80 MSPS

SAMPLE

= 80 MSPS

10215-014

10215-015

105

100

95

90

85

SNR/SFDR (dBFS/dBc)

80

75

70

20 30 40 50 60 70

SFDR

SNRFS

SAMPLE FREQUENCY (MSPS)

Figure 14. SNR/SFDR vs. Encode, f

= 19.7 MHz

IN

80

10215-013

Rev. 0 | Page 12 of 40

105

100

95

90

85

80

SNR/SFDR (d BFS/d Bc)

75

70

65

20 30 40 50 60 70 80

Figure 17. SNR/SFDR vs. Encode, f

SFDR

SNRFS

SAMPLE FREQUENCY (MSPS)

= 30.5 MHz

IN

10215-016

ANALOG DEVICES AD9637 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AD9637-80