ANALOG DEVICES AD9635 Service Manual

Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS

Data Sheet

FEATURES

1.8 V supply operation
Low power: 115 mW per channel at 125 MSPS with scalable

power options
SNR = 71 dBFS (to Nyquist)
SFDR = 93 dBc at 70 MHz
DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced

range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Clock divider

Programmable output clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging and ultrasound
Radar/LIDAR

GENERAL DESCRIPTION

The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to­digital converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

Rev. 0

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No

rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Trademarks and registered trademarks are the property of their respective owners.

1.8 V Analog-to-Digital Converter

AD9635

FUNCTIONAL BLOCK DIAGRAM

AVDD DRVDD

AD9635

VINA+
VINA–

VCM

VINB+
VINB–

12-BIT PIPELINE

12-BIT PIPELINE

REFERENCE

SERIAL PORT

INTERFACE

SCLK/

DFS

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported; the AD9635 typically consumes less
than 2 mW in the full power-down state. The ADC provides
several features designed to maximize flexibility and minimize
system cost, such as programmable output clock and data align­ment and digital test pattern generation. The available digital
test patterns include built-in deterministic and pseudorandom
patterns, along with custom user-defined test patterns entered via
the serial port interface (SPI).

The AD9635 is available in a RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Small Footprint. Two ADCs are contained in a small, space-

saving package.

2. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS

with scalable power options.

3. Pin Compatibility with the AD9645, a 14-Bit Dual ADC.

4. Ease of Use. A data clock output (DCO) operates at

frequencies of up to 500 MHz and supports double data
rate (DDR) operation.

5. User Flexibility. SPI control offers a wide range of flexible

features to meet specific system requirements.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

AGND

ADC

ADC

SDIO/

CSB CLK+ CLK–

PDWN

Figure 1.

12

12

12

12

1 TO 8

CLOCK DIVIDER

D0A+
D0A–
D1A+
D1A–
D0B+
D0B–
D1B+

LVDS DRIVERS

PLL, SERIALIZER AND DDR

D1B–
DCO+
DCO–
FCO+
FCO–

10577-001

AD9635 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications .......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 12

AD9635-80 .................................................................................. 12

AD9635-125 ................................................................................ 15

Equivalent Circuits ......................................................................... 18

Theory of Operation ...................................................................... 19

Analog Input Considerations .................................................... 19

Voltage Reference ....................................................................... 20

Clock Input Considerations ...................................................... 21

Power Dissipation and Power-Down Mode ........................... 22

Digital Outputs and Timing ..................................................... 23

Output Test Modes ..................................................................... 26

Serial Port Interface (SPI) .............................................................. 27

Configuration Using the SPI ..................................................... 27

Hardware Interface ..................................................................... 28

Configuration Without the SPI ................................................ 28

SPI Accessible Features .............................................................. 28

Memory Map .................................................................................. 29

Reading the Memory Map Register Table ............................... 29

Memory Map Register Table ..................................................... 30

Memory Map Register Descriptions ........................................ 33

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Power and Ground Guidelines ................................................. 35

Exposed Pad Thermal Heat Slug Recommendations ............ 35

VCM ............................................................................................. 35

Reference Decoupling ................................................................ 35

SPI Por t ........................................................................................ 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

6/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

Data Sheet AD9635

REF

REF

REF

AVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

AVDD

2

DRVDD

DRVDD

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 1.

AD9635-80 AD9635-125

Parameter1 Temp

RESOLUTION 12 12 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed

Offset Error Full −0.6 −0.3 +0.1 −0.6 −0.3 +0.2 % FSR

Offset Matching Full −0.2 +0.1 +0.4 −0.2 +0.1 +0.4 % FSR

Gain Error Full −4.0 −0.8 +2.1 −4.7 −0.4 +4.8 % FSR

Gain Matching Full 0.5 2.4 0.6 2.9 % FSR

Differential Nonlinearity (DNL) Full −0.2

25°C −0.1 to +0.2

Integral Nonlinearity (INL) Full −0.7

25°C ±0.3

TEMPERATURE DRIFT

Offset Error Full 2.9 3.7 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.0 1.02 0.98 1.0 1.02 V

Load Regulation at 1.0 mA (V

= 1 V ) 25°C 2 2 mV

Input Resistance 25°C 7.5 7.5 kΩ

INPUT-REFERRED NOISE

V

= 1.0 V 25°C 0.41 0.42 LSB rms

ANALOG INPUTS

Differential Input Voltage ( V

= 1 V ) Full 2 2 V p-p
Common-Mode Voltage Full 0.9 0.9 V
Common-Mode Range 25°C 0.5 1.3 0.5 1.3 V
Differential Input Resistance 25°C 5.2 5.2 kΩ
Differential Input Capacitance 25°C 3.5 3.5 pF

POWER SUPPLY

Min Typ Max Min Typ Max Unit

+0.4 −0.3

−0.1 to +0.2

+0.7 −1.1

±0.4

+0.6 LSB

LSB

+1.1 LSB

LSB

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
I

Full 57 61 75 81 mA

I

(ANSI-644 Mode)2 Full 45 47 52 55 mA

I

(Reduced Range Mode)2 25°C 36

43

TOTAL POWER CONSUMPTION

DC Input Full 174 186 215 232 mW
Sine Wave Input (Two Channels; Includes Output Drivers

Full 184 194 229 245 mW

in ANSI-644 Mode)

Sine Wave Input (Two Channels; Includes Output Drivers

25°C 167 212 mW

in Reduced Range Mode)
Power-Down 25°C 2 2 mW
Standby3 Full 91 99 114 124 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on both channels.

3

Can be controlled via the SPI.

Rev. 0 | Page 3 of 36

mA

AD9635 Data Sheet

fIN = 30.5 MHz

25°C 90

93 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 70 MHz

Full −94

−82 −94

−82

dBc

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 2.

AD9635-80 AD9635-125

Parameter1 Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 71.8 71.5 dBFS
fIN = 30.5 MHz 25°C 71.7 71.5 dBFS
fIN = 70 MHz Full 70.6 71.2 70.1 71.1 dBFS
fIN = 139.5 MHz 25°C 69.9 70.2 dBFS
fIN = 200.5 MHz 25°C 68.4 68.9 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 71.8 71.5 dBFS
fIN = 30.5 MHz 25°C 71.6 71.5 dBFS
fIN = 70 MHz Full 70.5 71.2 69.7 71.1 dBFS
fIN = 139.5 MHz 25°C 69.6 70.2 dBFS
fIN = 200.5 MHz 25°C 68.2 68.7 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 11.6 11.6 Bits
fIN = 30.5 MHz 25°C 11.6 11.6 Bits
fIN = 70 MHz Full 11.4 11.5 11.3 11.5 Bits
fIN = 139.5 MHz 25°C 11.3 11.4 Bits
fIN = 200.5 MHz 25°C 11.0 11.1 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 93 92 dBc

Unit Min Typ Max Min Typ Max

fIN = 70 MHz Full 82 94 82 93 dBc
fIN = 139.5 MHz 25°C 81 92 dBc
fIN = 200.5 MHz 25°C 82 83 dBc

fIN = 9.7 MHz 25°C −93 −92 dBc
fIN = 30.5 MHz 25°C −90 −93 dBc
fIN = 70 MHz Full −94 −85 −93 −82 dBc
fIN = 139.5 MHz 25°C −81 −92 dBc
fIN = 200.5 MHz 25°C −82 −83 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 9.7 MHz 25°C −96 −95 dBc
fIN = 30.5 MHz 25°C −95

−95 dBc

fIN = 139.5 MHz 25°C −95 −93 dBc
fIN = 200.5 MHz 25°C −92 −89 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND

AIN2 = −7.0 dBFS
f

= 70.5 MHz, f

IN1

= 72.5 MHz 25°C −92 −92 dBc

IN2

CROSSTALK2 25°C −97 −97 dB
CROSSTALK (OVERRANGE CONDITION)3 25°C −97 −97 dB
POWER SUPPLY REJECTION RATIO (PSRR)4

AVDD 25°C 44 43 dB
DRVDD 25°C 59 66 dB

ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Te sting and Evaluat ion, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is specified with 3 dB of the full-scale input range.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitude of the spur voltage over the amplitude of the pin voltage, expressed in decibels (dB).

Rev. 0 | Page 4 of 36

Data Sheet AD9635

Logic 1 Voltage

Full

1.2 AVDD + 0.2

V

Logic 0 Voltage

Full 0

0.8

V

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF

LOGIC INPUT (SCLK/DFS)

Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO/PDWN)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V

Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO/PDWN)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644

Logic Compliance LVDS
Differential Output Voltage Magnitude (VOD) Full 290 345 400 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER,

REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage Magnitude (VOD) Full 160 200 230 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO/PDWN pins sharing the same connection.

Rev. 0 | Page 5 of 36

AD9635 Data Sheet

1, 2

Fall Time (tF) (20% to 80%)

Full 300 ps

FCO

CPD

FCO

SAMPLE

DAT A

SAMPLE

SAMPLE

SAMPLE

FRAME

SAMPLE

SAMPLE

SAMPLE

DATA -MAX

DATA -MIN

CLK

HIGH

LOW

Time required for the SDIO pin to switch from an input to an output relative

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

CLOCK3

Input Clock Rate Full 10 1000 MHz
Conversion Rate Full 10 80/125 MSPS
Clock Pulse Width High (tEH) Full 6.25/4.00 ns
Clock Pulse Width Low (tEL) Full 6.25/4.00 ns

OUTPUT PARAMETERS3

Propagation Delay (tPD) Full 2.3 ns
Rise Time (tR) (20% to 80%) Full 300 ps

Temp Min Typ Max Unit

FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t

) Full 1.5 2.3 3.1 ns

)4 Full t

)4 Full (t

)4 Full (t

/12) − 300 t
/12) − 300 t

+ (t

/12) ns
/12 (t
/12 (t

/12) + 300 ps

/12) + 300 ps
Lane Delay (tLD) 90 ps
Data-to-Data Skew (t

− t

) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 250 ns
Wake-Up Time (Power-Down)5 25°C 375 μs
Pipeline Latency Full 16

Clock
cycles

APERTURE

Aperture Delay (tA) 25°C 1 ns
Aperture Uncertainty (Jitter, tJ) 25°C 174 fs rms
Out-of-Range Recovery Time 25°C 1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

t

/16 is based on the number of bits in two LVDS data lanes. t

SAMPLE

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

SAMPLE

= 1/fS.

Clock
cycles

TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit

SPI TIMING REQUIREMENTS See Figure 68

tDS Setup time between the data and the rising edge of SCLK 2 ns min
tDH Hold time between the data and the rising edge of SCLK 2 ns min
t

Period of the SCLK 40 ns min
tS Setup time between CSB and SCLK 2 ns min
tH Hold time between CSB and SCLK 2 ns min
t

SCLK pulse width high 10 ns min

t

SCLK pulse width low 10 ns min

t

EN_SDIO

10 ns min

to the SCLK falling edge (not shown in Figure 68)

t

Time required for the SDIO pin to switch from an output to an input relative

DIS_SDIO

10 ns min

to the SCLK rising edge (not shown in Figure 68)

Unit

Rev. 0 | Page 6 of 36

Data Sheet AD9635

D0A–

D0A+
D1A–

D1A+

FCO–

BYTEWISE

MODE

FCO+

D0A–

D0A+

D1A–

D1A+

FCO–

DCO+

CLK+

CLK–

DCO–

DCO+

DCO–

FCO+

BITWISE

MODE

SDR

DDR

10577-002

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

MSB

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

MSB

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

MSB

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

MSB

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

t

EH

t

CPD

t

FRAME

t

FCO

t

PD

t

DATA

t

LD

t

EL

VINx±

t

A

N – 1

N

N + 1

D0A–

D0A+
D1A–

D1A+

FCO–

BYTEWISE

MODE

FCO+

D0A–

D0A+
D1A–

D1A+

FCO–

DCO+

CLK+

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

DCO+

DCO–

10577-003

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

MSB

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

MSB

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

D05

N – 17

t

EH

t

CPD

t

FRAME

t

FCO

t

PD

t

DATA

t

LD

t

EL

VINx±

t

A

N – 1

N

N + 1

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

D08

N – 15

D06

N – 15

D04

N – 15

D02

N – 15

LSB

N – 16

MSB

N – 16

D07

N – 15

D05

N – 15

D03

N – 15

MSB

N – 15

D01

N – 17

D04

N – 16

D03

N – 15

D02

N – 15

D01

N – 15

D04

N – 15

MSB

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

MSB

N – 15

D08

N – 15

D07

N – 15

D06

N – 15

D05

N – 16

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Tabl e 20 for SPI register settings.

Figure 2. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

Figure 3. 10-Bit DDR/SDR, Two-Lane, 1× Frame Mode

Rev. 0 | Page 7 of 36

AD9635 Data Sheet

D0A–

D0A+
D1A–

D1A+

FCO–

BYTEWISE

MODE

FCO+

D0A–

D0A+
D1A–

D1A+

FCO–

DCO+

CLK+

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

DCO+

DCO–

10577-004

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

MSB

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

MSB

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

MSB

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

MSB

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

t

EH

t

CPD

t

FRAME

t

FCO

t

PD

t

DATA

t

LD

t

EL

VINx±

t

A

N – 1

N

N + 1

D0A–

D0A+

D1A–

D1A+

FCO–

BYTEWISE

MODE

FCO+

D0A–

D0A+

D1A–

D1A+

FCO–

DCO+

CLK+

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

DCO+

DCO–

10577-005

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

MSB

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

MSB

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

D05

N – 17

t

EH

t

CPD

t

FRAME

t

FCO

t

PD

t

DATA

t

LD

t

EL

VINx±

t

A

N – 1

N

N + 1

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

D08

N – 15

D06

N – 15

D04

N – 15

D02

N – 15

LSB

N – 16

MSB

N – 16

D07

N – 15

D05

N – 15

D03

N – 15

MSB

N – 15

D01

N – 17

D04

N – 16

D03

N – 15

D02

N – 15

D01

N – 15

D04

N – 15

MSB

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

MSB

N – 15

D08

N – 15

D07

N – 15

D06

N – 15

D05

N – 16

Figure 4. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode

Figure 5. 10-Bit DDR/SDR, Two-Lane, 2× Frame Mode

Rev. 0 | Page 8 of 36

Data Sheet AD9635

10577-006

D0x–

D0x+

FCO–

DCO+

CLK+

VINx±

CLK–

DCO–

FCO+

D10

N – 17

MSB

N – 17

D9

N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17D0N – 17

MSB

N – 16

D10

N – 16

t

A

t

DATA

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

10577-007

D0x–

D0x+

FCO–

DCO+

CLK+

VINx±

CLK–

DCO–

FCO+

MSB
N – 9D8N – 9

D8

N – 8D7N – 8D6N – 8

D7

N – 9D6N – 9D5N – 9D4N – 9D3N – 9D2N – 9D1N – 9D0N – 9

MSB
N – 8

D5

N – 8

t

A

t

DATA

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

Figure 6. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode

Figure 7. Wordwise DDR, One-Lane, 1× Frame, 10-Bit Output Mode

Rev. 0 | Page 9 of 36

AD9635 Data Sheet

AVDD to AGND

−0.3 V to +2.0 V

CLK+, CLK− to AGND

−0.3 V to +2.0 V

Ψ

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating
Electrical

DRVDD to AGND −0.3 V to +2.0 V
Digital Outputs to AGND

(D0x±, D1x±, DCO+, DCO−,
FCO+, FCO−)

VINx+, VINx− to AGND −0.3 V to +2.0 V
SCLK/DFS, SDIO/PDWN, CSB to AGND −0.3 V to +2.0 V
RBIAS to AGND −0.3 V to +2.0 V
VREF to AGND −0.3 V to +2.0 V
VCM to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature Range (Ambient) −40°C to +85°C
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to +2.0 V

THERMAL RESISTANCE

The exposed paddle is the only ground connection on the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow

Package Type

32-Lead LFCSP,
5 mm × 5 mm

1

Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-STD 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Velocity
(m/sec)

0 37.1 3.1 20.7 0.3 °C/W

1.0 32.4 0.5 °C/W

2.5 29.1 0.8 °C/W

1, 2

1, 3

θ

θ

JA

JC

1, 4

θ

JB

1, 2

Unit

JT

Typ i c a l θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and
power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 10 of 36

Data Sheet AD9635

24

AVDD

23

RBIAS

22

VCM

21

VREF

20

CSB

19

DRVDD

18

D0A+

17

D0A–

1
2
3
4
5
6
7
8

AVDD

CLK+
CLK–

S

DIO/PDWN
SCLK/DFS

DRVDD

D1B–
D1B+

9

10111213141516

D0B–

D0B+

DCO–

DCO+

FCO–

FCO+

D1A–

D1A+

32313029282726

25

AVDD

VINB–

VINB+

AVDD

AVDD

VINA+

VINA–

AVDD

AD9635

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PADDLE IS THE ONLY GROUND CO NNE CTION
ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND
OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT
DISSIPAT ION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

10577-008

4

SDIO/PDWN

Data Input/Output in SPI Mode (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
pull-down. DFS high = twos complement output; DFS low = offset binary output.

6, 19

DRVDD

1.8 V Supply Pins for Output Driver Domain.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 8. Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND,

Exposed Pad

The exposed paddle is the only ground connection on the chip. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength

benefits.
1, 24, 25, 28 29, 32 AVDD 1.8 V Supply Pins for ADC Analog Core Domain.
2, 3 CLK+, CLK− Differential Encode Clock for LVPECL, LVDS, or 1.8 V CMOS Inputs.

Power-Down in Non-SPI Mode (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.
5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format, with 30 kΩ internal

7, 8 D1B−, D1B+ Channel B Digital Outputs.
9, 10 D0B−, D0B+ Channel B Digital Outputs.
11, 12 DCO−, DCO+ Data Clock Outputs.
13, 14 FCO−, FCO+ Frame Clock Outputs.
15, 16 D1A−, D1A+ Channel A Digital Outputs.
17, 18 D0A−, D0A+ Channel A Digital Outputs.
20 CSB SPI Chip Select. Active low enable with 15 kΩ internal pull-up.
21 VREF 1.0 V Voltage Reference Input/Output.
22 VCM Analog Output Voltage at Mid AVDD Supply. Sets the common-mode voltage of the analog inputs.
23 RBIAS Sets the analog current bias. Connect this pin to a 10 kΩ (1% tolerance) resistor to ground.
26, 27 VINA−, VINA+ Channel A ADC Analog Inputs.
30, 31 VINB+, VINB− Channel B ADC Analog Inputs.

Rev. 0 | Page 11 of 36