ANALOG DEVICES AD9634 Service Manual

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

A

V

FEATURES

SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS SFDR = 87 dBc at 185 MHz A

−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A 250 MSPS

Total power consumption: 360 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 350 MHz Internal ADC voltage reference Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer Serial port control Energy-saving power-down modes User-configurable, built-in self test (BIST) capability

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G)

TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

and 250 MSPS

IN

and

IN

1.8 V Analog-to-Digital Converter

AD9634

FUNCTIONAL BLOCK DIAGRAM

DD AGND DRVDD

VIN+

VIN–

VCM

AD9634

REFERENCE

SCLK SDIO CSB CLK+ CLK–

PIPELINE

12-BIT

ADC

SERIAL PORT

12

PAR ALL EL DDR LVDS

AND

DRIVERS

1-TO-8

CLOCK DIVI DER

Figure 1.

D0±/D1±

. . .

D10±/D11±

DCO±

OR±

09996-001

GENERAL DESCRIPTION

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The ADC output data are routed directly to the external 12-bit LVDS out p ut p or t .

Flexible power-down options allow significant power savings, when desired.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.

The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.

2. Fast overrange and threshold detect.

3. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 350 MHz.

4. 3-pin, 1.8 V SPI port for register programming and readback.

5. Pin compatibility with the AD9642, allowing a simple

migration up to 14 bits, and with the AD6672.

AD9634

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9634

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled, unless otherwise noted.

Table 1.

AD9634-170 AD9634-210 AD9634-250

Parameter Te mp e r at u r e

RESOLUTION Full 12 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±11 ±11 ±11 mV Gain Error Full +2/−11 +1/−8 +3/−7 %FSR Differential Nonlinearity (DNL) Full ±0.4 ±0.4 ±0.4 LSB 25°C ±0.22 ±0.22 ±0.22 LSB Integral Nonlinearity (INL)1 Full ±0.4 ±0.4 ±0.6 LSB 25°C ±0.2 ±0.2 ±0.27 LSB

TEMPERATURE DRIFT

Offset Error Full ±7 ±7 ±7 ppm/°C Gain Error Full ±55 ±58 ±75 ppm/°C

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.531 0.391 0.407 LSB rms

ANALOG INPUT

Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

I

Full 123 134 129 139 136 145 mA

AVDD

1

I

Full 50 54 56 60 64 68 mA

DRVDD

POWER CONSUMPTION

Sine Wave Input (DRVDD = 1.8 V) Full 311 340 333 360 360 385 mW Standby Power4 Full 50 50 50 mW Power-Down Power Full 5 5 5 mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and its complement.

3

Input resistance refers to the effective resistance between one differential input pin and its complement.

4

Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).

Min Typ Max Min Typ Max Min Typ Max Unit

Rev. 0 | Page 3 of 32

AD9634

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted.

Table 2.

AD9634-170 AD9634-210 AD9634-250 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 30 MHz 25°C 70.3 70.2 70.1 dBFS fIN = 90 MHz 25°C 70.1 70.1 70.0 dBFS Full 69.1 68.8 dBFS fIN = 140 MHz 25°C 69.9 70.0 69.9 dBFS fIN = 185 MHz 25°C 69.5 69.6 69.7 dBFS Full 67.8 dBFS fIN = 220 MHz 25°C 69.2 69.2 69.3 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 30 MHz 25°C 69.4 69.2 69.2 dBFS fIN = 90 MHz 25°C 69.2 69.1 69.0 dBFS Full 68.1 67.8 dBFS fIN = 140 MHz 25°C 68.9 69.1 69.0 dBFS fIN = 185 MHz 25°C 68.5 68.7 68.7 dBFS Full 66.7 dBFS fIN = 220 MHz 25°C 68.3 68.3 68.4 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 30 MHz 25°C 11.2 11.2 11.2 Bits fIN = 90 MHz 25°C 11.2 11.2 11.2 Bits fIN = 140 MHz 25°C 11.1 11.2 11.2 Bits fIN = 185 MHz 25°C 11.1 11.1 11.1 Bits fIN = 220 MHz 25°C 11.0 11.0 11.1 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 30 MHz 25°C −96 −96 −90 dBc fIN = 90 MHz 25°C −95 −92 −89 dBc Full −83 −80 dBc fIN = 140 MHz 25°C −97 −94 −91 dBc fIN = 185 MHz 25°C −86 −95 −87 dBc Full −80 dBc fIN = 220 MHz 25°C −84 −84 −93 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 30 MHz 25°C 96 96 90 dBc fIN = 90 MHz 25°C 95 92 89 dBc Full 83 80 dBc fIN = 140 MHz 25°C 97 94 91 dBc fIN = 185 MHz 25°C 86 95 87 dBc Full 80 dBc fIN = 220 MHz 25°C 84 84 93 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 30 MHz 25°C −98 −96 −95 dBc fIN = 90 MHz 25°C −97 −95 −95 dBc Full −87 −83 dBc fIN = 140 MHz 25°C −98 −97 −96 dBc fIN = 185 MHz 25°C −95 −95 −94 dBc Full −81 dBc fIN = 220 MHz 25°C −96 −95 −94 dBc

Rev. 0 | Page 4 of 32

AD9634

AD9634-170 AD9634-210 AD9634-250 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit

TWO-TONE SFDR

fIN = 184.1 MHz, 187.1 MHz (−7 dBFS) 25°C 87 89 88 dBc FULL POWER BANDWIDTH2 25°C 350 350 350 MHz NOISE BANDWIDTH3 25°C 1000 1000 1000 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.

3

Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally.

Rev. 0 | Page 5 of 32

AD9634

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Full 10 22 μA Low Level Input Current Full −22 −10 μA Input Capacitance Full 4 pF Input Resistance Full 12 15 18 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 50 71 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK)2

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO)1

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

LVDS Data and OR Outputs (OR+, OR−)

Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull-up.

2

Pull-down.

CMOS/LVDS/LVPECL Full 0.9 V Full 0.3 3.6 V p-p Full AGND AVDD V Full 0.9 1.4 V

Rev. 0 | Page 6 of 32

AD9634

SWITCHING SPECIFICATIONS

Table 4.

AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS1

Input Clock Rate Full 625 625 625 MHz

Conversion Rate2

DCS Enabled Full 40 170 40 210 40 250 MSPS

DCS Disabled Full 10 170 10 210 10 250 MSPS CLK Period, Divide-by-1 Mode (t CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns

Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns

Divide-by-2 Mode Through

Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS1

Data Propagation Delay (tPD) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns DCO Propagation Delay (t DCO to Data Skew (t

DCO

) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns

SKEW

Pipeline Delay (Latency) Full 10 10 10 Cycles Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power-Down) Full 100 100 100 μs Out-of-Range Recovery Time Full 3 3 3 Cycles

1

See . Figure 2

2

Conversion rate is the clock rate after the divider.

Timing Diagram

VIN

) Full 5.8 4.8 4 ns

CLK

Full 0.8 0.8 0.8 ns

) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns

N – 1

t

A

N

N + 1

N + 2

N + 3

N + 4

N + 5

EVEN/ODD

CLK+

CLK–

DCO–

DCO+

D0±/D1±

(LSB)

D10±/D11±

(MSB)

t

CH

t

CLK

t

DCO

t

PD

SKEW

D0

N – 10D1N – 10D0N – 9D1N – 9D0N – 8D1N – 8D0N – 7D1N – 7D0N – 6

D10

N – 10

D11

N – 10

D10

N – 9

D11

N – 9

D10

N – 8

D11

N – 8

D10

N – 7

D11

N – 7

D10

N – 6

09996-002

Figure 2. Even/Odd LVDS Mode Data Output Timing

Rev. 0 | Page 7 of 32

AD9634

TIMING SPECIFICATIONS

Table 5.

Parameter Test Conditions/Comments Min Typ Max Unit

SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

Minimum period that SCLK should be in a logic high state 10 ns

HIGH

t

Minimum period that SCLK should be in a logic low state 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58)

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58)

10 ns

Rev. 0 | Page 8 of 32

AD9634

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2V VCM to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V SDIO to AGND −0.3 V to DRVDD + 0.3 V D0±/D1± through D10±/D11±

−0.3 V to DRVDD + 0.3 V

to AGND DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +125°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Package Typ e

32-Lead LFCSP

5 mm × 5 mm (CP-32-12)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Veloc ity

(m/sec) θ

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

0 37.1 3.1 20.7 °C/W

1.0 32.4 °C/W

2.0 29.1 °C/W

Typical θJA is specified for a 4-layer PCB with solid ground plane. As shown in Ta b le 7 , airflow increases heat dissipation, which reduces θ

. In addition, metal in direct contact with the package

JA

leads from metal traces, through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 9 of 32

AD9634

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVD D

VIN+

VIN–

AVD D

VCM

D6–/D7–

D6+/D7+

D8–/D9–

DNC 25

D8+/D9+

24

CSB

23

SCLK SDIO

22

DCO+

21 20

DCO–

19

D10+/D11+ (MSB)

18

D10–/D11– (MSB) DRVDD

17

09996-003

32313029282726

1

CLK+

2

CLK–

AVD D

3 4 5 6 7 8

AD9634

TOP VIEW

(Not to Scale)

9

10111213141516

D2–/D3–

D4–/D5–

D2+/D3+

D4+/D5+

OR–

OR+ D0–/D1– (LSB) D0+/D1+ (LSB)

DRVDD

NOTES

1. DNC = DO NOT CONNE CT. DO NOT CONNECT TO T HIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM O F THE PACKAGE PROVIDES THE ANALOG GRO UND FOR T HE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type Description

ADC Power Supplies

8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0

AGND, Exposed Paddl e

Ground

Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation.

25 DNC Do No Connect. Do not connect to this pin.

ADC Analog

30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output

Common-Mode Level Bias Output for Analog Inputs. This pin should be

decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement.

Digital Outputs

5 OR+ Output Overrange—True. 4 OR− Output Overrange—Complement. 7 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/Data 1—True (LSB). 6 D0−/D1− (LSB) Output DDR LVDS Output Data 0/Data 1—Complement (LSB). 10 D2+/D3+ Output DDR LVDS Output Data 2/Data 3—True. 9 D2−/D3− Output DDR LVDS Output Data 2/Data 3—Complement. 12 D4+/D5+ Output DDR LVDS Output Data 4/Data 5—True. 11 D4−/D5− Output DDR LVDS Output Data 4/Data 5—Complement. 14 D6+/D7+ Output DDR LVDS Output Data 6/Data 7—True. 13 D6−/D7− Output DDR LVDS Output Data 6/Data 7—Complement. 16 D8+/D9+ Output DDR LVDS Output Data 8/Data 9—True. 15 D8−/D9− Output DDR LVDS Output Data 8/Data 9—Complement. 19 D10+/D11+ (MSB) Output DDR LVDS Output Data 10/Data 11—True (MSB). 18 D10−/ D11− (MSB) Output DDR LVDS Output Data 10/Data 11—Complement (MSB). 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement.

Rev. 0 | Page 10 of 32

ANALOG DEVICES AD9634 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

Timing Diagram

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS