ANALOG DEVICES AD9627 Service Manual

12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS,

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FEATURES

SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS SFDR = 84 dBc to 70 MHz @ 150 MSPS Low power: 820 mW @ 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS ou

tput supply Integer 1-to-8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features

Fast detect/threshold bits Composite signal monitor

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G)

GSM, EDGE, WCDMA,

CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

1.8 V Dual Analog-to-Digital Converter

AD9627

FUNCTIONAL BLOCK DIAGRAM

SCLK/

AVDD

FD BITS/THRESHOLD

VIN+A

VIN–A

VREF

SENSE

CML

RBIAS

VIN–B

VIN+B

SHA

REF

SELECT

SHA

AD9627

MULTICHI P

SYNC

AGND SYNC FD(0:3)B

NOTES

1. PIN NAMES ARE F OR THE CMO S PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PI N NAMES.

FD(0:3)A

DVDD

DETECT

ADC

FD BITS/THRESHOLD

PRODUCT HIGHLIGHTS

1. Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/

150 MSPS ADC.

2. F

ast overrange detect and signal monitor with serial output.

3. Si

gnal monitor block with dedicated serial output mode.

4. P

roprietary differential input that maintains excellent SNR

performance for input frequencies up to 450 MHz.

5. O

peration from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

tandard serial port interface (SPI) that supports various

6. S

product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.

in compatibility with the AD9640, AD9627-11, and AD9600

7. P

for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits.

SDIO/

DCS

PROGRAMMING DATA

SIGNAL

MONITOR

DIVIDE

1 TO 8

DUTY CYCLE

STABILIZER

ADC

DETECT

Figure 1.

CSB

DFS

SPI

DCO

GENERATIO N

SIGNAL MO NITOR

DATA

SIGNAL MONITOR

INTERFACE

SMI

SCLK/

SDFS

PDWN

DRVDD

CMOS

SMI

SDO/

OEB

D11A

D0A

OUTPUT BUFFER

CLK+

CLK–

DCOA

DCOB

D11B

D0B

OUTPUT BUF FER

DRGND

06571-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9627

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REVISION HISTORY

10/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 76

AD9627

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GENERAL DESCRIPTION

The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined a

rchitecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9627 has several functions that simplify the automatic ga

in control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monit

oring of the incoming signal power, using the four fast detect

bits of the ADC with very low latency. If the input signal level

exceeds the programmable threshold, the coarse upper threshold

cator goes high. Because this threshold indicator has very

indi low latency, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block al

lows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 12-b

it output ports. These outputs can be set from 1.8 V to 3.3 V

CMOS or 1.8 V LVDS.

Flexible power-down options allow significant power savings,

en desired.

wh

Programming for setup and control is accomplished using a 3-bit S

PI-compatible serial interface.

The AD9627 is available in a 64-lead LFCSP and is specified over t

he industrial temperature range of −40°C to +85°C.

Rev. 0 | Page 3 of 76

AD9627

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SPECIFICATIONS

ADC DC SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table 1.

AD9627BCPZ-80 AD9627BCPZ-105

Parameter Temperature

Min Typ Max Min Typ Max

RESOLUTION Full 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Gain Error Full +0.1 −1.8 −3.7 −0.5 −2.2 −3.7 % FSR Differential Nonlinearity (DNL)

1

Full ±0.4 ±0.4 LSB 25°C ±0.2 ±0.2 LSB Integral Nonlinearity (INL)

1

Full ±0.9 ±0.9 LSB

25°C ±0.4 ±0.4 LSB MATCHING CHARACTERISTIC

Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Gain Error Full ±0.2 ±0.75 ±0.2 ±0.75 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.3 0.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance

2

Full 8 8 pF

VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1, 3

I

AVDD

1, 3

I

DVDD

1

I

(3.3 V CMOS) Full 23 34 mA

DRVDD

1

I

(1.8 V CMOS) Full 11 15 mA

DRVDD

1

I

(1.8 V LVDS) Full 47 47 mA

DRVDD

Full 233 310 mA

Full 26

278

34

365

POWER CONSUMPTION

DC Input Full 452 490 600 650 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 495 657 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 550 740 mW Standby Power

4

Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

AVDD

and I

currents.

DVDD

Unit

mA

Rev. 0 | Page 4 of 76

AD9627

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ADC DC SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table 2.

AD9627BCPZ-125 AD9627BCPZ-150

Parameter Temperature

Min Typ Max Min Typ Max

RESOLUTION Full 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.2 ±0.6 % FSR Gain Error Full −0.7 −2.7 −3.9 −0.9 −3.2 −5.2 % FSR Differential Nonlinearity (DNL)

1

Full ±0.4 ±0.9 LSB

25°C ±0.2 ±0.2 LSB

Integral Nonlinearity (INL)

1

Full ±0.9 ±1.3 LSB 25°C ±0.4 ±0.5 LSB MATCHING CHARACTERISTIC

Offset Error 25°C ±0.3 ±0.6 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.75 ±0.2 ±0.8 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.3 0.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p

Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1, 3

I

AVDD

1, 3

I

DVDD

1

I

(3.3 V CMOS) Full 36 42 mA

DRVDD

1

I

(1.8 V CMOS) Full 18 22 mA

DRVDD

1

I

(1.8 V LVDS) Full 48 49 mA

DRVDD

Full 385 419 mA Full 42

455

50

495

POWER CONSUMPTION

DC Input Full 750 800 820 890 mW

Sine Wave Input1 (DRVDD = 1.8 V) Full 814 895 mW

Sine Wave Input1 (DRVDD = 3.3 V) Full 900 995 mW

Standby Power

4

Full 77 77 mW

Power-Down Power Full 2.5 6 2.5 6 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

AVDD

and I

DVDD

currents.

Unit

mA

Rev. 0 | Page 5 of 76

AD9627

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ADC AC SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table 3.

Parameter

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.3 MHz 25°C 69.7 69.6 dB fIN = 70 MHz 25°C 69.5 69.4 dB Full 68.1 68.6 dB fIN = 140 MHz 25°C 69.2 69.1 dB fIN = 220 MHz 25°C 68.5 68.4 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.3 MHz 25°C 69.6 69.5 dB fIN = 70 MHz 25°C 69.4 69.3 dB Full 67.4 68.0 dB fIN = 140 MHz 25°C 69.0 69.0 dB fIN = 220 MHz 25°C 68.3 68.1 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.3 MHz 25°C 11.5 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.4 11.4 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.3 MHz 25°C −87 −87 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −74 −74 dBc fIN = 140 MHz 25°C −84 −84 dBc fIN = 220 MHz 25°C −83 −83 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.3 MHz 25°C 87 87 dBc fIN = 70 MHz 25°C 85 85 dBc Full 74 74 dBc fIN = 140 MHz 25°C 84 84 dBc fIN = 220 MHz 25°C 83 83 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −82 −82 dBc fIN = 140 MHz 25°C −89 −87 dBc fIN = 220 MHz 25°C −89 −86 dBc

TWO-TONE SFDR

fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc

fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK ANALOG INPUT BANDWIDTH 25°C 650 650 MHz

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

1

2

Temperature

Full −95 −95 dB

AD9627BCPZ-80 AD9627BCPZ-105

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 6 of 76

AD9627

www.BDTIC.com/ADI

ADC AC SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table 4.

Parameter

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.3 MHz 25°C 69.5 69.4 dB fIN = 70 MHz 25°C 69.4 69.2 dB Full 68.1 67.1 dB fIN = 140 MHz 25°C 69.1 68.8 dB fIN = 220 MHz 25°C 68.8 68.2 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.3 MHz 25°C 69.4 69.3 dB fIN = 70 MHz 25°C 69.3 69.1 dB Full 67.9 65.9 dB fIN = 140 MHz 25°C 69.0 68.7 dB fIN = 220 MHz 25°C 68.3 67.8 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.3 MHz 25°C 11.4 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.3 11.3 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.3 MHz 25°C −86.5 −86.5 dBc fIN = 70 MHz 25°C −85 −84 dBc Full −74 −73 dBc fIN = 140 MHz 25°C −84 −83.5 dBc fIN = 220 MHz 25°C −83 −77 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.3 MHz 25°C 86.5 86.5 dBc fIN = 70 MHz 25°C 85 84 dBc Full 74 73 dBc fIN = 140 MHz 25°C 84 83.5 dBc fIN = 220 MHz 25°C 83 77 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −81 −80 dBc fIN = 140 MHz 25°C −89 −88 dBc fIN = 220 MHz 25°C −89 −88 dBc

TWO-TONE SFDR

fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc

fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK ANALOG INPUT BANDWIDTH 25°C 650 650 MHz

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

1

2

Temperature

Full −95 −95 dB

AD9627BCPZ-125 AD9627BCPZ-150

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 7 of 76

AD9627

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 5.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full GND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS)2

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA

1

2

Rev. 0 | Page 8 of 76

AD9627

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Parameter Temperature Min Typ Max Unit

Input Resistance Full 26 kΩ

Input Capacitance Full 5 pF DIGITAL OUTPUTS

CMOS Mode—DRVDD = 3.3 V

High Level Output Voltage

IOH = 50 μA Full 3.29 V IOH = 0.5 mA Full 3.25 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

Rev. 0 | Page 9 of 76

AD9627

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SWITCHING SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 6.

AD9627BCPZ-80 AD9627BCPZ-105

Parameter Temperature

Min Typ Max Min Typ Max

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz Conversion Rate

DCS Enabled DCS Disabled

CLK Period—Divide-by-1 Mode (t

1

Full 20 80 20 105 MSPS Full 10 80 10 105 MSPS

) Full 12.5 9.5 ns

CLK

CLK Pulse Width High

Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns Divide by-1-Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3 Through Divide-by-8

Full 0.8 0.8 ns

Modes, DCS Enabled

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns

DCO

Full 2.2 4.5 6.4 2.2 4.5 6.4 ns

Setup Time (tS) Full 6.25 5.25 ns Hold Time (tH) Full 5.75 4.25 ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns

DCO

Full 2.4 5.2 6.9 2.4 5.2 6.9 ns

Setup Time (tS) Full 6.65 5.15 ns Hold Time (tH) Full 5.85 4.35 ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 5.2 7.3 9.0 5.2 7.3 9.0 ns

DCO

Full 2.0 4.8 6.3 2.0 4.8 6.3 ns

CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)

Full 12/12.5 12/12.5 Cycles

Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time

3

Full 350 350 μs

OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors.

Unit

Rev. 0 | Page 10 of 76

AD9627

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SWITCHING SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 7.

AD9627BCPZ-125 AD9627BCPZ-150

Parameter Temperature

Min Typ Max Min Typ Max

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz Conversion Rate

DCS Enabled DCS Disabled

CLK Period—Divide-by-1 Mode (t

1

CLK

Full 20 125 20 150 MSPS Full 10 125 10 150 MSPS

) Full 8 6.66 ns

CLK Pulse Width High

Divide-by-1 Mode, DCS Enabled Full 2.4 4 5.6 2.0 3.33 4.66 ns Divide-by-1 Mode, DCS Disabled Full 3.6 4 4.4 3.0 3.33 3.66 ns Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3 Through Divide-by-8

Full 0.8 0.8 ns

Modes, DCS Enabled

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns

DCO

Full 2.2 4.5 6.4 2.2 4.5 6.4 ns

Setup Time (tS) Full 4.5 3.83 ns Hold Time (tH) Full 3.5 2.83 ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns

DCO

Full 2.4 5.2 6.9 2.4 5.2 6.9 ns

Setup Time (tS) Full 4.4 3.73 ns Hold Time (tH) Full 3.6 2.93 ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 5.2 7.3 9.0 5.2 7.3 9.0 ns

DCO

Full 2.0 4.8 6.3 2.0 4.8 6.3 ns

CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)

Full 12/12.5 12/12.5 Cycles

Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time

3

Full 350 350 μs

OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles

1

Conversion rate is the clock rate after the divider.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors.

Unit

Rev. 0 | Page 11 of 76

AD9627

C

A

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TIMING SPECIFICATIONS

Table 8.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SSYNC

t

HSYNC

SPI TIMING REQUIREMENTS

t

DS

t

DH

t

CLK

t

S

t

H

t

HIGH

t

LOW

t

EN_SDIO

t

DIS_SDIO

SPORT TIMING REQUIREMENTS

t

CSSCLK

t

SSCLKSDO

t

SSCLKSDFS

Timing Diagrams

H A/CH B DAT

SYNC to rising edge of CLK setup time 0.24 ns SYNC to rising edge of CLK hold time 0.40 ns

Setup time between the data and the rising edge of SCLK 2 ns Hold time between the data and the rising edge of SCLK 2 ns Period of the SCLK 40 ns Setup time between CSB and SCLK 2 ns Hold time between CSB and SCLK 2 ns SCLK pulse width high 10 ns SCLK pulse width low 10 ns Time required for the SDIO pin to switch from an input to an

10 ns

output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an

10 ns

input relative to the SCLK rising edge

Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 0.4 ns Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 0.4 ns

N+2

CLK+

CLK–

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

N+ 3

N – 10

N+ 4

N+ 5

N+ 6

N+ 8

N+ 7

CH A/CH B FAST

DETECT

t

S

DCOA/DCOB

Figure 2. CMOS Output Mode Data an

N – 1 N + 2 N + 3 N + 4 N + 5 N + 6N – 3 N – 2

t

H

N

d Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)

Rev. 0 | Page 12 of 76

t

N + 1

DCO

t

CLK

06571-002

AD9627

C

A

www.BDTIC.com/ADI

N

t

A

CLK+

CLK–

H A/CH B DAT

CH A/CH B F AST

DETECT

DCO+

DCO–

t

PD

ABABABABABABABABA AB

N – 13

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

ABABABABABABABABA AB

N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7

Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect M

N+ 1

t

CLK

N+2

N+ 3

N – 10

N – 4

t

DCO

N+ 4

N+ 5

t

N+ 6

CLK

N+ 8

N+ 7

ode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)

06571-003

CLK+

CLK–

SMI SCLK

SMI SDFS

t

CSSCLK

t

SSYNC

SYNC

Figure 4. SYNC Input Timing Requirements

t

SSCLKSDFS

Figure 5. Signal Monitor SPORT Outpu

t

HSYNC

t

SSCLKSDO

DATA DATASMI SDO

t Timing (Divide-by-2 Mode)

06571-004

06571-005

Rev. 0 | Page 13 of 76

AD9627

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

ELECTRICAL

AVDD, DVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to +3.9 V SYNC to AGND −0.3 V to +3.9 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to DRGND −0.3 V to +3.9 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V SMI SDO/OEB −0.3 V to DRVDD + 0.3 V SMI SCLK/PDWN −0.3 V to DRVDD + 0.3 V SMI SDFS −0.3 V to DRVDD + 0.3 V D0A/D0B through D11A/D11B to

DRGND

FD0A/FD0B through FD3A/FD3B to

DRGND

DCOA/DCOB to DRGND

−0.3 V to DRVDD + 0.3 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 10. Thermal Resistance

Airflow Package Typ e

64-Lead LFCSP 9 mm × 9 mm (CP-64-3)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Ve

lo city

(m/s) θ

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

0 18.8 0.6 6.0 °C/W

1.0 16.5 °C/W

2.0 15.8 °C/W

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the package

JA

leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 14 of 76

AD9627

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DRGND

D3B

D2B

D1B

D0B (LSB)

DNC

DVDD

FD3B

FD2B

FD1B

FD0B

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN+B

43

VIN–B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN–A

37

VIN+A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

D4B D5B D6B D7B D8B D9B

D10B

D11B (MSB)

DCOB DCOA

DNC DNC

D0A (LSB)

D1A D2A

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICATO R

EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)

AD9627

PARALLEL CMOS

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

171819202122232425262728293031

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

FD0A

DRGND

DRVDD

DVDD

FD1A

D11A (MSB)

32

FD2A

FD3A

06571-006

Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 11. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 12, 13, 58, 59 DNC Do Not Connect. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Tab le 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator. See Tab le 17 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Tab le 17 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Tab le 17 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Tab le 17 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Table 17 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 17 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 17 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 17 for details. Digital Input 52 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. 0 | Page 15 of 76

AD9627

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Outputs 14 D0A (LSB) Output Channel A CMOS Output Data. 15 D1A Output Channel A CMOS Output Data. 16 D2A Output Channel A CMOS Output Data. 17 D3A Output Channel A CMOS Output Data. 18 D4A Output Channel A CMOS Output Data. 19 D5A Output Channel A CMOS Output Data. 22 D6A Output Channel A CMOS Output Data. 23 D7A Output Channel A CMOS Output Data. 25 D8A Output Channel A CMOS Output Data. 26 D9A Output Channel A CMOS Output Data. 27 D10A Output Channel A CMOS Output Data. 28 D11A (MSB) Output Channel A CMOS Output Data. 60 D0B (LSB) Output Channel B CMOS Output Data. 61 D1B Output Channel B CMOS Output Data. 62 D2B Output Channel B CMOS Output Data. 63 D3B Output Channel B CMOS Output Data. 2 D4B Output Channel B CMOS Output Data. 3 D5B Output Channel B CMOS Output Data. 4 D6B Output Channel B CMOS Output Data. 5 D7B Output Channel B CMOS Output Data. 6 D8B Output Channel B CMOS Output Data. 7 D9B Output Channel B CMOS Output Data. 8 D10B Output Channel B CMOS Output Data. 9 D11B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Rev. 0 | Page 16 of 76

AD9627

www.BDTIC.com/ADI

DRGND

DNC

FD3+

FD3–

FD2+

FD2–

DVDD

FD1+

FD1–

FD0+

FD0–

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN+B

43

VIN–B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN–A

37

VIN+A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

DNC

DNC D0– (LSB) D0+ (LSB)

D1– D1+ D2– D2+

DCO–

DCO+

D3– D3+ D4– D4+ D5–

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICATO R

EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)

AD9627

PARALLEL LVDS

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

171819202122232425262728293031

D6–

D7–

D8–

D5+

D6+

DRGND

DRVDD

D7+

DVDD

D8+

D9–

D9+

D10–

D10+

32

D11– (MSB)

D11+ (MSB)

06571-007

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 2, 3, 62,

DNC Do Not Connect.

63 ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details. 53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details. 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details. 55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details. 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details. 58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details. 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details. 60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details. Digital Input

52 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. 0 | Page 17 of 76

AD9627

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 13 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 12 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 15 D4+ Output Channel A/Channel B LVDS Output Data 4 —True. 14 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 17 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 16 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 19 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 18 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 23 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 22 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 26 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 25 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 28 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 27 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Rev. 0 | Page 18 of 76

AD9627

V

C

S

V

www.BDTIC.com/ADI

EQUIVALENT CIRCUITS

LK+

IN

06571-008

Figure 8. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 9. Equivalent Clock Input Circuit

DRVDD

CLK–

SCLK/DFS

26kΩ

1kΩ

06571-012

Figure 12. Equivalent SCLK/DFS Input Circuit

SENSE

06571-009

1kΩ

06571-013

Figure 13. Equivalent SENSE Circuit

AVDD

26kΩ

CSB

1kΩ

DRGND

6571-010

Figure 10. Digital Output

DRVDD

26kΩ

DIO/DCS

1kΩ

06571-011

Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit

Rev. 0 | Page 19 of 76

Figure 14. Equivalent CSB Input Circuit

AVDD

REF

6kΩ

06571-015

Figure 15. Equivalent VREF Circuit

06571-014

AD9627

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 64k sample, T

0

–20

–40

= 25°C, unless otherwise noted.

A

150MSPS

2.3MHz @ –1dBF S SNR = 69.4dBc (70.4dBFS) ENOB = 11.4 BI TS SFDR = 86.5dBc

–20

–40

0

150MSPS 140MHz @ –1dBFS SNR = 68.8dBc (69.8dBFS) ENOB = 11.3 BITS SFDR = 83.5d Bc

–60

–80

AMPLITUDE ( dBFS)

–100

–120

Figure 16. AD9627-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

Figure 17. AD9627-150 Single-Tone FFT with f

SECOND HARMONIC

THIRD HARMONIC

07

FREQUENCY (MHz)

150MSPS

30.3MHz @ –1dBF S SNR = 69.3dBc (70.3dBFS) ENOB = 11.4 BITS SFDR = 84.0d Bc

HARMONIC

FREQUENCY (MHz)

THIRD

605040302010

= 2.3 MHz

IN

SECOND HARMONIC

605040302010

= 30.3 MHz

IN

0

06571-016

0

06571-017

–60

–80

AMPLITUDE ( dBFS)

–100

–120

070605040302010

Figure 19. AD9627-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

070605040302010

Figure 20. AD9627-150 Single-Tone FFT with f

SECOND HARMONIC

FREQUENCY (MHz)

150MSPS 220MHz @ –1dBFS SNR = 68.2dBc (69. 2dBFS) ENOB = 11.2 BITS SFDR = 77.0dBc

SECOND HARMONIC

FREQUENCY (MHz)

THIRD HARMONIC

THIRD

HARMONIC

= 140 MHz

IN

= 220 MHz

IN

06571-019

06571-020

0

150MSPS 70MHz @ –1dBFS SNR = 69.2dBc (70. 2dBFS)

–20

ENOB = 11.4 BITS SFDR = 84.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

07

SECOND HARMONIC

FREQUENCY (MHz)

Figure 18. AD9627-150 Single-Tone FFT with f

THIRD

HARMONIC

605040302010

= 70 MHz

IN

0

06571-018

Rev. 0 | Page 20 of 76

0

150MSPS 337MHz @ –1dBFS SNR = 67.6dBc (68. 6dBFS)

–20

ENOB = 11.1 BITS SFDR = 74.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

070605040302010

FREQUENCY (MHz)

THIRD HARMONIC

Figure 21. AD9627-150 Single-Tone FFT with f

SECOND

HARMONIC

= 337 MHz

IN

06571-021

AD9627

www.BDTIC.com/ADI

0

125MSPS 70MHz @ –1dBFS SNR = 69.4dBc (70. 4dBFS)

–20

ENOB = 11.4 BITS SFDR = 85dBc

–40

–20

–40

0

150MSPS 440MHz @ –1dBFS SNR = 65.7dBc (66.7dBFS) ENOB = 10.4 BITS SFDR = 70.0d Bc

–60

–80

AMPLITUDE ( dBFS)

100

–

–120

07

Figure 22. AD9627-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

SECOND HARMONIC

06

Figure 23. AD9627-125 Single-Tone FFT with f

SECOND HARMONIC

THIRD HARMONIC

FREQUENCY (MHz)

125MSPS

2.3MHz @ –1dBF S SNR = 69.5dBc (70.5dBFS) ENOB = 11.4 BITS SFDR = 86.5d Bc

FREQUENCY (MHz)

605040302010

= 440 MHz

IN

5040302010

= 2.3 MHz

IN

0

06571-022

0

06571-023

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0605040302010

Figure 25. AD9627-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0605040302010

Figure 26. AD9627-125 Single-Tone FFT with f

SECOND HARMONIC

FREQUENCY (MHz)

THIRD HARMONIC

125MSPS 140MHz @ –1dBFS SNR = 69.1dBc (70.1dBFS) ENOB = 11.3 BITS SFDR = 84dBc

SECOND HARMONIC

= 70 MHz

IN

THIRD HARMONIC

= 140 MHz

IN

06571-025

06571-026

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

06

FREQUENCY (MHz)

Figure 24. AD9627-125 Single-Tone FFT with f

125MSPS

30.3MHz @ –1dBF S SNR = 69.4dBc (70.4dBFS) ENOB = 11.4 BITS SFDR = 85dBc

THIRD HARMONIC

SECOND

HARMONIC

5040302010

= 30.3 MHz

IN

0

06571-024

0

125MSPS 337MHz @ –1dBFS SNR = 67.6dBc (68. 6dBFS)

–20

ENOB = 11.1 BITS SFDR = 74dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0605040302010

Figure 27. AD9627-125 Single-Tone FFT with f

Rev. 0 | Page 21 of 76

THIRD HARMONIC

FREQUENCY (MHz)

SECOND HARMONIC

= 337 MHz

IN

06571-027

AD9627

–

www.BDTIC.com/ADI

120

SFDR (dBFS)

100

80

SNR (dBFS)

60

40

SNR/SFDR (dBc AND dBFS)

20

0

–90 0–10–20–30–40–50–60–70–80

SFDR (dBc)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

85dB REFERENCE L INE

Figure 28. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 2.4 MHz

with f

IN

100

SFDR (dBFS)

06571-028

)

IN

SNR/SFDR (dBc)

95

90

85

SFDR = +25°C

80

75

70

65

60

55

0440035030025020015010050

SFDR = –40°C

INPUT FREQ UENCY (MHz)

SFDR = +85°C

SNR = +25°C SNR = +85°C SNR = –40°C

Figure 31. AD9627-150 Single-Tone SNR/SFDR vs.

Input Frequ

2.5

) and Temperature with 1 V p-p Full Scale

ency (f

IN

50

06571-031

0.5

80

SNR (dBFS)

60

SFDR (dBc)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SNR/SFDR (dBc AND dBFS)

40

20

0

–90 0–10–20–30–40–50–60–70–80

Figure 29. AD9627-150 Single-Tone S

= 98.12 MHz

f

IN

95

90

85

80

75

70

SNR/SFDR (dBc)

65

60

55

04

SFDR = –40°C

SNR = +25°C SNR = +85°C SNR = –40°C

INPUT FREQ UENCY (MHz)

Figure 30. AD9627-150 Single-Tone SNR/SFDR vs.

Input Frequ

) and Temperature with 2 V p-p Full Scale

ency (f

IN

85dB REFERENCE LINE

NR/SFDR vs. Input Amplitude (A

SFDR = +85°C

SFDR = +25°C

25020015010050

50400350300

) with

IN

–3.0

–3.5

–4.0

GAIN ERROR (%F SR)

–4.5

–5.0

–40 806040

06571-029

TEMPERATURE ( °C)

GAIN

OFFSET

200–20

0.4

0.3

0.2

0.1

0

OFFSET ERROR (%FSR)

06571-032

Figure 32. AD9627-150 Gain and Offset vs. Temperature

0

SFDR (dBc)

–20

IMD3 (dBc)

–40

–60

–80

SFDR/IMD3 (dBc AND dBFS )

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

06571-030

Figure 33. AD9627-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

with f

= 29.1 MHz, f

IN1

SFDR (dBFS)

IMD3 (dBFS)

INPUT AMPLI TUDE (dBFS)

= 32.1 MHz, fS = 150 MSPS

IN2

06571-033

)

IN

Rev. 0 | Page 22 of 76

AD9627

www.BDTIC.com/ADI

0

–20

SFDR (dBc)

–40

IMD3 (dBc)

–60

–20

–40

–60

0

150MSPS

169.1MHz @ –7dBF S

172.1MHz @ –7dBF S SFDR = 83.8d Bc (90.8dBFS )

–80

SFDR/IMD3 (dBc AND dBFS )

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

SFDR (dBFS)

IMD3 (dBFS)

INPUT AMPLITUDE (dBFS)

Figure 34. AD9627-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 169.1 MHz, f

with f

IN1

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 15.36 30.72 46.08 61. 44

= 172.1 MHz, fS = 150 MSPS

IN2

FREQUENCY (MHz )

Figure 35. AD9627-125, Two 64k WCDMA Carriers

= 170 MHz, fS = 122.88 MSPS

with f

IN

0

–20

150MSPS

29.1MHz @ –7dBF S

32.1MHz @ –7dBF S SFDR = 86.1d Bc (93.1dBFS )

–80

AMPLITUDE ( dBFS)

–100

–120

07605040302010

06571-034

)

IN

06571-035

Figure 37. AD9627-150 Two-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

07605040302010

FREQUENCY (MHz)

= 172.1 MHz

f

IN2

FREQUENCY (MHz )

= 169.1 MHz and

IN1

NPR = 61.5dBc NOTCH @ 18.5MHz NOTCH WIDT H = 3MHz

0

06571-037

0

06571-038

Figure 38. AD9627-150 Noise Power Ratio (NPR)

100

SFDR - SIDE B

90

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

07

FREQUENCY (MHz)

Figu re 36. AD9627-150 Two-Tone FFT with f

= 29.1 MHz and f

IN1

605040302010

0

06571-036

= 32.1 MHz

IN2

Rev. 0 | Page 23 of 76

SFDR - SIDE A

SNR - SIDE B

SNR - SIDE A

SAMPLE RATE (MSPS)

SNR/SFDR (dBc)

80

70

60

50

0150125100755025

Figure 39. AD9627-150 Single-Tone SNR/SFDR vs. Sample Rate (f

with f

= 2.3 MHz

IN

06571-039

)

S

ANALOG DEVICES AD9627 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

ADC DC SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

ADC DC SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

ADC AC SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

ADC AC SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS—AD9627BCPZ-80/AD9627BCPZ-105

SWITCHING SPECIFICATIONS—AD9627BCPZ-125/AD9627BCPZ-150

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS