ANALOG DEVICES AD9626 Service Manual

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

www.BDTIC.com/ADI

FEATURES

SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ f SFDR = 80 dBc @ f Excellent linearity

DNL =

±0.3 LSB typical

INL = ±0.7 LSB typical

CMOS outputs

Single data port at up to 250 MHz

Interleaved dual port @ ½ sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation

272 mW

364 mW @ 250 MSPS Programmable input voltage range

V to 1.5 V, 1.25 V nominal

1.0

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

omplement, Gray code)

c Clock duty cycle stabilizer Integrated data capture clock

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

@ 170 MSPS

1.8 V Analog-to-Digital Converter AD9626

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

FUNCTIONAL BLOCK DIAGRAM

AGNDPWDNRBIAS AVDD (1.8V)

CML

VIN+

VIN–

CLK+

CLK–

REFERENCE

TRACK-AND-HOLD

CLOCK

MANAGEMENT

ADC 12-BIT CORE

SERIAL PORT

SCLK SDIO CSB

RESET

12 12

Figure 1.

AD9626

OUTPUT

STAGING

LVDS

DRVDD

DRGND

Dx11 TO Dx0

OVRA

OVRB

DCO+

DCO–

07099-001

GENERAL DESCRIPTION

The AD9626 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differen-

ial clock for full performance operation. The digital outputs are

t CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9626 is

vailable in a 56-lead LFCSP, specified over the industrial

a temperature range (−40°C to +85°C).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS

with a 70 MHz input.

2. L

ow Power—Consumes only 364 mW @ 250 MSPS.

3. E

ase of Use—CMOS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

erial Port Control—Standard serial port interface supports

4. S

various product functions, such as data formatting, clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.

in-Compatible Family—10-bit pin-compatible family

5. P

offered as the AD9601.

AD9626

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REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9626

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SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T unless otherwise noted.

Table 1.

Parameter

1

RESOLUTION 12 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.0 4.0 4.0 mV Full −12 +12 −12 +12 −12 +12 mV Gain Error 25°C 1.4 1.4 1.4 % FS Full −2.1 +4.5 −2.1 +4.5 −2.1 +4.5 % FS Differential Nonlinearity (DNL) 25°C 0.3 0.3 0.3 LSB Full −0.6 +0.6 −0.6 +0.6 −0.6 +0.6 LSB Integral Nonlinearity (INL) 25°C 0.7 0.6 0.7 LSB Full −1.4 +1.4 −1.1 +1.1 −1.7 +1.7 LSB

TEMPERATURE DRIFT

Offset Error Full ±8 ±8 ±8 µV/°C Gain Error Full 0.021 0.021 0.021 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.58 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents

3

I

AVDD

3

I

/Single Port Mode

DRVDD

3

I

/Interleaved Mode

DRVDD

Power Dissipation

Single Port Mode Interleaved Mode

3

4

5

4

5

Power-Down Mode Supply

Currents I

AVDD

I

DRVDD

Standby Mode Supply Currents

I

AVDD

I

DRVDD

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9626.

5

Interleaved mode; user-programmable feature. See the Memory Map section.

are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.

DRVDD

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,

MAX

AD9626-170 AD9626-210 AD9626-250

Temp Min Typ Max Min Typ Max Min Typ Max Unit

Full 134 143 151 161 178 191 mA Full 17 18.5 21 22 24 25.5 mA Full 15 18 20 mA Full mW Full 272 291 310 330 364 390 mW Full 268 304 357 mW

Full 40 40 40 µA Full 170 170 22 170 µA

Full 19 19 19 mA Full 170 170 22 170 µA

Rev. 0 | Page 3 of 36

AD9626

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AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T enabled, unless otherwise noted.

Table 2.

Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit

SNR

fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.6 63.0 dB fIN = 70 MHz 25°C 64.4 64.2 63.8 dB Full 63.0 62.3 dB

SINAD

fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.5 62.8 dB fIN = 70 MHz 25°C 64.2 64.0 63.4 dB Full 62.6 62.0 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 10.6 10.6 10.5 Bits fIN = 70 MHz 25°C 10.5 10.5 10.5 Bits

WORST HARMONIC (SECOND OR THIRD)

fIN = 10 MHz 25°C 84 86 83 dBc Full 75 77 73 dBc fIN = 70 MHz 25°C 79 79 80 dBc Full 71 73 71 dBc

WORST OTHER (SFDR EXCLUDING

SECOND AND THIRD) fIN = 10 MHz 25°C 92 90 84 dBc Full 85 79 76 dBc fIN = 70 MHz 25°C 92 87 84 dBc Full 81 77 73 dBc

TWO-TONE IMD

140.2 MHz/141.3 MHz @ −7 dBFS 25°C 80 dBFS

170.2 MHz/171.3 MHz @ −7 dBFS 25°C 83 83 dBc

ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

= −40°C, T

MIN

1

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, , Single Port Output mode, DCS

MAX

AD9626-170 AD9626-210 AD9626-250

Rev. 0 | Page 4 of 36

AD9626

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

AD9626-170 AD9626-210 AD9626-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full

Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V Input Resistance (Differential) Full 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance Full 4 4 4 pF

LOGIC INPUTS

Logic 1 Voltage Full

Logic 0 Voltage Full

Logic 1 Input Current (SDIO) Full 0 0 0 µA Logic 0 Input Current (SDIO) Full −60 −60 −60 µA Logic 1 Input Current

(SCLK, PDWN, CSB, RESET)

Logic 0 Input Current

(SCLK, PDWN, CSB, RESET)

Input Capacitance 25°C 4 4 4 pF

LOGIC OUTPUTS2

High Level Output Voltage Full DRVDD − 0.05 DRVDD − 0.05 DRVDD − 0.05 V Low Level Output Voltage Full GND + 0.05 GND + 0.05 GND + 0.05 V Output Coding Twos complement, Gray code, or offset binary (default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

AVDD −

0.3

0.8 × A

Full 55 55 50 µA

Full 0 0 0 µA

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

VDD

AVDD +

1.6

0.2 × VDD

A

AVDD −

0.3

0.8 × A

VDD

AVDD +

1.6

0.2 × AVDD

AVDD −

0.3

0.8 × A

VDD

V

AVDD +

1.6

0.2 × AVDD

V

Rev. 0 | Page 5 of 36

AD9626

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

AD9626-170 AD9626-210 AD9626-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full 170 Minimum Conversion Rate Full CLK+ Pulse Width High (tCH) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns CLK+ Pulse Width Low (tCL) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns Output, Single Data Port Mode

Data Propagation Delay (tPD) 25°C 3.7 3.7 3.7 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full 0 0.3 0.55 0 0.3 0.55 0 0.3 0.55 ns

SKEW

Latency Full 6 6 6 Cycles

SKEWA

2

PDA

CPDA

, t

SKEWB

Output, Interleaved Mode

Data Propagation Delay (t DCO Propagation Delay (t Data to DCO Skew (t

Latency Full 6 6 6 Cycles Standby Recovery 25°C 250 250 250 ns Power-Down Recovery

Aperture Delay (tA) 25°C 0.1 0.1 0.1 ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 0.2 ps rms

1

See Figure 2.

2

See Figure 3.

1

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

40

210

250 40

40 MSPS

MSPS

) 25°C 3.4 3.4 3.4 ns

, t

) 25°C 3.5 3.5 3.5 ns

PDB

, t

) 25°C 3.0 3.0 3.0 ns

CPDB

) Full 0 0.5 1.1 0 0.5 1.1 0 0.5 1.1 ns

50 50 50 µs

Rev. 0 | Page 6 of 36

AD9626

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TIMING DIAGRAMS

N + 2

N + 1

N

t

A

t

= 1/

f

CLK+

CLK–

DCO–

DCO+

t

DAX N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7

CLK

t

CPD

t

SKEW

PD

N + 2

CLK+

CLK–

DCO+

DCO–

DAX

N + 1

N

t

A

t

= 1/

f

CLK

t

CPDA

t

PDA

SKEWA

N + 3

CLK

N – 6

N + 3

CLK

Figure 2. Single Port Mode

N + 4

N + 5

t

CPDB

N – 4

N + 4

N + 6

N + 5

N – 2

N + 7

N + 6

N + 8

N + 7

N + 8

07099-051

N

N + 2

t

SKEWB

t

PDB

DBX

N – 7

N – 5

N – 3

N – 1

N + 1

07099-050

Figure 3. Interleaved Mode

Rev. 0 | Page 7 of 36

AD9626

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V

DRVDD to DRGND −0.3 V to +2.0 V

AGND to DRGND −0.3 V to +0.3 V

AVDD to DRVDD −2.0 V to +2.0 V

Dx0 Through Dx11 to DRGND −0.3 V to DRVDD + 0.3 V

DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V

OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V

CLK+ to AGND −0.3 V to +3.6 V

CLK− to AGND −0.3 V to +3.6 V

VIN+ to AGND −0.3 V to AVDD + 0.2 V

VIN− to AGND −0.3 V to AVDD + 0.2 V

SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V

PDWN to AGND −0.3 V to +3.6 V

CSB to AGND −0.3 V to +3.6 V

SCLK/DFS to AGND −0.3 V to +3.6 V ENVIRONMENTAL

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Lead Temperature

(Soldering, 10 sec)

Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θ

56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θ

.

JA

θ

JC

Unit

JA

. In

ESD CAUTION

Rev. 0 | Page 8 of 36

AD9626

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SB)

AVDD

DA3

DA2

DA1

DA0 (L

DCO+

DA5

DA4

54

56

55

DCO–

53

52

51

50

49

CLK+

DRGND

DRVDD

AVDD

CLK–

43

44

48

47

46

45

1DA6 2DA7 3DA8 4DA9 5DA10 6(MSB) DA11 7DRVDD 8DRGND

9OVRA 10(LSB) DB0 11DB1 12DB2 13DB3 14DB4

PIN 1 INDICATO R

AD9626

TOP VIEW

(Not to Scale)

PIN 0 (EXPOS ED PADDLE) = AGND

21

17

16

18

19

15

DB5

20

B7

DB8

DB9

D

DB6

DB10

25

26

24

23

22

/DCS

OVRB

DRVDD

DRGND

SDIO

(MSB) DB11

SCLK/DFS

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 RBIAS 30 AVDD 29 PWDN

28

27

CSB

RESET

07099-002

Figure 4. Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No. Mnemonic Description

30, 32, 33, 34, 37, 38,

AVDD 1.8 V Analog Supply.

39, 41, 42, 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND 8, 23, 48 DRGND

1

Analog Ground.

Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

ed internal bias voltage for VIN+/VIN−.

optimiz 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial P

ort Mode); Duty Cycle Stabilizer Select

(External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 DA0 (LSB) Output Port A Output Bit 0 (LSB). 52 DA1 Output Port A Output Bit 1. 53 DA2 Output Port A Output Bit 2. 54 DA3 Output Port A Output Bit 3. 55 DA4 Output Port A Output Bit 4. 56 DA5 Output Port A Output Bit 5. 1 DA6 Output Port A Output Bit 6. 2 DA7 Output Port A Output Bit 7.

Rev. 0 | Page 9 of 36

AD9626

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Pin No. Mnemonic Description

3 DA8 Output Port A Output Bit 8. 4 DA9 Output Port A Output Bit 9. 5 DA10 Output Port A Output Bit 10. 6 DA11 (MSB) Output Port A Output Bit 11 (MSB). 9 OVRA Output Port A Overrange Output Bit. 10 DB0 (LSB) Output Port B Output Bit 0 (LSB). 11 DB1 Output Port B Output Bit 1. 12 DB2 Output Port B Output Bit 2. 13 DB3 Output Port B Output Bit 3. 14 DB4 Output Port B Output Bit 4. 15 DB5 Output Port B Output Bit 5. 16 DB6 Output Port B Output Bit 6. 17 DB7 Output Port B Output Bit 7. 18 DB8 Output Port B Output Bit 8. 19 DB9 Output Port B Output Bit 9. 20 DB10 Output Port B Output Bit 10. 21 DB11 (MSB) Output Port B Output Bit 11 (MSB). 22 OVRB Output Port B Overrange Output Bit.

1

AGND and DRGND should be tied to a common quiet ground plane.

Rev. 0 | Page 10 of 36

AD9626

V

C

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EQUIVALENT CIRCUITS

CLK+

10kΩ 10kΩ

Figure 5. Clock Inputs

AVDD

1.2V

CLK–

SB

07099-003

Figure 8. Equivalent CSB Input Circuit

AVDD

26kΩ

1kΩ

07099-006

1kΩ

DRVDD

DRGND

7099-052

07099-007

BUF

CML

AVDD

= ~1.4 V)

V

CML

~1.4V

7099-004

07099-005

IN+

AVDD

VIN–

Figure 6. Analog Inputs (V

SCLK/DFS

RESET

PDWN

BUF

2kΩ

BUF

1kΩ

30kΩ

Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit

Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−)

DRVDD

SDIO/DCS

Figure 10. Equivalent SDIO/DCS Input Circuit

Rev. 0 | Page 11 of 36

ANALOG DEVICES AD9626 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS