ANALOG DEVICES AD9608 Service Manual

10-Bit, 125/105 MSPS, 1.8 V Dual

A

V

FEATURES

1.8 V analog supply operation

1.8 V CMOS or 1.8 V LVDS output SNR = 61.7 dBFS at 70 MHz SFDR = 85 dBc at 70 MHz Low power: 71 mW/channel ADC core at 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.13 LSB Serial port control options

Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data

alignment

APPLICATIONS

Communications Diversity radio systems I/Q demodulation systems Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound

Analog-to-Digital Converter (ADC)

AD9608

FUNCTIONAL BLOCK DIAGRAM

DCS

SPI

CSB

MUX OPTION

CONTROLS

PDWN DFSCLK+ CLK–

MODE

CMOS/LVDS

OEB

ORA

D9A

D0A

OUTPUT BUFFER

DCOA

DRVDD

ORB

D9B

D0B

OUTPUT BUFFER

DCOB

1

GND

DD SCLK

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.

REF

SELECT

ADC

DIVIDE 1TO 8

SYNC

SDIO

PROGRAMMING DATA

AD9608

DUTY CYCLE

STABILIZER

Figure 1.

PRODUCT HIGHLIGHTS

1. Operates from a single 1.8 V analog power supply and

features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families.

2. Provides a patented sample-and-hold circuit that maintains

excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.

3. Includes a standard serial port interface that supports various

product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing, and offset adjustments.

4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin

compatible with the AD9650, AD9269, and AD9268 16-bit ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628 and AD9231 12-bit ADCs, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

09977-001

1

This product is protected by a U.S. patent.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9608

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9608

GENERAL DESCRIPTION

The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus.

AD9608 is available in a 64-lead RoHS-compliant LFCSP and

The is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.

Rev. 0 | Page 3 of 40

AD9608

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 1.

AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION Full 10 10 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full −1.0 −0.3 +0.4 −1.0 −0.3 +0.4 % FSR Gain Error Full −2.8 ±1.5 +9.0 −2.8 ±1.5 +9.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.35 ±0.35 LSB

25°C ±0.12 ±0.13 LSB

Integral Nonlinearity (INL)1 Full ±0.40 ±0.40 LSB 25°C ±0.14 ±0.14 LSB MATCHING CHARACTERISTIC

Offset Error Full ±0.1 ±1.0 ±0.1 ±1.0 % FSR

Gain Error Full ±0.5 ±6.5 ±0.5 ±6.5 % FSR TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V

Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.08 0.08 LSB rms ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p

Input Capacitance2 Full 5 5 pF

Input Resistance (Differential) Full 7.5 7.5 kΩ

Input Common-Mode Voltage Full 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

I

AVDD

1

I

(1.8 V CMOS)

DRVDD

1

I

(1.8 V LVDS)

DRVDD

POWER CONSUMPTION

DC Input Full 125 141 mW

Sine Wave Input1 (DRVDD = 1.8 V CMOS Output Mode)

Sine Wave Input1 (DRVDD = 1.8 V LVDS Output Mode)

Standby Power3 Full

Power-Down Power Full 2.0 2.0 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).

Full 76.8 82.0 87.7 93.0 mA Full 14.7 17.4 mA Full 48.5 49.7 mA

Full 165 174 189 199 mW Full 226 247 mW

108

120 mW

Rev. 0 | Page 4 of 40

AD9608

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 2.

AD9608-105 AD9608-125 Parameter1 Temp Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 9.7 MHz 25°C 61.7 61.7 dBFS fIN = 30.5 MHz 25°C 61.7 61.7 dBFS fIN = 70 MHz 25°C 61.7 61.7 dBFS Full 61.3 61.3 dBFS

fIN = 100 MHz fIN = 200 MHz 25°C 61.4 61.4 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 61.6 61.6 dBFS fIN = 30.5 MHz 25°C 61.6 61.6 dBFS fIN = 70 MHz 25°C 61.6 61.6 dBFS Full 61.1 61.1 dBFS fIN = 100 MHz 25°C 61.5 61.5 dBFS fIN = 200 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) CROSSTALK2 ANALOG INPUT BANDWIDTH

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

25°C 61.6 61.6 dBFS

25°C 25°C 25°C 25°C 25°C

25°C 25°C 25°C Full 25°C 25°C

25°C Full 25°C

61.3

−90 −90

−89 −89

−75 −75

−89 −89

−84 −84

85 85 85 85 85 85 75 75 85 85 84 84

−85 −85

−75 −75

−85 −85

82 82

−95 −95 650 650

9.9

61.3

9.9

dBFS

Bits Bits Bits Bits Bits

dBc dBc dBc dBc dBc dBc

dBc dB MHz

Rev. 0 | Page 5 of 40

AD9608

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 3.

Parameter Temp Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS/SYNC)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT/OUTPUT (SDIO/DCS)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

Rev. 0 | Page 6 of 40

AD9608

Parameter Temp Min Typ Max Unit

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 4.

AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 1000 1000 MHz

Conversion Rate1

DCS Enabled Full 20 105 20 125 MSPS

DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH) Full 4.76 4 ns Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 ps rms

DATA OUTPUT PARAMETERS

CMOS Mode CMOS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

LVDS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 2.4 DCO Propagation Delay (t DCO to Data Skew (t

SKEW

CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B Wake-Up Time (Power-Down)3 Full 350 350 μs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Ta ). ble 18

3

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 9.52 8 ns

CLK

)2 Full 2.0 3.1 4.4 2.0 3.1 4.4 ns

DCO

) Full −1.2

)2 Full

DCO

4.4 4.4

−0.1

+1.0 −1.2

−0.1

+1.0 ns

2.4 ns ns

) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns

Full 16/16.5 16/16.5 Cycles

Rev. 0 | Page 7 of 40

AD9608

TIMING SPECIFICATIONS

Table 5.

Parameter Descriptions Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

SSYNC

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 40 ns min t

Period of the SCLK 2 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 10 ns min t

SCLK pulse width high 10 ns min

HIGH

t

SCLK pulse width low 10 ns min

LOW

t

EN_SDIO

t

DIS_SDIO

Timing Diagrams

CH A/CH B DATA

CLK+

CLK–

DCOA/DCOB

VIN

CLK+

CLK–

DCOA/DCOB

CH A DATA

CH B DATA

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

VIN

N – 1

t

CH

Figure 2. CMOS Default Output Mode Data Output Timing

N – 1

t

CH

Figure 3. CMOS Interleaved Output Mode Data Output Timing

t

A

N

t

CLK

t

DCO

t

N – 16N – 17

t

PD

t

A

N

t

CLK

t

DCO

t

SKEW

CH A

N – 16

t

PD

CH B

N – 16

Rev. 0 | Page 8 of 40

SKEW

N + 1

CH B

N – 15

CH A

N – 15

N + 3

N + 2

N – 15 N – 14 N – 13 N – 12

N + 3

N + 2

CH A

CH B

CH A

CH B

N – 14

CH B

N – 14

N – 13

CH A

N – 13

N – 12

CH B

N – 12

N – 11

CH A

N – 11

CH A

N – 10

CH B

N – 10

N + 4

CH B N – 9

CH A N – 9

CH A N – 8

CH B N – 8

N + 5

10 ns min

2 ns min

09977-002

09977-003

AD9608

VIN

CLK+

N – 1

t

A

N

N + 1

t

CH

t

CLK

N + 2

N + 3

N + 4

N + 5

CLK–

t

DCO

t

PD

CH A

N – 16

CH A

N – 16

CH A0 N – 16

CH A8 N – 16

CH B0 N – 16

CH B8 N – 16

SKEW

CH B

N – 16

CH B

N – 16

CH A1 N – 16

CH A9 N – 16

CH B1

N – 16

CH B9

N – 16

CH A

N – 15

CH A

N – 15

CH A0 N – 15

CH A8 N – 15

CH B0 N – 15

CH B8 N – 15

CH B

N – 15

CH B

N – 15

CH A1 N – 15

CH A9 N – 15

CH B1 N – 15

CH B9 N – 15

CH A

N – 14

CH A

N – 14

CH A0 N – 14

CH A8 N – 14

CH B0 N – 14

CH B8 N – 14

CH B

N – 14

CH B

N – 14

CH A1 N – 14

CH A9 N – 14

CH B1 N – 14

CH B9 N – 14

CH A

N – 13

CH A

N – 13

CH A0 N – 13

CH A8 N – 13

CH B0 N – 13

CH B8 N – 13

CH B

N – 13

CH B

N – 13

CH A1 N – 13

CH A9 N – 13

CH B1 N – 13

CH B9 N – 13

CH A

N – 12

CH A

N – 12

CH A0 N – 12

CH A8 N – 12

CH B0 N – 12

CH B8 N – 12

09977-004

PARALLEL

INTERLEAVED

MODE

CHANNEL

MULTIPLEXED

MODE

CHANNEL A

CHANNEL

MULTIPLEXED

MODE

CHANNEL B

DCO–

DCO+

D0+ (LSB)

D0– (LSB)

D9+ (MSB)

D9– (MSB)

D1+/D0+ (LSB)

D1–/D0– (LSB)

D9+/D8+ (MSB)

D9–/D8– (MSB)

D1+/D0+ (LSB)

D1–/D0– (LSB)

D9+/D8+ (MSB)

D9–/D8– (MSB)

Figure 4. LVDS Modes for Data Output Timing

CLK+

t

SSYNC

t

HSYNC

SYNC

09977-005

Figure 5. SYNC Input Timing Requirements

Rev. 0 | Page 9 of 40

AD9608

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

1

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V OEB −0.3 V to DRVDD + 0.2 V PDWN −0.3 V to DRVDD + 0.2 V D0A, D0B through D9A, D9B to AGND −0.3 V to DRVDD + 0.2 V DCOA, DCOB to AGND −0.3 V to DRVDD + 0.2 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

1

The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +

0.2 V but should not exceed 2.1 V.

Package Typ e

64-Lead LFCSP 9 mm × 9 mm (CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown Tabl e 7, airflow improves heat dissipation, which reduces θ package leads from metal traces, through holes, ground, and power planes reduces θ

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Airflow Veloc ity (m/sec) θ

1, 2

1, 3

θ

JA

JC

1, 4

θ

JB

1, 2

Ψ

JT

Unit

0 22.3 1.4 N/A 0.1 °C/W

1.0 19.5 N/A 11.8 0.2 °C/W

2.5 17.5 N/A N/A 0.2 °C/W

. In addition, metal in direct contact with the

JA

.

JA

Rev. 0 | Page 10 of 40

AD9608

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVD D

VIN+B

VIN–B

AVD D

RBIAS

VCM

SENSE

VREF

AVD D

VIN–A

VIN+A

AVD D

49

PDWN

48

OEB

47

CSB

46

SCLK/DFS

45

SDIO/DCS

44

ORA

43

D9A (MSB)

42

D8A

41

D7A

40

D6A

39

D5A

38

DRVDD

37

D4A

36

D3A

35

D2A

34

D1A

33

CLK+ CLK–

SYNC

NC NC NC NC NC NC

DRVDD

D0B (LSB)

D1B D2B D3B D4B D5B

646362616059585756555453525150

PIN 1

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AD9608

PARALLEL CMO S

TOP VIEW

(Not to Scal e)

171819202122232425262728293031

D8B

D6B

D7B

DRVDD

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THI S PIN.

2. THE EXP OSED THERMAL PAD ON THE BOTTO M OF THE PACKAGE PROVIDES

THE ANALOG GRO UND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED T O GROUND F OR PROPER OPERATIO N.

NCNCNC

ORB

DCOA

DCOB

D9B (MSB)

NCNCNC

DRVDD

32

D0A (LSB)

09977-006

Figure 6. Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54,

AVDD Supply Analog Power Supply (1.8 V Nominal).

59, 60, 63, 64 4, 5, 6, 7, 8, 9,

NC No Connect. Do not connect to this pin. 25, 26, 27, 29, 30, 31

0

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground

for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement.

Rev. 0 | Page 11 of 40

AD9608

Pin No. Mnemonic Type Description

Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 32 D0A (LSB) Output Channel A CMOS Output Data. 33 D1A Output Channel A CMOS Output Data. 34 D2A Output Channel A CMOS Output Data. 35 D3A Output Channel A CMOS Output Data. 36 D4A Output Channel A CMOS Output Data. 38 D5A Output Channel A CMOS Output Data. 39 D6A Output Channel A CMOS Output Data. 40 D7A Output Channel A CMOS Output Data. 41 D8A Output Channel A CMOS Output Data. 42 D9A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 11 D0B (LSB) Output Channel B CMOS Output Data. 12 D1B Output Channel B CMOS Output Data. 13 D2B Output Channel B CMOS Output Data. 14 D3B Output Channel B CMOS Output Data. 15 D4B Output Channel B CMOS Output Data. 16 D5B Output Channel B CMOS Output Data. 17 D6B Output Channel B CMOS Output Data. 18 D7B Output Channel B CMOS Output Data. 20 D8B Output Channel B CMOS Output Data. 21 D9B (MSB) Output Channel B CMOS Output Data. 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.

48 PDWN Input

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

Rev. 0 | Page 12 of 40

ANALOG DEVICES AD9608 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS