ANALOG DEVICES AD9559 Service Manual

Line Card Adaptive Clock Translator

AD9559

Rev. 0

Trademarks and registered trademarks are the prop erty of their respective owners.

REFERENCE

INPUT

MONITOR

AND MUX

STABLE

SOURCE

DIGITAL

PLL 0

DIGITAL

PLL 1

CLOCK

MULTIPLIER

ANALOG

PLL 0

ANALOG

PLL 1

÷3 TO ÷11

HF DIVIDER 0

÷3 TO ÷11

HF DIVIDER 1

EEPROM

SERIAL INTERFACE

(SPI OR I

2

C)

STATUS AND

CONTROL PINS

CHANNEL 0B

DIVIDER

CHANNEL 0A

DIVIDER

CHANNEL 1A

DIVIDER

CHANNEL 1B

DIVIDER

AD9559

10644-001

Data Sheet

FEATURES

Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually

no disturbance on output phase

Supports Telcordia GR-253 jitter generation, transfer, and

tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback

dividers for use in OTN mapping/demapping applications Dual digital PLL architecture with four reference inputs

(single-ended or differential) 4x2 crosspoint allows any reference input to drive either PLL Input reference frequencies from 2 kHz to 1250 MHz Reference validation and frequency monitoring (2 ppm) Programmable input reference switchover priority 20-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a

single differential LVDS/HSTL output or as 2 single-ended

CMOS outputs Output frequencies: 262 kHz to 1250 MHz Programmable 17-bit integer and 24-bit fractional

feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths

from 0.1 Hz to 2 kHz Low noise system clock multiplier Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles

Dual PLL, Quad Input, Multiservice

Pin program function for easy frequency translation

configuration Software controlled power-down 72-lead (10 mm × 10 mm) LFCSP package

APPLICATIONS

Network synchronization, including synchronous Ethernet

and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient

control Wireless base station controllers Cable infrastructure Data communications

GENERAL DESCRIPTION

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The

AD9559 generates an output clock synchronized to up to four

external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9559 operates over an industrial temperature range of

−40°C to +85°C. If a single DPLL version of this part is needed, refer to the

AD9557.

FUNCTIONAL BLOCK DIAGRAM

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subj ect to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

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AD9559 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Supply Voltage ............................................................................... 4

Supply Current .............................................................................. 4

Power Dissipation ......................................................................... 5

System Clock Inputs (XOA, XOB) ............................................. 5

Reference Inputs ........................................................................... 6

Reference Monitors ...................................................................... 7

Reference Switchover Specifications .......................................... 7

Distribution Clock Outputs ........................................................ 8

Time Duration of Digital Functions ........................................ 10

Digital PLL (DPLL_0 and DPLL_1) ........................................ 10

Analog PLL (APLL_0 and APLL_1) ........................................ 10

Digital PLL Lock Detection ...................................................... 10

Holdover Specifications ............................................................. 10

Serial Port Specifications—SPI Mode ...................................... 11

Serial Port Specifications—I2C Mode ...................................... 12

Logic Inputs (

Logic Outputs (M5 to M0) ........................................................ 12

Jitter Generation ......................................................................... 13

Absolute Maximum Ratings .......................................................... 16

ESD Caution ................................................................................ 16

Pin Configuration and Function Descriptions ........................... 17

Typical Performance Characteristics ........................................... 20

Input/Output Termination Recommendations .......................... 26

Getting Started ................................................................................ 27

Chip Power Monitor and Startup ............................................. 27

Multifunction Pins at Reset/Power-Up ................................... 27

Device Register Programming Using a Register Setup File .. 27

Register Programming Overview ............................................. 28

Theory of Operation ...................................................................... 31

Overview ...................................................................................... 31

Reference Input Physical Connections .................................... 32

Reference Monitors .................................................................... 32

Reference Input Block ................................................................ 32

Reference Switchover ................................................................. 33

RESET

, M5 to M0) ............................................. 12

Rev. 0 | Page 2 of 120

Digital PLL (DPLL) Core .......................................................... 34

Loop Control State Machine ..................................................... 36

System Clock (SYSCLK) ................................................................ 37

SYSCLK Inputs ........................................................................... 37

SYSCLK Multiplier ..................................................................... 37

Output PLL (APLL) ....................................................................... 39

APLL Configuration .................................................................. 39

APLL Calibration ....................................................................... 39

Clock Distribution .......................................................................... 40

Clock Dividers ............................................................................ 40

Output Enable ............................................................................. 40

Output Mode and Power-Down ............................................... 40

Clock Distribution Synchronization ........................................ 41

Status and Control .......................................................................... 42

Multifunction Pins (M0 to M5) ............................................... 42

IRQ Function .............................................................................. 42

Watchd o g Tim e r ......................................................................... 43

EEPROM ..................................................................................... 43

Serial Control Port ......................................................................... 49

SPI/I²C Port Selection ................................................................ 49

SPI Serial Port Operation .......................................................... 49

I²C Serial Port Operation .......................................................... 53

Programming the I/O Registers ................................................... 56

Buffered/Active Registers .......................................................... 56

Write Detect Registers ............................................................... 56

Autoclear Registers ..................................................................... 56

Register Access Restrictions ...................................................... 56

Thermal Performance .................................................................... 57

Power Supply Partitions ................................................................. 58

3.3 V Supplies .............................................................................. 58

1.8 V Supplies .............................................................................. 58

Bypass Capacitors for Pin 21 and Pin 33 ................................. 58

Register Map ................................................................................... 59

Register Map Bit Descriptions ...................................................... 72

Serial Control Port Configuration (Register 0x0000 to

Register 0x0005) ......................................................................... 72

Clock Part Family ID (Register 0x000C and

Register 0x000D) ........................................................................ 72

User Scratchpad (Register 0x000E and Register 0x000F) ..... 73

General Configuration (Register 0x0100 to

Register 0x0109) ......................................................................... 73

Data Sheet AD9559

IRQ Mask (Register 0x010A to Register 0x112) ..................... 74

System Clock (Register 0x0200 to Register 0x0207) .............. 76

Reference Input A (Register 0x0300 to Register 0x031A) ..... 77

Reference Input B (Register 0x0320 to Register 0x033A) ...... 78

Reference Input C (Register 0x0340 to Register 0x035A) ..... 79

Reference Input D (Register 0x0360 to Register 0x037A) ..... 81

DPLL_0 Controls (Register 0x0400 to Register 0x0415) ....... 82

APLL_0 Configuration (Register 0x0420 to

Register 0x0423) .......................................................................... 84

PLL_0 Output Sync and Clock Distribution

(Register 0x0424 to Register 0x042E) ....................................... 85

DPLL_0 Settings for Reference Input A (REFA)

(Register 0x0440 to Register 0x044C) ...................................... 87

DPLL_0 Settings for Reference Input B (REFB)

(Register 0x044D to Register 0x0459) ...................................... 88

DPLL_0 Settings for Reference Input C (REFC)

(Register 0x045A to Register 0x0466) ...................................... 89

DPLL_0 Settings for Reference Input D (REFD)

(Register 0x0467 to Register 0x0473) ....................................... 90

DPLL_1 Controls (Register 0x0500 to Register 0x0515) ....... 91

APLL_1 Configuration (Register 0x0520 to

Register 0x0523) .......................................................................... 93

PLL_1 Output Sync and Clock Distribution

(Register 0x0524 to Register 0x052E) ....................................... 94

DPLL_1 Settings for Reference Input C (REFC)

(Register 0x0540 to Register 0x054C) ...................................... 96

DPLL_1 Settings for Reference Input D (REFD)

(Register 0x054D to Register 0x0559) ...................................... 97

DPLL_1 Settings for Reference Input A (REFA)

(Register 0x055A to Register 0x0566) ...................................... 98

DPLL_1 Settings for Reference Input B (REFB)

(Register 0x0567 to Register 0x0573) ....................................... 99

Digital Loop Filter Coefficients (Register 0x0800 to

Register 0x0817) ........................................................................ 100

Common Operational Controls (Register 0x0A00 to

Register 0x0A0E) ...................................................................... 101

PLL_0 Operational Controls (Register 0x0A20 to

Register 0x0A24) ....................................................................... 104

PLL_1 Operational Controls (Register 0x0A40 to

Register 0x0A44) ....................................................................... 106

Status ReadBack (Register 0x0D00 to Register 0x0D05) ..... 107

IRQ Monitor (Register 0x0D08 to Register 0x0D10) .......... 108

PLL_0 Read-Only Status (Register 0x0D20 to

Register 0x0D2A) ...................................................................... 110

PLL_1 Read-Only Status (Register 0x0D40 to

Register 0x0D4A) ...................................................................... 112

EEPROM Control (Register 0x0E00 to Register 0x0E03) ... 113

EEPROM Storage Sequence (Register 0x0E10 to

Register 0x0E3C) ....................................................................... 113

Outline Dimensions ...................................................................... 120

Ordering Guide ......................................................................... 120

REVISION HISTORY

7/12—Revision 0: Initial Version

Rev. 0 | Page 3 of 120

AD9559 Data Sheet

VDD

1.71

1.80

1.89 V

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD3 = 3.3 V; VDD = 1.8 V; T

SUPPLY VOLTAGE

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE

VDD3 3.135 3.30 3.465 V

SUPPLY CURRENT

The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Tab l e 1. The test conditions for the typical (typ) supply current are at the typical supply voltage found in Tabl e 1. The test conditions for the minimum (min) supply current are at the minimum supply voltage found in Table 1.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT FOR TYPICAL CONFIGURATION

I

34 42 50 mA

VDD3

I

253 316 380 mA

VDD

SUPPLY CURRENT FOR ALL BLOCKS RUNNING

CONFIGURATION I

75 94 113 mA

VDD3

I

256 320 384 mA

VDD

= 25°C, unless otherwise noted.

A

Typical values are for the Typical Configuration parameter listed in Table 3

Maximum values are for the All Blocks Running parameter listed in Table 3

Rev. 0 | Page 4 of 120

Data Sheet AD9559

POWER DISSIPATION

All Blocks Running

0.71

0.89

1.1

W

SYSTEM CLOCK REFERENCE INPUT PATH

POWER DISSIPATION

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

Typical Configuration 0.57 0.71 0.85 W

Full Power-Down 75 110 mW

Incremental Power Dissipation

Complete DPLL/APLL On/Off 171 214 257 mW

Input Reference On/Off

Differential Without Divide-by-2 19 25 31 mW Additional current draw is in the VDD3 domain only Differential With Divide-by-2 25 32 39 mW Additional current draw is in the VDD3 domain only Single-Ended (Without Divide-by-2) 5 6.6 8 mW Additional current draw is in the VDD3 domain only

Output Distribution Driver On/Off

LVDS (at 750 MHz) 12 17 22 mW Additional current draw is in the VDD domain only HSTL (at 750 MHz) 14 21 28 mW Additional current draw is in the VDD domain only

1.8 V CMOS (at 250 MHz) 14 21 28 mW A single 1.8 V CMOS output with an 80 pF load

3.3 V CMOS (at 250 MHz) 18 27 36 mW A single 3.3 V CMOS output with an 80 pF load

System clock: 49.152 MHz crystal; two DPLLs active; two 19.44 MHz input references in differential mode; two HSTL drivers at 644.53125 MHz; two 3.3 V CMOS drivers at 161.1328125 MHz and 80 pF capacitive load on CMOS output

System clock: 49.152 MHz crystal; two DPLLs active, all input references in differential mode; two HSTL drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive load on CMOS outputs

Typical configuration with no external pull-up or pulldown resistors; about 2/3 of this power is on VDD3

Typical configuration; table values show the change in power due to the indicated operation

This power delta is computed relative to the typical configuration; the blocks powered down include one reference input, one DPLL, one APLL, one P divider, two channel dividers, one HSTL driver, and one CMOS driver; roughly 2/3 of the power savings is on the 1.8 V supply

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

PLL Output Frequency Range 750 805 MHz

Phase Frequency Detector (PFD) Rate 150 MHz Frequency Multiplication Range 4 255 Assumes valid system clock and PFD rates

Input Frequency Range 10 400 MHz Minimum Input Slew Rate 50 V/μs

Common-Mode Voltage 1.05 1.16 1.27 V Internally generated Differential Input Voltage Sensitivity 250 mV p-p

System Clock Input Doubler Duty Cycle

System Clock input = 50 MHz 45 50 55 % System Clock input = 20 MHz 46 50 54 %

System Clock input = 16 MHz to 20 MHz 47 50 53 % Input Capacitance 3 pF Single-ended, each pin Input Resistance 4.1 kΩ

Rev. 0 | Page 5 of 120

VCO range may place limitations on nonstandard system clock input frequencies

Minimum limit imposed for jitter performance; jitter performance affected if sine wave input ≤ 20 MHz

Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed supply rails; single-ended input can be accommodated by ac grounding complementary input; 1 V p-p recommended for optimal jitter performance

Amount of duty cycle variation that can be tolerated on the system clock input to use the doubler

AD9559 Data Sheet

Sinusoidal Input

10 750

MHz

fIN = 800 MHz to 1050 MHz

320

mV

LVPECL

390

ps

Input Voltage High (VIH)

1.8 V to 2.5 V Threshold Setting

0.5 V

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL RESONATOR PAT H

Crystal Resonator Frequency Range 10 50 MHz Fundamental mode, AT cut crystal Maximum Crystal Motional Resistance 100 Ω

REFERENCE INPUTS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

LVPECL Input 0.002 1250 MHz

LVDS Input 0.002 750 MHz Minimum Input Slew Rate 40 V/μs Minimum limit imposed for jitter performance Common-Mode Input Voltage

AC-Coupled 1.9 2 2.1 V Internally generated

DC-Coupled 1.0 2.4 V Differential Input Voltage Sensitivity mV

fIN < 800 MHz 240 mV

The reference input divide-by-2 block must be engaged

> 705 MHz

for f

IN

Minimum differential voltage across pins required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails

fIN = 1050 MHz to 1250 MHz 400 mV Differential Input Voltage Hysteresis 55 100 mV Input Resistance 21 kΩ Input Capacitance 3 pF Minimum Pulse Width High

LVDS 640 ps Minimum Pulse Width Low

LVPECL 390 ps

LVDS 640 ps

SINGLE-ENDED OPERATION

Frequency Range (CMOS) 0.002 300 MHz Minimum Input Slew Rate 40 V/μs Minimum limit imposed for jitter performance

1.2 V to 1.5 V Threshold Setting 1.0 V

1.8 V to 2.5 V Threshold Setting 1.4 V

3.0 V to 3.3 V Threshold Setting 2.0 V

Input Voltage Low (VIL)

1.2 V to 1.5 V Threshold Setting 0.35 V

3.0 V to 3.3 V Threshold Setting 1.0 V Input Resistance 47 kΩ Input Capacitance 3 pF Minimum Pulse Width High 1.5 ns Minimum Pulse Width Low 1.5 ns

Rev. 0 | Page 6 of 120

Data Sheet AD9559

REFERENCE MONITORS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

Reference Monitor

Loss of Reference Detection Time 1.15

DPLL PFD

Nominal phase detector period = R/f

period

Frequency Out-of Range Limits 2 105

Δf/f

REF

(ppm)

Programmable (lower bound subject to quality of the system clock (SYSCLK)); SYSCLK accuracy must be less than the lower bound

Validation Timer 0.001 65.535 sec Programmable in 1 ms increments

1

f

is the frequency of the active reference; R is the frequency division factor determined by the R divider.

REF

REFERENCE SWITCHOVER SPECIFICATIONS

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

50 Hz DPLL Loop Bandwidth

Peak ±55 ±100 ps Steady State ±55 ±100 ps

Time Required to Switch to a New Reference

Phase Build-Out Switchover 10

DPLL PFD period

Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements; base loop filter selection bit set to 1b for all active references

Tes t conditions: 19.44 MHz to 174.70308 MHz; DPLL BW = 50 Hz; 49.152 MHz signal generator used for system clock source

Calculated using the nominal phase detector period (NPDP = R/f

); the total time required

REF

is the time plus the reference validation time, plus the time required to lock to the new reference

REF

1

Rev. 0 | Page 7 of 120

AD9559 Data Sheet

HSTL MODE

Up to f

= 700 MHz

44

48

53 %

0.262

1250

MHz

Up to f

= 800 MHz

42.5

48

53.5 %

1.8 V Supply

0.302

250

MHz

10 pF load

DISTRIBUTION CLOCK OUTPUTS

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

Output Frequency

OUT0A, OUT0A and OUT0B, OUT0B

OUT1A, OUT1A and OUT1B, OUT1B Rise/Fall Time (20% to 80%)1 140 250 ps 100 Ω termination across the output pair Duty Cycle

OUT

Up to f

Up to f Differential Output Voltage Swing

= 750 MHz 43 48 54 %

OUT

= 1250 MHz 43 %

OUT

Common-Mode Output Voltage 750 850 1000 mV Output driver static Reference Input-to-Output Delay Variation

over Temperature

Static Phase Offset Variation from Active

Reference to Output over Voltage

Extremes

LVDS MODE

Output Frequency

OUT0A, OUT0A and OUT0B, OUT0B

OUT1A, OUT1A and OUT1B, OUT1B Rise/Fall Time (20% to 80%)1 185 280 ps 100 Ω termination across the output pair Duty Cycle

Up to f

Up to f Differential Output Voltage Swing

= 750 MHz 43 48 53 %

OUT

= 1250 MHz 43 %

OUT

Balanced, VOD 247 454 mV

Unbalanced, ΔVOD 50 mV

Offset Voltage

Common Mode, VOS 1.125 1.25 1.375 V Output driver static

Common-Mode Difference, ΔVOS 50 mV

Short-Circuit Output Current 10 24 mA Output driver static

CMOS MODE

Output Frequency

0.262 1250 MHz

0.302 1250 MHz

700 925 1200 mV

3.2 ps/°C

0.875 ps/mV

0.302 1250 MHz

Magnitude of voltage across pins; output driver static

HSTL mode; DPLL locked to same input reference at all times; stable system clock source (non-XTAL)

Valid for HSTL, LVDS, and 1.8 V CMOS output driver modes

Voltage swing between output pins; output driver static

Absolute difference between voltage swing of normal pin and inverted pin; output driver static

Voltage difference between pins; output driver static

OUT0A, OUT0A and OUT0B, OUT0B OUT1A, OUT1A and OUT1B, OUT1B

0.262 250 MHz 10 pF load

0.302 250 MHz 10 pF load

3.3 V Supply (OUT0A and OUT1A) Strong Drive Strength Setting

OUT0A, OUT0A

0.262 250 MHz 10 pF load

OUT1A, OUT1A

Weak Drive Strength Setting

OUT0A, OUT0A OUT1A, OUT1A

0.262 25 MHz 10 pF load

0.302 25 MHz 10 pF load

Rev. 0 | Page 8 of 120

Data Sheet AD9559

Duty Cycle

VDD3 = 3.3 V, IOH = 1 mA

VDD3 − 0.1

V

Parameter Min Typ Max Unit Test Conditions/Comments

Rise/Fall Time (20% to 80%)1

1.8 V Mode 1.5 3 ns 10 pF load

3.3 V Strong Mode 0.4 0.6 ns 10 pF load

3.3 V Weak Mode 8 ns 10 pF load

1.8 V Mode 50 % 10 pF load

3.3 V Strong Mode 47 51 56 % 10 pF load

3.3 V Weak Mode 51 % 10 pF load

Output Voltage High (VOH) Output driver static; strong drive strength

VDD3 = 3.3 V, IOH = 10 mA VDD3 − 0.3 V

VDD3 = 1.8 V, IOH = 1 mA VDD − 0.2 V

Output Voltage Low (VOL) Output driver static; strong drive strength

VDD3 = 3.3 V, IOL = 10 mA 0.3 V VDD3 = 3.3 V, IOL = 1 mA 0.1 V VDD3 = 1.8 V, IOL = 1 mA 0.1 V

OUTPUT TIMING SKEW 10 pF load

Between OUT0A, OUT0A and OUT0B, OUT0B

or OUT1A, OUT1A and OUT1B, OUT1B

Additional Delay on One Driver by

Changing Its Logic Type HSTL to LVDS 0 +15 +35 ps

HSTL to 1.8 V CMOS −5 0 +5 ps

OUT0B, OUT0B HSTL to OUT0B, OUT0B

3.3 V CMOS, Strong Mode

OUT1B, OUT1B HSTL to OUT1B, OUT1B

3.3 V CMOS, Strong Mode

1

The listed values are for the slower edge (rising or falling).

116 265 ps

HSTL mode on both drivers; rising edge only; any divide value

Positive value indicates that the LVDS edge is delayed relative to HSTL

Positive value indicates that the CMOS edge is delayed relative to HSTL

−765 −280 +250 ns The CMOS edge is delayed relative to HSTL

Rev. 0 | Page 9 of 120

AD9559 Data Sheet

Closed Loop Peaking

<0.1

dB

Programmable design parameter; part can be programmed

TIME DURATION OF DIGITAL FUNCTIONS

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

TIME DURATION OF DIGITAL FUNCTIONS

EEPROM-to-Register Download Time 16 25 ms Uses default EEPROM storage sequence (see Register 0x0E10

Register-to-EEPROM Upload Time 180 ms Uses default EEPROM storage sequence (see Register 0x0E10

Power-Down Exit Time

1

ms Time from power-down exit to system clock lock detect; system

DIGITAL PLL (DPLL_0 AND DPLL_1)

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL PLL

Phase Frequency Detector (PFD) Input

Frequency Range

Loop Bandwidth 0.1 2000 Hz Programmable design parameter;

Phase Margin 45 89 Degrees Programmable design parameter

2 100 kHz

to Register 0x0E4F)

to Register 0x0E4F

clock stability timer setting should be added to calculate the time needed for system clock stable

note that (f

for <0.1 dB peaking in accordance with Telcordia GR-253-CORE jitter transfer

/loop BW) ≥ 20

PFD

ANALOG PLL (APLL_0 AND APLL_1)

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

ANALOG PLL0

VCO Frequency Range 2940 3543 MHz Phase Frequency Detector (PFD) Input

Frequency Range Loop Bandwidth 240 kHz Programmable design parameter Phase Margin 68 Degrees Programmable design parameter

ANALOG PLL1

VCO Frequency Range 3405 4260 MHz Phase Frequency Detector (PFD) Input

Frequency Range Loop Bandwidth 240 kHz Programmable design parameter Phase Margin 68 Degrees Programmable design parameter

180 195 MHz

DIGITAL PLL LOCK DETECTION

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range 10 224 − 1 ps Reference-to-feedback phase difference Threshold Resolution 1 ps

FREQUENCY LOCK DETECTOR

Threshold Programming Range 10 224 − 1 ps Reference-to-feedback period difference Threshold Resolution 1 ps

HOLDOVER SPECIFICATIONS

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy <0.01 ppm Excludes frequency drift of SYSCLK source; excludes frequency

drift of input reference prior to entering holdover; compliant with GR-1244 Stratum 3

Rev. 0 | Page 10 of 120

Data Sheet AD9559

M5/EE CS

M5/ACS

is a dual function pin; the values in

Input Logic 0 Voltage

0.8 V

Input Logic 0 Current

1

µA

As an Input

Output Logic 1 Voltage

VDD3 − 0.6

V

1 mA load current

SCLK

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

Input Logic 1 Voltage

2.2 V

Input Logic 1 Current 20 µA Input Logic 0 Current Input Capacitance

SCLK

Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current

50 µA 2 pF Internal 10 kΩ pull-down resistor

2.2 V

0.8 V 200 µA

Input Capacitance 2 pF

SDIO

E

A

this table apply when this pin is used as a serial port pin, that is, ACS

EE

A

; see Table 16 for the specifications when this pin is used as a multifunction pin (M5)

Input Logic 1 Voltage 2.2 V Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance

As an Output

Output Logic 1 Voltage Output Logic 0 Voltage

M4/SDO

0.8 V 1 µA 1 µA 2 pF

VDD3 − 0.6 V 1 mA load current

0.4 V 1 mA load current M4/SDO is a dual function pin; the values in

this table apply when this pin is used as a serial port pin, that is SDO; see Table 16 for the specifications when this pin is used as a multifunction pin (M4)

Output Logic 0 Voltage 0.4 V 1 mA load current

TIMING

Clock Rate, 1/t Pulse Width High, t

Pulse Width Low, t SDIO to SCLK Setup, t SCLK to SDIO Hold, t

40 MHz

CLK

HIGH

LOW

DS

DH

SCLK to Valid SDIO and SDO, t

EE

AA

AACS

to SCLK Setup (tS)

EE

AA

AACS

to SCLK Hold (tC)

EE

AA

AACS

Minimum Pulse Width High

10 ns

13 ns

3 ns

6 ns

See Figure 47 and Figure 50

10 ns

DV

10 ns 0 ns 6 ns

Rev. 0 | Page 11 of 120

AD9559 Data Sheet

Input Logic 1 Voltage

0.7 × VDD3

V

SERIAL PORT SPECIFICATIONS—I2C MODE

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

SDA, SCL (AS INPUTS)

Input Logic 0 Voltage 0.3 × VDD3 V Input Current Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed

by the Input Filter, t

SP

SDA (AS OUTPUT)

Output Logic 0 Voltage Output Fall Time from V

IHmin

to V

20 + 0.1 C

ILmax

TIMING

SCL Clock Rate

Bus-Free Time Between a Stop and Start

Condition, t

Repeated Start Condition Setup Time, t

BUF

SU; STA

Repeated Hold Time Start Condition, t

Stop Condition Setup Time, t Low Period of the SCL Clock, t High Period of the SCL Clock, t

SCL/SDA Rise Time, t SCL/SDA Fall Time, t Data Setup Time, t Data Hold Time, t

R

20 + 0.1 C

F

100 ns

SU; DAT

100 ns

HD; DAT

Capacitive Load for Each Bus Line, C

1

Cb is the capacitance (pF) of a single bus line.

SU; STO

LOW

HIGH

1

b

−10 +10 µA For VIN = 10% to 90% of VDD3

0.015 × VDD3 50 ns

0.4 V IO = 3 mA

1

2F

250 ns 10 pF ≤ Cb ≤ 400 pF

b

400 kHz

1.3 µs

0.6 µs

0.6 µs After this period, the first clock pulse is

HD ; STA

generated

0.6 µs

1.3 µs

0.6 µs 20 + 0.1 C

1

300 ns

b

1

300 ns

b

400 pF

LOGIC INPUTS (RESET, M5 TO M0)

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

E

RESET

A

PINA Input High Voltage (V Input Low Voltage (V Input Current (I Input Capacitance (C

) 2.1 V

IH

) 0.8 V

IL

, I

) ±85 ±125 µA

INH

INL

) 3 pF

IN

LOGIC INPUTS (M5 to M0)

Input High Voltage (VIH) 2.5 V Input Low Voltage (V Input Current (I Input Capacitance (C

) 0.6 V

IL

, I

) ±1 ±5 µA

INH

INL

) 3 pF

IN

The M4 and M5 pins are dual function pins; the

values in this table apply when M4/SDO and

E

CS

A

are used as M pins; see Table 14 in the

M5/ Serial Port Specifications—SPI Mode for the specifications when these pins are used as serial port pins (SDO,

CS

A

E

A

)

LOGIC OUTPUTS (M5 TO M0)

Table 17.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTS (M5 to M0)

Output High Voltage (V Output Low Voltage (V

) VDD3 − 0.4 V IOH = 1 mA

OH

) 0.4 V IOL = 1 mA

OL

section

Rev. 0 | Page 12 of 120

Data Sheet AD9559

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Bandwidth: 12 kHz to 20 MHz

310 fs rms

Bandwidth: 20 kHz to 80 MHz

308 fs rms

Bandwidth: 12 kHz to 20 MHz

335 fs rms

JITTER GENERATION

Jitter Generation (Random Jitter)—49.152 MHz Crystal for System Clock Input

Table 18.

JITTER GENERATION System clock doubler enabled.

High phase margin mode enabled. Both PLLs are running with same output frequency. In cases where the two PLLs have different jitter, the higher jitter is listed. When two driver types are listed, both were tested at those conditions; the driver type with higher jitter is quoted, although there is usually not a significant jitter difference between driver types.

= 19.44 MHz; f

f

REF

= 622.08 MHz; f

OUT

= 50 Hz;

LOOP

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

307 fs rms

Bandwidth: 20 kHz to 80 MHz 313 fs rms Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz

= 19.44 MHz; f

f

REF

= 644.53 MHz; f

OUT

= 50 Hz;

LOOP

292 fs rms 149 fs rms

HSTL Driver, LVDS Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz

313 fs rms 306 fs rms

Bandwidth: 50 kHz to 80 MHz 286 fs rms Bandwidth: 16 MHz to 320 MHz

f

= 19.44 MHz; f

REF

= 693.48 MHz; f

OUT

= 50 Hz;

LOOP

154 fs rms

HSTL Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz

f

= 19.44 MHz; f

REF

= 174.703 MHz; f

OUT

LOOP

= 1 kHz;

335 fs rms 328 fs rms 328 fs rms 298 fs rms 150 fs rms

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

396 fs rms

Bandwidth: 20 kHz to 80 MHz 369 fs rms Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz

f

= 19.44 MHz; f

REF

LVDS Driver,

3.3 V CMOS Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz

f

= 25 MHz; f

REF

HSTL Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz

= 174.703 MHz; f

OUT

= 161.1328 MHz; f

OUT

LOOP

= 100 Hz;

LOOP

= 100 Hz;

347 fs rms 230 fs rms

337 fs rms 330 fs rms 354 fs rms 339 fs rms 220 fs rms

318 fs rms 310 fs rms 384 fs rms 361 fs rms 267 fs rms

Rev. 0 | Page 13 of 120

AD9559 Data Sheet

Bandwidth: 100 kHz to 10 MHz

256 fs rms

Bandwidth: 20 kHz to 80 MHz

373

Bandwidth: 50 kHz to 80 MHz

396

fs rms

Parameter Min Typ Max Unit Test Conditions/Comments

= 2 kHz; f

f

REF

HSTL Driver,

3.3 V CMOS Driver Bandwidth: 10Hz to 30 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz

f

= 25 MHz; f

REF

HSTL Driver

Bandwidth: 100 Hz to 500 MHz (Broadband) Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz

Jitter Generation (Random Jitter)—19.2 MHz TCXO for System Clock Input

Table 19.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

f

= 19.44 MHz; f

REF

HSTL Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz

Bandwidth: 50 kHz to 80 MHz 348 Bandwidth: 16 MHz to 320 MHz

f

= 19.44 MHz; f

REF

HSTL Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz

f

= 19.44 MHz; f

REF

HSTL Driver

Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz

f

= 25 MHz; f

REF

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 384 Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz

= 70.656 MHz; f

OUT

= 1 GHz; f

OUT

= 644.53 MHz; f

OUT

= 693.48 MHz; f

OUT

= 312.5 MHz; f

OUT

= 161.1328 MHz; f

OUT

LOOP

= 500 Hz;

LOOP

= 100 Hz;

= 10 Hz;

LOOP

= 10 Hz;

LOOP

= 10 Hz;

LOOP

= 10 Hz;

LOOP

6.5 ps rms 343 fs rms 335 fs rms 243 fs rms

881 fs rms 331 fs rms 330 fs rms

380 373

fs rms fs rms fs rms fs rms

148

fs rms

390 383 382 350 144

fs rms fs rms fs rms fs rms fs rms

398 392 400 379 172

fs rms fs rms fs rms fs rms fs rms

fs rms

378 416

fs rms fs rms

System clock doubler enabled. High phase margin mode enabled. Both PLLs are running with same output frequency. In cases where the two PLLs have different jitter, the higher jitter is listed. Where two driver types are listed, both were tested at those conditions; the driver type with higher jitter is quoted, although there is usually not a significant jitter difference between driver types.

Bandwidth: 4 MHz to 80 MHz 223

Rev. 0 | Page 14 of 120

fs rms

Data Sheet AD9559

Parameter Min Typ Max Unit Test Conditions/Comments

f

= 2 kHz; f

REF

= 70.656 MHz; f

OUT

HSTL Driver,

3.3 V CMOS Driver Bandwidth: 10 Hz to 30 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz Bandwidth: 100 kHz to 10 MHz

= 10 Hz;

LOOP

3.19 418 339 348

ps rms fs rms fs rms fs rms

Rev. 0 | Page 15 of 120

AD9559 Data Sheet

3.3 V Supply Voltage ( VDD3)

3.6 V

Junction Temperature

150°C

ABSOLUTE MAXIMUM RATINGS

Table 20.

Parameter Rating

1.8 V Supply Voltage ( VDD)

Maximum Digital Input Voltage −0.5 V to VDD3 + 0.5 V Storage Temperature Range Operating Temperature Range Lead Temperature

(Soldering 10 sec)

2 V

−65°C to +150°C

−40°C to +85°C 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 16 of 120

Data Sheet AD9559

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

VDD3 REFA REFA

VDD VDD GND VDD VDD VDD

LDO_0

LF_0

VDD3

VDD

VDD OUT0A OUT0A

17VDD 18VDD3

192021222324252627282930313233

34

OUT0B

VDD

GND

RESET

SCLK/SCL

SDIO/SDA

M5/CS

M4/SDO

VDD3

M3M2M1

M0

GND

VDD

35OUT1B

36OUT1B

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

VDD3 REFC REFC VDD VDD GND VDD VDD VDD LDO_1 LF_1 VDD3 VDD VDD OUT1A OUT1A VDD VDD3

7271706968676665646362616059585756

55

VDD3

REFB

VDD

XOA

XOB

VDD

REFD

VDD3

PIN 1 INDICATOR

AD9559

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPO S E D P AD IS THE GRO UND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTI ONALITY AND HE AT DISSIPATION, NOISE, AND M E CHANICAL STRENG TH BENEFIT S .

10644-002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 21. Pin Function Descriptions

Input/

Pin No. Mnemonic

1, 12, 18, 28,

VDD3 I Power

Output

37, 43, 54, 55, 72

2 REFA I

3

4, 5, 7, 8, 9, 13,

E

AREFA

VDD I Power

I

14, 17, 21, 34, 38, 41, 42, 46, 47, 48, 50, 51,

O

58, 59, 60, 61, 62, 65, 66, 67, 68, 69

6, 22, 33, 49 GND O Ground Connect these pins (along with the exposed die pad) to ground. 10

11

15

16

LDO_0 I LDO bypass

LF_0 I/O

AOUT0A

E

OUT0A O

Figure 2. Pin Configuration

Pi n Typ e Description

Differential input

Loop filter for APLL_0

HSTL, LVDS,

1.8 V CMOS HSTL, LVDS,

1.8 V CMOS

3.3 V Power Supply. See the Power Supply Partitions section for information about the recommended grouping of the power supply pins.

Reference A Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference A Input. Complementary signal to the input provided on Pin 2.

1.8 V Power Supply. See the Power Supply Partitions section for information about the recommended grouping of the power supply pins. Note that, for Pin 34 and Pin 21, it is recommended that a Size 0201, 0.1 µF bypass capacitor be placed between Pin 33 and Pin 34, as well as between Pin 21 and Pin 22, as close as possible to the AD9559.

Output PLL0 Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin to ground. This pin is also the ac ground reference for the integrated output PLL external loop filter.

Loop Filter Node for the Output PLL0. Connect an external 6.8 nF capacitor from this pin to Pin 10 (LDO_0).

PLL0 Complementary Output 0A. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

PLL0 Output 0A. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS. LVPECL levels can be achieved by ac-coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

Rev. 0 | Page 17 of 120

AD9559 Data Sheet

Input/

Pin No. Mnemonic

19

20

23

24

25

26

27

29, 30, 31, 32

E

AOUT0B

OUT0B O

E

ARESET

SCLK/SCL I 3.3 V CMOS

SDIO/SDA I/O 3.3 V CMOS

M5/ACSE

M4/SDO I/O 3.3 V CMOS Configurable I/O Pin (M4). Used for status and control of the AD9559.

M3, M2, M1, M0

35

36

39

40

44

45

52

53

56

57

OUT1B O

E

AOUT1B

OUT1A O

E

AOUT1A

LF_1 I/O

LDO_1 I LDO bypass

E

AREFC

REFC I

E

AREFD

REFD I

Output Pi n Typ e Description

O

HSTL, LVDS,

1.8 V CMOS,

PLL0 Complementary Output 0B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS.

3.3 V CMOS HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL0 Output 0B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac-coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

I

3.3 V CMOS Logic

Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has an internal 50 kΩ pull-up resistor.

Serial Programming Clock in SPI Mode (SCLK). Data clock for serial programming. Serial Clock Pin in I

2

C Mode (SCL).

Serial Data Input/Output (SDIO). When the device is in 4-wire SPI mode, data is written via this pin. In 3-wire SPI mode, data reads and writes both occur on this pin. There is no internal pull-up/pull-down resistor on this pin. Serial Data Pin in I2C Mode (SDA).

I/O 3.3 V CMOS Configurable I/O Pin (M5). Used for status and control of the AD9559.

Chip Select in SPI Mode (ACS

E

A

). Active low input. When programming a device in

SPI, this pin must be held low. In systems where more than one AD9559 is present, this pin enables individual programming of each AD9559. This pin has an internal 10 kΩ pull-up resistor.

Serial Data Output (SDO). In 4-wire SPI mode, this pin is used for reading serial data.

I/O 3.3 V CMOS

Configurable I/O Pins. These pins are used for status and control of the AD9559. These pins are also used at power-up and reset to control the serial port configuration and EEPROM loading. See Table 23 and Table 25 for more information. These pins do NOT have internal pull-down resistors.

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL1 Output 1B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac-coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

O

HSTL, LVDS,

1.8 V CMOS,

PLL1 Complementary Output 1B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS.

3.3 V CMOS HSTL, LVDS,

1.8 V CMOS

PLL1 Output 1A. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS. LVPECL levels can be achieved by ac-coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

O

HSTL, LVDS,

1.8 V CMOS Loop filter for

APLL_1

PLL1 Complementary Output 1A. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

Loop Filter Node for the Output PLL1. Connect an external 6.8 nF capacitor from this pin to Pin 45 (LDO_1).

Output PLL1 Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin to ground. This pin is also the ac ground reference for the integrated output PLL external loop filter.

I

Differential input

Complementary Reference C Input. Complementary signal to the input provided on Pin 53.

Reference C Input. This internally biased input is typically ac-coupled; when configured in that manner, it can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

I

Differential input

Complementary Reference D Input. Complementary signal to the input provided on Pin 57.

Reference D Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Rev. 0 | Page 18 of 120

Data Sheet AD9559

70

REFB

I

Differential

Reference B Input. This internally biased input is typically ac-coupled; when

Input/

Pin No. Mnemonic

63

64

XOB I

XOA I

Output Pi n Typ e Description

Differential input

Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and should be ac-coupled with a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB.

Differential input

System Clock Input. XOA contains internal dc biasing and should be ac-coupled with a 0.01 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option, but a spur may be introduced if the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.1 μF capacitor from XOB to ground.

71

EP

input

AREFB

E

I

Differential input

GND O Exposed pad

configured in this manner, it can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference B Input. Complementary signal to the input provided on Pin 70.

The exposed pad is the ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.

Rev. 0 | Page 19 of 120

AD9559 Data Sheet

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

1k10 100 10k 100k 1M 10M 100M

PHASE NOISE (dBc/Hz)

FREQUENCY OF F SET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 331fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –75 100Hz –92 1kHz –116 10kHz –126 100kHz –130 1MHz –143 10MHz –152 FLOOR –158

10644-300

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

1k10 100 10k 100k 1M 10M 100M

PHASE NOISE (dBc/Hz)

FREQUENCY OF F SET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 310fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –71 100Hz –82 1kHz –105 10kHz –114 100kHz –117 1MHz –133 10MHz –142 FLOOR –153

10644-003

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OF F SET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 306fs

PHASE NOISE ( d Bc/Hz): 10Hz –70 100Hz –86 1kHz –105 10kHz –114 100kHz –117 1MHz –134 10M

Hz –141

FLOOR –153

10644-004

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OF F SET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 328fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –70 100Hz –85 1kHz –105 10kHz –112 100kHz –115 1MHz –133 10MHz –142

10644-005

TYPICAL PERFORMANCE CHARACTERISTICS

fR = input reference clock frequency; f

= output clock frequency; f

OUT

= SYSCLK input frequency; VDD3 and VDD at nominal supply voltage.

SYS

Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 50 Hz, f

= 156.25 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 3. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 50 Hz, f

= 622.08 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 4. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 50 Hz, f

= 644.53125 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 5. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 50 Hz, f

= 693.482991 MHz,

OUT

= 49.152 MHz Crystal

SYS

Rev. 0 | Page 20 of 120

Data Sheet AD9559

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 335fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –82 100Hz –90 1kHz –96 10kHz –119 100kHz –128 1MHz –143 10MHz –152 FLOOR –158

10644-006

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 309fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –84 100Hz –93 1kHz –116 10kHz –125 100kHz –130 1MHz –144 10MHz –152 FLOOR –158

10644-007

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 321fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –61 100Hz –69 1kHz –108 10kHz –127 100kHz –132 1MHz –146 10MHz –153

10644-008

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 331fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –70 100Hz –75 1kHz –86 10kHz –108 100kHz –112 1MHz –129 10MHz –142 FLOOR –152

10644-009

Figure 6. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 1 kHz, f

= 174.703 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 8. Absolute Phase Noise (Output Driver = HSTL),

= 2 kHz, f

f

R

DPLL Loop BW = 100 Hz, f

= 125 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 7. Absolute Phase Noise (Output Driver = 3.3.V CMOS),

f

= 19.44 MHz, f

R

DPLL Loop BW = 100 Hz, f

= 161.1328125 MHz,

OUT

= 49.152 MHz Crystal

SYS

Rev. 0 | Page 21 of 120

Figure 9. Absolute Phase Noise (Output Driver = HSTL),

f

= 25 MHz, f

R

DPLL Loop BW = 500 Hz, f

= 1 GHz,

OUT

= 49.152 MHz Crystal

SYS

AD9559 Data Sheet

–60

PHASE NOISE (dBc/Hz)

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (12kHz TO 20MHz): 383fs

PHASE NOISE ( d Bc /Hz): 10Hz –60 100Hz –85 1kHz –104 10kHz –112 100kHz –114 1MHz –132 10MHz –141 FLOOR –153

10644-011

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

10644-012

INTEGRATED RMS JITTER (12kHz TO 20MHz): 392fs

PHASE NOISE ( d Bc /Hz): OFFSET LEVEL 10Hz –66 100Hz –91 1kHz –110 10kHz –119 100kHz –121 1MHz –136 10MHz –146 FLOOR –156

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

10644-013

INTEGRATED RMS JITTER (12kHz TO 20MHz): 378fs

PHASE NOISE ( d Bc /Hz): OFFSET LEVEL 10Hz –74 100Hz –97 1kHz –116 10kHz –125 100kHz –127 1MHz –143 10MHz –153 FLOOR –158

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

1k10 100 10k 100k 1M 10M 100M

10644-014

INTEGRATED RMS JITTER (12kHz TO 20MHz): 418fs

PHASE NOISE ( d Bc/Hz): OFFSET LEVEL 10Hz –71 100Hz –96 1kHz –122 10kHz –132 100kHz –134 1MHz –149 10MHz –157 FLOOR –161

INTEGRATED RMS JITTER

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

1k10 100 10k 100k 1M 10M 100M

FREQUENCY OF F SET (Hz)

Figure 10. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 10 Hz, f

(12kHz TO 20MHz): 373fs PHASE NOISE ( d Bc /Hz):

10Hz –60 100Hz –85 1kHz –104 10kHz –113 100kHz –114 1MHz –132 10MHz –142 FLOOR –153

= 644.53 MHz,

OUT

= 19.2 MHz TCXO

SYS

10644-010

Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS),

= 19.44 MHz, f

f

R

DPLL Loop BW = 10 Hz, f

=161.1328125 MHz,

OUT

= 19.2 MHz TCXO

SYS

Figure 11. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 10 Hz, f

Figure 12. Absolute Phase Noise (Output Driver = HSTL),

f

= 19.44 MHz, f

R

DPLL Loop BW = 0.1 Hz, f

= 693.482991 MHz,

OUT

= 19.2 MHz TCXO

SYS

= 312.5 MHz,

OUT

= 19.2 MHz TCXO

SYS

Rev. 0 | Page 22 of 120

Figure 14. Absolute Phase Noise (Output Driver = 1.8V CMOS),

= 2 kHz, f

f

R

DPLL Loop BW = 10 Hz, f

= 70.656 MHz,

OUT

= 19.2 MHz TCXO

SYS

Data Sheet AD9559

DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (mV)

0 100 200 300 400 600 800 1000 1200500 700 900 1100

FREQUENCY (MHz)

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.

95

2.00

10644-116

0

1200

1000

800

600

400

200

DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (mV)

0 100 200 300 400 500 600 700 800

FREQUENCY (MHz)

LVDS (DEFAULT)

LVDS (BOOST)

10644-117

3.5

3.0

1.0

1.5

2.0

2.5

0 30025020015010050

PEAK-TO-PEAK AMPLITUDE (V)

FREQUENCY (MHz)

1.8 V MODE

3.3V STRONG MODE

10644-118

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

0 10080604020

PEAK-TO-PEAK AMPLITUDE (V)

FREQUENCY (MHz)

3.3V WEAK MO DE

10644-119

0

10

20

30

40

50

60

70

0 140012001000800600400200

POWER (mW)

FREQUENCY (MHz)

10644-120

0

5

10

15

20

25

30

35

40

45

50

0 100 200 300 400 500 600 700 900800

POWER (mW)

FREQUENCY (MHz)

10644-121

Figure 15. Amplitude vs. Toggle Rate,

HSTL Mode (LVPECL-Compatible Mode)

Figure 16. Amplitude vs. Toggle Rate, LVDS

Figure 18. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Weak Mode) CMOS

Figure 19. Power Consumption vs. Frequency,

HSTL Mode on Output Driver Power Supply Only

(Pin 17, Pin 21, Pin 34, and Pin 38)

Figure 17. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Strong Mode) and 1.8 V CMOS

Figure 20. Power Consumption vs. Frequency,

LVDS Mode on Output Driver Power Supply Only

(Pin 17, Pin 21, Pin 34, and Pin 38)

Rev. 0 | Page 23 of 120

AD9559 Data Sheet

0

10

20

30

40

50

60

80

70

0 20018016014012010080604020

POWER (mW)

FREQUENCY (MHz)

10644-122

1.8V CMOS

3.3V CMOS W E AK

3.3V CMOS STRONG

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1.0

–1 0 1 2 3 4 5

DIFFERENTIAL AMPLITUDE (V)

TIME (ns)

10644-123

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

–1 0 1 2 3 4

DIFFERENTIAL AMPLITUDE (V)

TIME (ns)

10644-124

–0.2

0.2

0.6

1.0

1.4

1.8

2.2

2.6

3.0

3.4

–1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

AMPLITUDE (V)

TIME (ns)

10pF LOAD

2pF LOAD

10644-126

–1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

AMPLITUDE (V)

TIME (ns)

–0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

10pF LOAD

2pF LOAD

10644-127

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

–5 5 15 25 35 45 55 65 75 85 95

AMPLITUDE (V)

TIME (ns)

10pF LOAD

2pF LOAD

10644-128

Figure 21. Power Consumption vs. Frequency for Two CMOS Drivers;

Power Is Measured on Output Driver Power Supply Only

(Pin 17, Pin 21, Pin 34, and Pin 38 for 1.8 V CMOS Mode or

on Pin 18 and Pin 37 for 3.3 V CMOS Mode); C

LOAD

= 80 pF

Figure 22. Output Waveform, HSTL (400 MHz)

Figure 24. Output Waveform,

3.3 V CMOS (100 MHz, Strong Mode)

Figure 25. Output Waveform, 1.8 V CMOS (100 MHz)

Figure 23. Output Waveform, LVDS (400 MHz)

Figure 26. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode)

Rev. 0 | Page 24 of 120

Data Sheet AD9559

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

0

3

10 100 1k 10k 100k

FREQUENCY OFFSET (Hz)

LOOP GAIN (dB)

10644-129

LOOP BW = 100Hz; HIGH PHASE M ARGIN; PEAKING: 0.06dB; –3dB: 69Hz

LOOP BW = 2kHz; HIGH PHASE M ARGIN; PEAKING: 0.097dB; –3dB: 1.23kHz

LOOP BW = 5kHz; HIGH PHASE M ARGIN; PEAKING: 0.14dB; –3dB: 4.27kHz

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

0

3

10 100 1k

FREQUENCY OFFSET (Hz)

LOOP GAIN (dB)

10k 100k

10644-230

LOOP BW = 100Hz; NORMAL PHASE M ARGIN; PEAKING: 0.09dB; –3dB: 117Hz

LOOP BW = 2kHz; NORMAL PHASE M ARGIN; PEAKING: 1.6dB; –3dB: 2.69kHz

Figure 27. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 5 kHz Loop

Bandwidth Settings; High Phase Margin Loop Filter Setting

(This figure is compliant with Telcordia GR-253

jitter transfer test for loop bandwidths < 2 kHz.)

Note that bandwidth is defined as the point where t he open loop gain = 0 dB.

Figure 28. Closed-Loop Transfer Function for 100 Hz and 2 kHz Loop

Bandwidth Settings; Normal Phase Margin Loop Filter Setting

Note that bandwidth is defined as the point where t he open loop gain = 0 dB.

Rev. 0 | Page 25 of 120

AD9559 Data Sheet

AD9559

HSTL OR LVDS

DOWNSTREAM

DEVICE

WITH HIGH

IMPEDANCE

INPUT AND

INTERNAL

DC BIAS

0.1µF

100Ω

10644-130

Z0 = 50Ω

Z

0

= 50Ω

SINGLE-ENDED

(NOT COUPLED)

AD9559

HSTL OR LVDS

Z

0

= 50Ω

Z

0

= 50Ω

SINGLE-ENDED

(NOT COUPLED)

LVDS OR 1.8V HS TL

HIGH IMPE DANCE

DIFFERENTIAL

RECEIVER

100Ω

10644-131

SINGLE-ENDED

(NOT COUPLED)

VS = 3.3V

3.3V

LVPECL

82Ω82Ω

127Ω127Ω

0.1µF

AD9559

1.8V

HSTL

Z0 = 50Ω

Z

0

= 50Ω

10644-132

XOA

XOB

AD9559

10MHz TO 50MHz FUNDAMENTAL

AT-CUT CRYST AL WITH

10pF LOAD CAP ACITANCE

10pF

10644-133

XOA

300Ω

150Ω

0.1µF

XOB

AD9559

3.3V CMOS TCXO

0.1µF

10644-134

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

Figure 29. AC-Coupled LVDS or HSTL Output Driver

(100 Ω resistor can be placed on either side of decoupling capacitors

and should be as close to the destination receiver as possible.)

Figure 30. DC-Coupled LVDS or HSTL Output Driver

Figure 31. Interfacing the HSTL Driver to a 3.3 V LVPECL Input

(This method incorporates impedance matching and dc-biasing for bipolar

LVPECL receivers. If the receiver is self-biased, the termination scheme shown in

Figure 29 is recommended.)

(The recommended C

Figure 32. System Clock Input (XOA/XOB) in Crystal Mode

shown here should equal the C

When Using a TCXO/OCXO with 3.3 V CMOS Output

= 10 pF is shown. The values of 10 pF shunt capacitors

LOAD

of the crystal.)

LOAD

Figure 33. System Clock Input (XOA, XOB)

Rev. 0 | Page 26 of 120

Data Sheet AD9559

GETTING STARTED

CHIP POWER MONITOR AND STARTUP

The AD9559 monitors the voltage on the power supplies at power-up. When VDD3 is greater than 2.35 V ± 0.1 V and VDD is greater than 1.4 V ± 0.05 V, the device generates a 20 ms reset pulse. The power-up reset pulse is internal and independent of the

E

RESET

A

pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. Within 45 ns after the internal reset pulse, the M5 to M0 multifunction pins behave as high impedance digital inputs and continue to do so until programmed otherwise.

During a device reset (either via the power-up reset pulse or the

E

RESET

A

pin), the M3 to M0 multifunction pins behave as high impedance inputs; and at the point where the reset condition is cleared, level-sensitive latches capture the logic pattern that is present on the multifunction pins.

MULTIFUNCTION PINS AT RESET/POWER-UP

At start-up, the M0 and M1 pins allow the user to either bypass EEPROM loading or load one of three EEPROM profiles. See Table 23 for information on setting the M0 and M1 pins.

Pin M3 selects SPI or I²C mode: SPI mode is set by pulling M3 low at startup. If M3 is high, I²C mode is set, and the M4 and M5 pins determine the I²C address. See Ta ble 25 for information on SPI/I²C configuration.

If 4-wire SPI mode is selected, by setting Bit 7 of Register 0x0000, the M4/SDO pin functions as SDO and is not available for other functions as an M pin. However, in I²C mode and in 3-wire SPI mode, M4 is available as the fifth M pin.

A sixth M pin, M5, is available if the serial port is in I²C mode or 2-wire SPI mode. In 2-wire SPI mode, there is no available, and it is assumed that the

AD9559 is the only device

on the SPI bus.

CS

A

E

A

DEVICE REGISTER PROGRAMMING USING A REGISTER SETUP FILE

The evaluation software contains a programming wizard and a convenient graphical user interface that assists the user in determining the optimal configuration for the DPLLs, APLLs, and SYSCLK based on the desired input and output frequencies. It generates a register setup file with a .STP extension that is easily readable using a text editor.

The user can configure PLL_0 and PLL_1 independently. To do so, the user should program the common registers (such as the system clock and reference inputs) first. Next, the registers that are unique to PLL_0 or PLL_1 can be configured independently.

After using the evaluation software to create the setup file, use the following sequence to program the AD9559:

1. Set user free run mode.

DPLL_0: Register 0x0A22 = 0x01. DPLL_1: Register 0x0A42 = 0x01.

2. Update all registers (also referred to as IO_UPDATE).

Register 0x0005 = 0x01.

3. Write the register values in the STP file from Address 0x0000

to Address 0x0207.

4. IO_UPDATE. Register 0x0005 = 0x01.

5. Ve r if y that SYSCLK is stable. Register 0x0D01[1] = 1.

The user must issue an IO_UPDATE each time before polling Register 0x0D01.

6. For the outputs to toggle prior to DPLL phase or frequency

lock, set the following: APLL_0: Register 0x0A20 = 0x40 (soft sync). APLL_1: Register 0x0A40 = 0x40 (soft sync).

7. Write the rest of the registers in the STP file starting at

Address 0x0300.

8. Calibrate APLL on next IO_UPDATE.

APLL_0: Register 0x0A20 = 0x20. APLL_1: Register 0x0A40 = 0x20.

9. IO_UPDATE. Register 0x0005 = 0x01.

10. Clear user free run mode.

DPLL_0: Register 0x0A22[0] = 0b. DPLL_1: Register 0x0A42[0] = 0b.

11. IO_UPDATE. Register 0x0005 = 0x01.

Rev. 0 | Page 27 of 120

AD9559 Data Sheet

REGISTER PROGRAMMING OVERVIEW

This section provides a programming overview of the register blocks in the AD9559, describing what they do and why they are important. This is supplemental information only, needed only if the user wishes to load the registers without using the STP file.

The AD9559 evaluation software contains a wizard that determines the register settings based on the user’s input and output frequencies. It is strongly recommended that the evaluation software be used to determine these settings.

Multifunction Pins (Optional)

This step is required only if the user intends to use any of the multifunction pins for status or control. The multifunction pin parameters are at Register 0x0100 to Register 0x0107.

Table 196 has a list of M pin output functions, and Tab l e 197 has a list of M pin input functions.

IRQ Functions (Optional)

This step is required only if the user intends to use the IRQ feature. The IRQ functions are divided into three groups: common, PLL_0, and PLL_1.

The user must first choose the events that trigger an IRQ and then set them in Register 0x010A to Register 0x0112. Next, an M pin must be assigned to the IRQ function. The user can choose to dedicate one M pin to each of the three IRQ groups, or one M pin can be assigned for all IRQs.

The IRQ monitor registers are located at Register 0x0D08 to Register 0x0D10. If the desired bits in the IRQ mask registers at Register 0x010A to Register 0x0112 are set high, the appropriate IRQ monitor bit at Register 0x0D08 to Register 0x0D10 is set high when the indicated event occurs.

Individual IRQ events are cleared by using the IRQ clearing registers at Register 0x0A05 to Register 0x0A0E or by setting the clear all IRQs bit (Register 0x0A05[0]) to 1b.

The default values of the IRQ mask registers are such that interrupts are not generated. The default IRQ pin mode is opendrain NMOS.

Watchdog Timer (Optional)

This step is required only if the user intends to use the watchdog timer. The watchdog timer control is at Register 0x0108 and Register 0x0109. The watchdog timer is disabled by default.

The watchdog timer is useful for generating an IRQ after a fixed amount of time. The timer is reset by setting the clear watchdog timer bit in Register 0x0A05[7] to 1.

The user can also program an M pin for the watchdog timer output. In this mode, the M pin generates a 40 ns pulse every time the watchdog timer expires.

System Clock Configuration

The system clock multiplier (SYSCLK) parameters are at Register 0x0200 to Register 0x0207. For optimal performance, use the following steps:

1. Set the system clock PLL input type and divider values.

2. Set the system clock period.

It is essential to program the system clock period because many of the AD9559 subsystems rely on this value.

3. Set the system clock stability timer.

It is highly recommended that the system clock stability timer be programmed. This is especially important when using the system clock multiplier and also applies when using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the AD9559. The system clock stability timer specifies the amount of time that the system clock PLL must be locked before the part declares that the system clock is stable. The default value is 50 ms.

4. Update all registers (Register 0x0005 = 0x01).

Important Note

The system clock must be stable for the digital PLL blocks to function correctly and read back the registers updated on the system clock domain. These registers include the status registers, as well as the free running tuning word. Therefore, when debugging the stable by checking Bit 1 in Register 0x0D01.

AD9559, the user mus

t first ensure that the system clock is

Reference Inputs

The reference input parameters and reference dividers are common to both PLLs; there is only one reference divider (R divider) for each reference input. The register address for each reference input is as follows:

• REFA: Register 0x0300 to Register 0x031A

• REFB: Register 0x0320 to Register 0x033A

• REFC: Register 0x0340 to Register 0x035A

• REFD: Register 0x0360 to Register 0x037A

These registers include the following settings:

• Reference logic family

• Reference divider (R divider value)

• Reference input period and tolerance

• Reference validation timer

• Phase and frequency lock detector settings

Rev. 0 | Page 28 of 120

Data Sheet AD9559

Other reference input settings can be found at the following register addresses:

Note that the APLL calibration and synchronization bits can be found in the following registers:

 Reference input enable information is found in the DPLL

Feedback Dividers section.

 Reference power-down is found in Register 0x0A01.  Reference priority settings are found in the DPLL profiles.

DPLL_0: Registers 0x0440 through 0x0473 DPLL_1: Registers 0x0540 through 0x0573

 Reference switching mode settings are found in

DPLL_0: Register 0x0A22 DPLL_1: Register 0x0A42

DPLL Controls and Settings

The DPLL control parameters are separate for DPLL_0 and DPLL_1. They reside in the following locations:

 DPLL_0: Register 0x0400 to Register 0x0415  DPLL_1: Register 0x0500 to Register 0x0515

These registers include the following settings:

 30-bit free running frequency  DPLL pull-in range limits  DPLL closed-loop phase offset  Tuning word history control (for holdover operation)  Phase slew control (for controlling the phase slew rate

during a closed-loop phase adjustment)

With the exception of the free running tuning word, the default values of these registers are fine for normal operation. The free running frequency of the DPLL determines the frequency that appears at the APLL input when user free run mode is selected. The correct free running frequency is required for the APLL to calibrate and lock correctly.

Note that the user free run bits, which enable user free run mode, can be found in the following registers:

 DPLL_0: Register 0x0A22 = 0x01  DPLL_1: Register 0x0A42 = 0x01

Output PLLs (APLLs) and Output Drivers

The registers controlling the APLLs and output drivers reside at the following locations:

 APLL_0: Register 0x0420 to Register 0x042E  APLL_1: Register 0x0520 to Register 0x052E

The following functions are controlled in these registers:

 APLL settings (feedback divider, charge pump current)  Output synchronization mode  Output divider values  Output enable/disable (disabled by default)  Output logic type

 APLL_0: Register 0x0A20  APLL_1: Register 0x0A40

DPLL Feedback Dividers

Each digital PLL has separate feedback divider settings for each reference input. This allows the user to have each digital PLL perform a different frequency translation. However, there is only one reference divider (R divider) for each reference input.

The feedback divider register settings reside in the following locations:

 DPLL_0, REFA: Register 0x0440 to Register 0x044C  DPLL_0, REFB: Register 0x044D to Register 0x0459  DPLL_0, REFC: Register 0x045A to Register 0x0466  DPLL_0, REFD: Register 0x0467 to Register 0x0473  DPLL_1, REFC: Register 0x0540 to Register 0x054C  DPLL_1, REFD: Register 0x054D to Register 0x0559  DPLL_1, REFA: Register 0x055A to Register 0x0566  DPLL_1, REFB: Register 0x0567 to Register 0x0573

These registers include the following settings:

 Reference priority  Reference input enable (separate for each DPLL)  DPLL loop bandwidth  DPLL loop filter  DPLL feedback divider (integer portion)  DPLL feedback divider (fractional portion)

Common Operational Controls

The common operational controls reside at Register 0x0A00 to Register 0x0A0E and include the following:

 Simultaneous calibration and synchronization of both PLLs  Global power-down  Reference power-down  Reference validation override  IRQ clearing (for all IRQs)

PLL_0 and PLL_1 Operational Controls

The PLL_0 and PLL_1 operational controls are located at Register 0x0A20 to Register 0x0A44 and include the following:

 APLL calibration and synchronization  Output driver enable and power-down  DPLL reference input switching modes  DPLL phase offset control

Rev. 0 | Page 29 of 120

AD9559 Data Sheet

APLL VCO Calibration

VCO calibration ensures that, at the time of calibration, the dc control voltage of the APLL VCO is centered in the middle of its operating range. The user can calibrate VCO_0 independently of VCO_1, and vice versa. It is important to remember the following conditions when calibrating the APLL VCO:

• The system clock must be stable.

• The APLL VCO must have the correct frequency from the

30-bit DCO (digitally controlled oscillator) during calibration. The free running tuning word is found in DPLL_0: Registers 0x0400 to 0x0403 DPLL_1: Registers 0x0500 to 0x0503

• The APLL VCO must be recalibrated any time the APLL

frequency changes.

• APLL VCO calibration occurs on the low-to-high

transition of the APLL VCO calibration bit. APLL_0: Register 0x0A20[1] APLL_1: Register 0x0A40[1]

• The VCO calibration bit is not an autoclearing bit.

Therefore, this bit must be cleared (and an IO_UPDATE issued) before the APLL is recalibrated.

• The best way to monitor successful APLL calibration is

by monitoring the APLL locked bit, in the following registers: APLL_0: Register 0x0D20[3] APLL_1: Register 0x0D40[3]

Generate the Output Clock

If Register 0x0425 (for PLL_0) and/or Register 0x0525 (for PLL_1) is programmed for automatic clock distribution synchronization via the DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs. Otherwise, set and then clear the soft sync bit (Bit 2 in Register 0x0A20 for APLL_0 and Register 0x0A40 for APPL_1) or use a multifunction pin input (if programmed accordingly) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs.

Generate the Reference Acquisition

After the registers are programmed, clear the user free run bit (Bit 0 in Register 0x0A22 for DPLL_0 and Register 0x0A42 for DPPL_1) and issue an IO_UPDATE using Register 0x0005[0] to invoke all of the register settings programmed up to this point.

The DPLLs lock to the first available reference that has the highest priority.

Rev. 0 | Page 30 of 120