ANALOG DEVICES AD9551 Service Manual

R

Multiservice Clock Generator

FEATURES

Translation between any two standard network rates Dual reference inputs and dual clock outputs Pin programmable for standard network rate translation SPI programmable for arbitrary rational rate translation Output frequencies from 10 MHz to 900 MHz Input frequencies from 19.44 MHz to 806 MHz On-chip VCO Meets OC-192 high band jitter generation requirement Supports standard forward error correction (FEC) rates Supports holdover operation Supports hitless switchover and phase build-out (even with

unequal reference frequencies) SPI-compatible 3-wire programming interface Single supply (3.3 V)

APPLICATIONS

Multiservice switches Multiservice routers Exact network clock frequency translation General-purpose frequency translation

GENERAL DESCRIPTION

The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation.

AD9551

Reference conditioning and switchover circuitry internally synchronizes the two references so that if one reference fails, there is virtually no phase perturbation at the output.

The AD9551 uses an external crystal and an internal DCXO to provide for holdover operation. If both references fail, the device maintains a steady output signal.

The AD9551 provides pin-selectable, preset divider values for standard (and FEC adjusted) network frequencies. The pinselectable frequencies include any combination of 15 possible input frequencies and 16 possible output frequencies. A SPI interface provides further flexibility by making it possible to program almost any rational input/output frequency ratio.

The AD9551 is a clock generator that employs fractional-N-based phase-locked loops (PLL) using sigma-delta (Σ-) modulators (SDMs). The fractional frequency synthesis capability enables the device to meet the frequency and feature requirements for multiservice switch applications. The AD9551 precisely generates a wide range of standard frequencies when using any one of those same standard frequencies as a timing base (reference). The primary challenge of this function is the precise generation of the desired output frequency because even a slight output frequency error can cause problems for downstream clocking circuits in the form of bit or cycle slips. The requirement for exact frequency translation in such applications necessitates the use of a fractional-N-based PLL architecture with variable modulus.

BASIC BLOCK DIAGRAM

C

YSTAL

(26MHz)

REFA

REFB

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks ar

e the property of their respective owners.

REFERENCE

CONDITIONING

AND SWITCH-

OVER

HOLDOVER

LOOP

PIN-DEFINED AND SERIAL

PROGRAMMING

Figure 1.

PLL

OUTPUT

CIRCUITRY

AD9551

OUT1

OUT2

07805-001

AD9551

REVISION HISTORY

9/09—Rev. A to Rev. B

Changes to Table 25 ........................................................................ 33

6/09—Rev. 0 to Rev. A

Changes to Figure 23 ...................................................................... 23

4/09—Revision 0: Initial Version

Rev. B | Page 2 of 40

AD9551

L

A

The AD9551 is easily configured using the external control pins (A[3:0], B[3:0], and Y[3:0]). The logic state of these pins sets predefined divider values that establish a specific input-to-output frequency ratio. For applications requiring other frequency ratios, the user can override any of the preconfigured divider settings via the serial port, which enables a very wide range of applications.

The AD9551 architecture consists of two cascaded PLL stages. The first stage consists of fractional division (via SDM), followed by a digital PLL that uses a crystal resonator-based DCXO. The DCXO relies on an external crystal with a resonant frequency in the range of 19.44 MHz to 52 MHz. The DCXO constitutes the first PLL, which operates within a narrow frequency range (±50 ppm) around the crystal resonant frequency. This PLL has a loop bandwidth of approximately 180 Hz, providing initial jitter cleanup of the input reference signal. The second stage is a frequency multiplying PLL that translates the first stage output frequency (in the range of 19.44 MHz to 104 MHz) up to ~3.7 GHz. This PLL incorporates an SDM-based fractional feedback divider that enables fractional frequency multiplication. Programmable integer dividers at the output of this second PLL establish a final output frequency of up to 900 MHz.

It is important to understand that the architecture of the AD9551 produces an output frequency that is most likely not coherent with the input reference frequency. The reason is that the input and crystal frequencies typically are not harmonically related and neither are the output and crystal frequencies. As a result, there is generally no relationship between the phase of the input and output signals.

FUNCTIONAL BLOCK DIAGRAM

INPUT PL

LOCKED

XTAL1 XTAL0 LF

The AD9551 includes reference signal processing blocks that enable a smooth switching transition between two reference inputs. This circuitry automatically detects the presence of the reference input signals. If only one input is present, the device uses it as the active reference. If both inputs are present, one becomes the active reference and the other becomes the alternate reference. The circuitry edge-aligns the backup reference with the active reference. If the active reference fails, the circuitry automatically switches to the backup reference (if available), making it the new active reference. Meanwhile, if the failed reference is once again available, it becomes the new backup reference and is edge-aligned with the new active reference (a precaution against failure of the new active reference).

If neither reference can be used, the AD9551 supports a holdover mode. Note that the external crystal is necessary to provide the switchover and holdover functionality. It is also the clock source for the reference synchronization and monitoring functions.

The AD9551 relies on a single external capacitor for the output PLL loop filter. With proper termination, the output is compatible with LVPECL, LVDS, or CMOS logic levels, although the AD9551 is implemented in a strictly CMOS process.

The AD9551 operates over the extended industrial temperature range of −40°C to +85°C.

OUTPUT PLL

LOCKED

REFA, REF

REFB, REFB

SCLK, SDIO,

A[3:0]

B[3:0]

Y[3:0]

TEST

MUX

f

2

REFA

N

A

SDM

A

f

2

REFB

N

B

SDM

B

3

4

REGISTER BANK

PRECONFIGURED

DIVIDER V ALUES

CS

SYNCHRONI ZATIO N AND

SWITCH OVER CONTRO L

REFERENCE

MONITOR

SAMPLE RATE CONTROL

DIG.

P

LOOP

F D

FILTER

19.44MHz MODE

DCXO

NA, MODA, FRAC

NB, MODB, FRAC

N, MOD, FRAC, P0, P1, P

LOOP

CONFIGURATION

A

B

2

LOCK

DETECT

f

IF

P F D

CHARGE

PUMP

N = 4N

N1 4/5

SDM

+ N

1

FRAC, MOD

3350MHz TO

4050MHz

VCO

0

N

P2, P1, P

AD9551

4 TO111 TO

P

0P1

0

63

1 TO

63

P

f

2

OUT1

f

OUT2

2

OUT1, OUT1

OUT2, OUT2

07805-002

Figure 2.

Rev. B | Page 3 of 40

AD9551

SPECIFICATIONS

Minimum and maximum values apply for full range of supply voltage and operating temperature variation. Typical values apply for VDD = 3.3 V, T

= 25°C, unless otherwise noted.

A

REFERENCE CLOCK INPUT CHARACTERISTICS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

FREQUENCY RANGE 19 INPUT CAPACITANCE 3 pF INPUT RESISTANCE 6 kΩ Measured single-ended DUTY CYCLE 40 60 % REFERENCE CLOCK INPUT VOLTAGE SWING

Differential 250 mV Maximum magnitude across pin pair Single-Ended 250 mV Peak-to-peak

1

The 19 MHz lower limit applies only to the 19.44 MHz operating mode.

OUTPUT CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL MODE

Differential Output Voltage Swing Common-Mode Output Voltage VDD − 1.77 VDD − 1.66 VDD − 1.20 V Output driver static Frequency Range 0 900 MHz Duty Cycle 40 60 % Up to 805 MHz output frequency Rise/Fall Time1 (20% to 80%) 255 305 ps

LVDS MODE

Differential Output Voltage Swing

Balanced, VOD 247 454 mV

Unbalanced, ∆VOD 25 mV

Offset Voltage

Common Mode, VOS 1.125 1.375 V Output driver static Common-Mode Difference, ∆VOS 25 mV

Short-Circuit Output Current 17 24 mA Frequency Range 0 900 MHz Duty Cycle 40 60 % Up to 805 MHz output frequency Rise/Fall Time1 (20% to 80%) 285 355 ps

CMOS MODE

Output Voltage High, VOH

IOH = 10 mA 2.8 V IOH = 1 mA 2.8 V

Output Voltage Low, VOL

IOL = 10 mA 0.5 V IOL = 1 mA 0.3 V

Frequency Range 0 200 MHz

1

806 MHz

Measured with a differential probe across the input pins

690 765 889 mV Output driver static

100 Ω termination between both pins of the output driver

Voltage swing between output pins; output driver static

Absolute difference between voltage swing of normal pin and inverted pin; output driver static

Voltage difference between output pins; output driver static

100 Ω termination between both pins of the output driver

Output driver static; standard drive strength setting

3.3 V CMOS; standard drive strength setting

Rev. B | Page 4 of 40

AD9551

Parameter Min Typ Max Unit Test Conditions/Comments

Duty Cycle 45 55 % At maximum output frequency Rise/Fall Time1 (20% to 80%) 500 745 ps

1

The listed values are for the slower edge (rise or fall).

JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH)

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

12 kHz to 20 MHz 1.3 ps rms fIN = 19.44 MHz, f

0.8 ps rms fIN = 622.08 MHz, f

50 kHz to 80 MHz 0.5 ps rms fIN = 19.44 MHz, f

0.6 ps rms fIN = 622.08 MHz, f

4 MHz to 80 MHz 0.1 ps rms fIN = 622.08 MHz, f

JITTER TRANSFER BANDWIDTH 180 Hz

JITTER TRANSFER PEAKING 0.1 dB

CRYSTAL OSCILLATOR CHARACTERISTICS

3.3 V CMOS; standard drive strength setting; 10 pF load

= 622.08 MHz

OUT

= 622.08 MHz

OUT

= 622.08 MHz

OUT

= 622.08 MHz

OUT

= 622.08 MHz

OUT

See the Typical Performance Characteristics section

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL FREQUENCY

Range 19 26 52 MHz

Tolerance 20 ppm CRYSTAL MOTIONAL RESISTANCE 100 Ω DCXO LOAD CAPACITANCE CONTROL

RANGE

3 to 21 pF

Requires a crystal with a 10 pF load specification

POWER CONSUMPTION

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

TOTAL CURRENT 169 195 mA

VDD CURRENT BY PIN

Pin 9 24 27 mA

Pin 23 78 84 mA

Pin 27 36 42 mA

Pin 34 36 42 mA LVPECL OUTPUT DRIVER 38 mA

At maximum output frequency with both output channels active

900 MHz with 100 Ω termination between both pins of the output driver

Rev. B | Page 5 of 40

AD9551

LOGIC INPUT PINS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS

Logic 1 Voltage, VIH 1.0 V

Logic 0 Voltage, VIL 0.8 V Logic 1 Current, IIH 3 µA Logic 0 Current, IIL 17 µA

1

The A[3:0], B[3:0], Y[3:0], and OUTSEL pins have 100 kΩ internal pull-up resistors.

RESET PIN

Table 7.

Parameter Min Typ Max Unit

INPUT CHARACTERISTICS

Input Voltage High, VIH 1.8 V Input Voltage Low, VIL 1.3 V Input Current High, I Input Current Low, I

MINIMUM PULSE WIDTH HIGH 2 ns

1

The RESET pin has a 100 kΩ internal pull-up resistor, so the default state of the device is reset.

1

For the CMOS inputs, a static Logic 1 results from either a pull-up resistor or no connection

1

0.3 12.5 µA

INH

31 43 µA

INL

LOGIC OUTPUT PINS

Table 8.

Parameter Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage High, VOH 2.7 V Output Voltage Low, VOL 0.4 V

SERIAL CONTROL PORT

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

CS

Input Logic 1 Voltage 1.6 V Input Logic 0 Voltage 0.5 V Input Logic 1 Current 0.03 µA Input Logic 0 Current 2 µA Input Capacitance 2 pF

SCLK

Input Logic 1 Voltage 1.6 V Input Logic 0 Voltage 0.5 V Input Logic 1 Current 2 µA Input Logic 0 Current 0.03 µA Input Capacitance 2 pF

SDIO

Input

Input Logic 1 Voltage 1.6 V Input Logic 0 Voltage 0.5 V

Rev. B | Page 6 of 40

AD9551

Parameter Min Typ Max Unit Test Conditions/Comments

Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF

Output

Output Logic 1 Voltage 2.8 V 1 mA load current Output Logic 0 Voltage 0.3 V 1 mA load current

SERIAL CONTROL PORT TIMING

Table 10.

Parameter Limit Unit

SCLK

Clock Rate, 1/t

Pulse Width High, t

Pulse Width Low, t SDIO to SCLK Setup, tDS 4 ns min SCLK to SDIO Hold, tDH 0 ns min SCLK to Valid SDIO, tDV 13 ns max CS to SCLK Setup (tS) and Hold (tH)

CS Minimum Pulse Width High

50 MHz max

CLK

3 ns min

HIGH

3 ns min

LOW

0 ns min

6.4 ns min

Rev. B | Page 7 of 40

AD9551

ABSOLUTE MAXIMUM RATINGS

Table 11.

Parameter Rating

Supply Voltage (VDD) 3.6 V Maximum Digital Input Voltage −0.5 V to VDD + 0.5 V Storage Temperature −65°C to +150°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 40

AD9551

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A2

A3

B0

B1

37

38

39

40

PIN 1

1B2

INDICATOR

2B3 3

REFA

4REFA 5REFB 6

REFB

7RESET 8LDO_IPDIG 9VDD

10LDO_XTAL

NOTES

1. EXPOSED DI E PAD MUST BE CONNECTED TO GND.

AD9551

TOP VIEW

(Not to Scale)

11

12

13

CS

XTAL0

XTAL1

14

SCLK

Figure 3. Pin Configuration

Table 12. Pin Function Descriptions

Pin No.

9, 23,

Mnemonic Type

VDD P Power Supply Connection (3.3 V Analog Supply).

1

Description

27, 34 30, 31 GND P Analog Ground. 4 REFA I Analog Input (Active High)—Reference Clock Input A. 3

REFA

I Analog Input (Active High)—Complementary Reference Clock Input A.

5 REFB I Analog Input (Active High)—Reference Clock Input B. 6 13

REFB CS

I Analog Input (Active High)—Complementary Reference Clock Input B. I Digital Input Chip Select (Active Low).

14 SCLK I Serial Data Clock. 15 SDIO I/O Digital Serial Data Input/Output. 7 RESET I

Digital Input (Active High). Resets internal logic to default states. This pin has an internal 100 kΩ

pull-up resistor, so the default state of the device is reset. 11 XTL0 I Pin for Connecting an External Crystal (20 MHz to 30 MHz). 12 XTL1 I Pin for Connecting an External Crystal (20 MHz to 30 MHz). 33 OUT1 O Square Wave Clocking Output 1. 32

OUT1

O Complementary Square Wave Clocking Output 1.

29 OUT2 O Square Wave Clocking Output 2. 28

OUT2

17 LF I/O

O Complementary Square Wave Clocking Output 2.

Loop Filter Node for the Output PLL. Connect an external 12 nF capacitor (100 nF in 19.44 MHz

mode) from this pin to Pin 22 ( LDO_VCO). 26 OUTPUT PLL LOCKED O Active High Locked Status Indicator for the Output PLL. 25 INPUT PLL LOCKED O Active High Locked Status Indicator for the Input PLL. 16 OUTSEL I

Logic 0 selects LVDS, and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2

when the outputs are not under SPI port control. Can be overridden via the programming registers. 8 LDO_IPDIG P/O LDO Decoupling Pin. Connect a 0.47 F decoupling capacitor from this pin to ground. 10 LDO_XTAL P/O LDO Decoupling Pin. Connect a 0.47 F decoupling capacitor from this pin to ground. 22 LDO_VCO P/O LDO Decoupling Pin. Connect a 0.47 F decoupling capacitor from this pin to ground. 24 LDO_1.8 P/O LDO Decoupling Pin. Connect a 0.47 F decoupling capacitor from this pin to ground. 35 A0 I Control Pin. Selects preset values for the REFA dividers. 36 A1 I Control Pin. Selects preset values for the REFA dividers. 37 A2 I Control Pin. Selects preset values for the REFA dividers. 38 A3 I Control Pin. Selects preset values for the REFA dividers.

1

ND

OUT1

VDD

A0

A1

OUT

G

32

31

33

34

35

36

30 GND 29 OUT2 28

OUT2 27 VDD 26 OUT PUT PLL LOCKED 25 INPUT PLL LOCKED 24 LDO _1.8 23 VDD 22 LDO_VCO 21 Y0

15

17

16

18

19

20

LF

Y3

Y2

SDIO

Y1

UTSEL O

07805-003

Rev. B | Page 9 of 40

AD9551

Pin No. Mnemonic Type

39 B0 I Control Pin. Selects preset values for the REFB dividers. 40 B1 I Control Pin. Selects preset values for the REFB dividers. 1 B2 I Control Pin. Selects preset values for the REFB dividers. 2 B3 I Control Pin. Selects preset values for the REFB dividers. 21 Y0 I Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. 20 Y1 I Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. 19 Y2 I Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. 18 Y3 I Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. EP Exposed Die Pad The exposed die pad must be connected to GND.

1

P = power, I = input, O = output, I/O = input/output, P/O = power/output.

1

Description

Rev. B | Page 10 of 40

AD9551

m

TYPICAL PERFORMANCE CHARACTERISTICS

–20 –30

–40

–50 –60

–70

–80

–90

–100 –110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

–170 –180

100 1k 10k 100k 1M 10M 100M

FREQUENCY OF FSET F ROM CARRIER (Hz)

CARRIER 622.080005MHz 0.8813dB

RMS JITTER:

0.827ps (12kHz TO 20MHz)

0.618ps (50kHz TO 80MHz)

Figure 4. Phase Noise, Fractional-N

= 622.08 MHz, f

(f

IN

= 622.08 MHz, f

OUT1

= 26 MHz)

XTAL

–20 –30

–40

–50 –60

–70

–80

–90

–100 –110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

4

07805-00

–170 –180

100 1k 10k 100k 1M 10M 100M

FREQUENCY OF FSET F ROM CARRIER (Hz)

Figure 7. Phase Noise, Integer-N

= 622.08 MHz, f

(f

IN

CARRIER 619.666689MHz 0.8705dB

RMS JITTER:

0.773ps (12kHz TO 20MHz)

0.559ps (50kHz TO 80MHz)

= 619.67 MHz, f

OUT1

= 26 MHz)

XTAL

07805-005

–20 –30

–40

–50 –60

–70

–80

–90

–100 –110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

–170 –180

100 1k 10k 100k 1M 10M 100M

FREQUENCY OF FSET F ROM CARRIER (Hz)

CARRIER 622.080027MHz 0.5414dB

RMS JITTER:

1.336ps (12kHz TO 20MHz)

0.463ps (50kHz TO 80MHz)

Figure 5. Phase Noise, 19.44 MHz Mode, Fractional-N

= 19.44 MHz, f

(f

IN

5

0

–5

–10

–15

–20

1.0

–25

0.5

JITTER TRANSFER (dB)

0

–30

–0.5

–1.0

–35

–40

10 100

10 100 1k 10k 100k

= 622.08 MHz, f

OUT1

FREQUENCY OFFSET (Hz)

= 52 MHz)

XTAL

Figure 6. Jitter Transfer (Minimal Peaking)

(Register 0x33[7] = 0)

–20 –30

–40

–50 –60

–70

–80

–90

–100 –110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

6

07805-00

–170 –180

100 1k 10k 100k 1M 10M 100M

FREQUENCY OF FSET F ROM CARRIER (Hz)

CARRIER 619.666712MHz 0.6233dB

RMS JITTER:

1.327ps (12kHz TO 20MHz)

0.438ps (50kHz TO 80MHz)

07805-007

Figure 8. Phase Noise, 19.44 MHz Mode, Integer-N

= 19.44 MHz, f

(f

IN

5

0

–5

–10

–15

–20

1.0

–25

0.5

JITTER TRANSFER (dB)

–30

0

–0.5

–35

–1.0

10 100

8

07805-00

–40

10 100 1k 10k 100k

= 619.67 MHz, f

OUT1

FREQUENCY OFFSET (Hz)

= 52 MHz)

XTAL

07805-009

Figure 9. Jitter Transfer (Nominal Peaking)

(Register 0x33[7] = 1)

Rev. B | Page 11 of

40

AD9551

35

25

30

25

20

15

SUPPLY CURRENT (mA)

10

5 100 1k

FREQUENCY (MHz)

LVPECL

LVDS (STRONG)

LVDS (WEAK)

Figure 10. Supply Current vs. Output Frequency— LVPECL and LVDS

(10 pF Load)

1.6

1.4

1.2

1.0

0.8

AMPLITUDE (V p-p)

0.6

LVPECL

LVDS (STRONG)

LVDS (WEAK)

20

15

10

SUPPLY CURRENT (mA)

5

024

07805-

0

0 50 100 150 200 250

FREQUENCY (MHz )

07805-025

Figure 13 Supply Current vs. Output Frequency—CMOS

(10 pF Load)

4.0

3.5

3.0

2.5

2.0

1.5

AMPLITUDE (V p-p)

1.0

0.5

20pF

5pF

10pF

0.4 0 200 400 600 800 1000

FREQUENCY (MHz )

028

07805-

Figure 11. Peak-to-Peak Output Voltage vs. Frequency—LVPECL and LVDS

(10 pF Load)

60

55

DUTY CYCLE (%)

LVDS (WEAK) LVDS (STRONG) LVPECL

50

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

07805-026

Figure 12. Duty Cycle vs. Output Frequency—LVPECL and LVDS

(10 pF Load)

0

0 100 200 300 400 500

FREQUENCY (MHz)

Figure 14. Peak-to-Peak Output Voltage vs. Frequency—CMOS

55

54

53

52

DUTY CYCL E (%)

51

50

0 100 200 300

FREQUENCY (MHz )

5pF 10pF 20pF

Figure 15. Duty Cycle vs. Output Frequency—CMOS

07805-029

027

07805-

Rev. B | Page 12 of 40

ANALOG DEVICES AD9551 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

BASIC BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

REFERENCE CLOCK INPUT CHARACTERISTICS

OUTPUT CHARACTERISTICS

JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH)

CRYSTAL OSCILLATOR CHARACTERISTICS

POWER CONSUMPTION

LOGIC INPUT PINS

RESET PIN

LOGIC OUTPUT PINS

SERIAL CONTROL PORT

SERIAL CONTROL PORT TIMING

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS