ANALOG DEVICES AD9523-1 Service Manual

Low Jitter Clock Generator with

14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

FEATURES

Output frequency: <1 MHz to 1 GHz Start-up frequency accuracy: <±100 ppm (determined by

VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of ½ period of VCO

output divider Output-to-output skew: <50 ps Duty cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <150 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz Broadband timing jitter: 124 fs Digital lock detect Nonvolatile EEPROM stores configuration settings SPI- and I²C-compatible serial control port Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with

external VCXO Phase detector rate of 300 kHz to 75 MHz Redundant reference inputs Auto and manual reference switchover modes

Revertive and nonrevertive switching Loss of reference detection with holdover mode Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

PLL2

Phase detector rate of up to 250 MHz Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

AD9523-1

FUNCTIONAL BLOCK DIAGRAM

OSC_IN, OSC_IN

AD9523-1

REFA, REFA

REFB, REFB

REF_TEST

SCLK/SCL

SDIO/ SDA

SDO

PLL1

CONTROL

INTERFACE

(SPI AND I

EEPROM

2

PLL2

C)

ZERO

DELAY

ZD_IN, ZD_IN

DIVIDE- BY-

3, 4, 5

DIVIDE- BY-

3, 4, 5

Figure 1.

8 OUTPUTS

6 OUTPUTS

14-CLOCK

DISTRIBUTI ON

GENERAL DESCRIPTION

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.

The AD9523-1 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.

An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

OUT0, OUT0

OUT3, OUT3

OUT10, OUT10

OUT13, OUT13

OUT4, OUT4

OUT9, OUT9

09278-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9523-1

REVISION HISTORY

3/11—Rev. A to Rev. B

Added Table Summary, Table 8 ...................................................... 7

Changes to Figure 24...................................................................... 21

Changes to EEPROM Operations Section and Writing to the

EEPROM Section............................................................................ 35

Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30.................... 40

Changes to Bits[4:3], Table 40....................................................... 47

Rev. B | Page 2 of 60

12/10—Rev. 0 to Rev. A

Changes to General Description Section .......................................1

Changes to Frequency Range, Table 11 ..........................................9

Changes to PLL2 General Description Section.......................... 23

Changes to Table 47, Address 0x0F3, Bit 1 ................................. 48

10/10—Revision 0: Initial Version

AD9523-1

SPECIFICATIONS

f

= 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, f

VCXO

Typical is given for VDD = 3.3 V ± 5%, and T T

(−40°C to +85°C) variation, as listed in Tabl e 1.

A

= 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and

A

CONDITIONS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE

VDD3_PLL, Supply Voltage for PLL1 and PLL2 3.135 3.3 3.465 V 3.3 V ± 5%

VDD3_VCO, Supply Voltage for VCO 3.135 3.3 3.465 V 3.3 V ± 5%

VDD3_REF, Supply Voltage Clock Output Drivers Reference 3.135 3.3 3.465 V 3.3 V ± 5%

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 3.135 3.3 3.465 V 3.3 V ± 5%

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 1.768 1.8 1.832 V 1.8 V ± 5%

TEMPERATURE RANGE, TA −40 +25 +85 °C

1

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,

respectively) and Supply Voltage Clock Output OUT1,

OUT1

(Pin 65 and Pin 64, respectively).

SUPPLY CURRENT

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS

VDD3_PLL, Supply Voltage for PLL1 and PLL2 37 41.9 mA Decreases by 9 mA typical if REFB is turned off

VDD3_VCO, Supply Voltage for VCO and VCO Divider M1 70 75.8 mA All outputs use VCO Divider M1

VDD3_REF, Supply Voltage Clock Output Drivers Reference

VCO Divider M1 Enabled

LVPECL Mode, LVDS Mode 4 5.1 mA

HSTL Mode, CMOS Mode 3 3.6 mA

VCO Divider M2 Enabled

LVPECL Mode, LVDS Mode 26 30.1 mA

HSTL Mode, CMOS Mode 24.5 28.6 mA

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 3.2 5.8 mA Current for each divider: f = 122.88 MHz

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 6.4 12 mA Current for each divider: f = 983.04 MHz

CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF Channel x control register, Bit 4 = 0

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11.5 13.2 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 40 45 mA f = 983.04 MHz

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz

LVPECL Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 13 14.4 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 41 46.5 mA f = 983.04 MHz

= 2949.12 MHz, doubler is on, unless otherwise noted.

VCO

OUT0

(Pin 68 and Pin 67,

Use VCO Divider M1; only one output driver is turned on; for each additional output that is turned on, the current increments by 1.2 mA maximum

Use VCO Divider M1; values are independent of the number of outputs turned on

Use VCO Divider M2; only one output driver is turned on; for each additional output that is turned on, the current increments by 1.2 mA maximum

Use VCO Divider M2; values are independent of the number of outputs turned on

Rev. B | Page 3 of 60

AD9523-1

Parameter Min Typ Max Unit Test Conditions/Comments

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 20 24.2 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 50 59.1 mA f = 983.04 MHz

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 14 16.7 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 42.5 49 mA f = 983.04 MHz

CMOS Mode (Single-Ended)

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 2 2.4 mA f = 15.36 MHz, 10 pF Load

CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON Channel x control register, Bit 4 = 1

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 10 10.8 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 29.8 mA f = 983.04 MHz

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz

LVPECL Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.4 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 28 31.2 mA f = 983.04 MHz

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 20 24.3 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 50 59.1 mA f = 983.04 MHz

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.7 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 31.8 mA f = 983.04 MHz

1

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,

respectively) and Supply Voltage Clock Output OUT1,

OUT1

(Pin 65 and Pin 64, respectively).

OUT0

(Pin 68 and Pin 67,

Rev. B | Page 4 of 60

AD9523-1

POWER DISSIPATION

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION Does not include power dissipated in termination resistors

Typical Configuration 898 984.7 mW

PD, Power-Down

74 98.2 mW

INCREMENTAL POWER DISSIPATION

Base Typical Configuration 393 434.7 mW

Switched to One Input,

−28.5 −8 mW Running at 30.72 MHz

Reference Single-Ended Mode

Switched to Two Inputs,

26 44.6 mW Running at 30.72 MHz

Reference Differential Mode

Switched to Two Inputs,

−27.5 −5.1 mW Running at 30.72 MHz

Reference Single-Ended Mode VCO Divider M2 76 88.3 mW Incremental power increase VCO Divider M2 (OUT4) from base typical Output Distribution, Driver On Incremental power increase (OUT1) from base typical

LVDS Mode

3.5 mA 29 34.8 mW Single 3.5 mA LVDS output at 122.88 MHz

88 105.6 mW Single 3.5 mA LVDS output at 983.04 MHz

7 mA 43 50 mW Single 7 mA LVDS output at 122.88 MHz

141 164 mW Single 7 mA LVDS output at 983.04 MHz

LVPECL Mode 46 51 mW Single LVPECL output at 122.88 MHz

144 159 mW Single LVPECL output at 983.04 MHz

HSTL Mode

8 mA 44 51 mW Single 8 mA HSTL output at 122.88 MHz 143 165 mW Single 8 mA HSTL output at 983.04 MHz 16 mA 48 55 mW Single 16 mA HSTL output at 122.88 MHz

153 176 mW Single 16 mA HSTL output at 983.04 MHz

CMOS Mode 6.6 7.9 mW Single 3.3 V CMOS output at 15.36 MHz

9.9 11.9 mW Dual complementary 3.3 V CMOS output at 15.36 MHz

9.9 11.9 mW Dual in-phase 3.3 V CMOS output at 15.36 MHz

Output Distribution, Driver On Lower power mode on, (Channel x control register, Bit 4 = 1)

LVDS Mode

3.5 mA 28.5 33.6 mW Single 3.5 mA LVDS output at 122.88 MHz

88 105.6 mW Single 3.5 mA LVDS output at 983.04 MHz

7 mA 37 42.9 mW Single 7 mA LVDS output at 122.88 MHz

98 113.7 mW Single 7 mA LVDS output at 983.04 MHz

LVPECL Mode 40.5 46 mW Single LVPECL output at 122.88 MHz

100 110 mW Single LVPECL output at 983.04 MHz

HSTL Mode

8 mA 34 39.1 mW Single 8 mA HSTL output at 122.88 MHz

94 108.1 mW Single 8 mA HSTL output at 983.04 MHz

16 mA 48 55.2 mW Single 16 mA HSTL output at 122.88 MHz

153 176 mW Single 16 mA HSTL output at 983.04 MHz

Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz, 3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 singleended CMOS 10 pF load at 122.88 MHz, 1 differential input reference at 30.72 MHz; f

= 122.88 MHz, f

VCXO

= 2949.12 MHz, VCO Divider M1

VCO

at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz PD pin pulled low, with typical configuration conditions

Absolute total power with clock distribution; 1 LVPECL output (OUT0) running at 122.88 MHz; 1 differential input reference at 30.72 MHz;

= 122.88 MHz, f

f

VCXO

= 2949.12 MHz, VCO Divider M1 at 3; VCO

VCO

Divider M2 is off

Rev. B | Page 5 of 60

AD9523-1

REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

DIFFERENTIAL MODE

Input Frequency Range 400 MHz Input Slew Rate (OSC_IN) 400 V/µs

Common-Mode Internally

Generated Input Voltage Input Common-Mode Range 1.025 1.475 V For dc-coupled LVDS (maximum swing) Differential Input Voltage,

Sensitivity Frequency < 250 MHz

Differential Input Voltage,

Sensitivity Frequency > 250 MHz

Differential Input Resistance 4.8 kΩ Differential Input Capacitance 1 pF Duty Cycle

Pulse Width Low 1 ns

Pulse Width High 1 ns

CMOS MODE, SINGLE-ENDED INPUT

Input Frequency Range 250 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V Input Capacitance 1 pF Duty Cycle

Pulse Width Low 1.6 ns

Pulse Width High 1.6 ns

0.6 0.7 0.8 V

100 mV p-p

200 mV p-p

Minimum limit imposed for jitter performance

Capacitive coupling required; can accommodate single-ended input by ac grounding of unused input; instantaneous voltage on either pin must not exceed the 1.8 V dc supply rails

Duty cycle limits are set by pulse width high and pulse width low

OSC_CTRL OUTPUT CHARACTERISTICS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT VOLTAGE

High VDD3_PLL − 0.15 V R Low 150 mV

LOAD

> 20 kΩ

REF_TEST INPUT CHARACTERISTICS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

REF_TEST INPUT

Input Frequency Range 250 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V

Rev. B | Page 6 of 60

AD9523-1

PLL1 OUTPUT CHARACTERISTICS

Table 7.

Parameter1 Min Typ Max Unit Test Conditions/Comments

MAXIMUM OUTPUT FREQUENCY 250 MHz

Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load Duty Cycle 45 50 55 % f = 250 MHz

OUTPUT VOLTAGE HIGH Output driver static

VDD3_PLL − 0.25 V Load current = 10 mA VDD3_PLL − 0.1 V Load current = 1 mA

OUTPUT VOLTAGE LOW Output driver static

0.2 V Load current = 10 mA

0.1 V Load current = 1 mA

1

CMOS driver strength: strong (see Table 52).

OUT0, OUT0 TO OUT13, OUT13 DISTRIBUTION OUTPUT CHARACTERISTICS

Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,

0x190[7] = 1 and 0x192[7:2] = 1.)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL MODE

Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers Rise Time/Fall Time (20% to 80%) 117 147 ps 100 Ω termination across output pair Duty Cycle 47 50 52 % f < 500 MHz 43 48 52 % f = 500 MHz to 800 MHz 40 49 54 % f = 800 MHz to 1 GHz Differential Output Voltage Swing 643 775 924 mV

Common-Mode Output Voltage VDD – 1.5 VDD − 1.4 VDD − 1.25 V Output driver static

SCALED HSTL MODE, 16 mA

Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers Rise Time/Fall Time (20% to 80%) 112 141 ps 100 Ω termination across output pair Duty Cycle 47 50 52 % f < 500 MHz 44 48 51 % f = 500 MHz to 800 MHz 40 49 54 % f = 800 MHz to 1 GHz Differential Output Voltage Swing 1.3 1.6 1.7 mV Nominal supply

Supply Sensitivity 0.6

Common-Mode Output Voltage VDD − 1.76 VDD − 1.6 VDD − 1.42 V

LVDS MODE, 3.5 mA

Maximum Output Frequency 1 GHz Rise Time/Fall Time (20% to 80%) 138 161 ps 100 Ω termination across output pair Duty Cycle 48 51 53 % f < 500 MHz 43 49 53 % f = 500 MHz to 800 MHz 41 49 55 % f = 800 MHz to 1 GHz Differential Output Voltage Swing

Balanced 247 454 mV

Unbalanced 50 mV

Common-Mode Output Voltage 1.125 1.375 V Output driver static Common-Mode Difference 50 mV

Short-Circuit Output Current 3.5 24 mA Output driver static

Rev. B | Page 7 of 60

mV/ mV

Magnitude of voltage across pins; output driver static

Change in output swing vs. VDD3_OUT[x:y] (∆V

Voltage swing between output pins; output driver static

Absolute difference between voltage swing of normal pin and inverted pin

Voltage difference between output pins; output driver static

/∆VDD3)

OD

AD9523-1

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS MODE

Maximum Output Frequency 250 MHz Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load Duty Cycle 45 50 55 % f = 250 MHz Output Voltage High Output driver static

VDD − 0.25 V Load current = 10 mA

VDD − 0.1 V Load current = 1 mA

Output Voltage Low Output driver static

0.2 V Load current = 10 mA

0.1 V Load current = 1 mA

TIMING ALIGNMENT CHARACTERISTICS

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT TIMING SKEW

Between Outputs in Same Group1

LVPECL, HSTL, and LVDS

Between LVPECL, HSTL, and

30 183 ps

LVDS Outputs

CMOS

Between CMOS Outputs 100 300 ps Single-ended, true phase, high-Z mode Mean Delta Between Groups1 50 Adjustable Delay 0 63 Steps Resolution step; for example, 8 × 0.5/1 GHz

Resolution Step 500 ps ½ period of 1 GHz

Zero Delay

Between Input Clock Edge on

150 500 ps REFA or REFB to ZD_IN Input Clock Edge, External Zero Delay Mode

1

There are three groups of outputs. They are as follows: the top outputs group, consisting of OUT0, OUT1, OUT2, and OUT3; the right outputs group, consisting of

OUT4, OUT5, OUT6, OUT7, OUT8, and OUT9; and the bottom outputs group, consisting of OUT10, OUT11, OUT12, and OUT13.

Delay off on all outputs; maximum deviation between rising edges of outputs; all outputs are on, unless otherwise noted

PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA,

= 10 kΩ, antibacklash pulse width is

R

ZERO

at maximum, BW = 40 Hz, REFA and ZD_IN are set to differential mode

Rev. B | Page 8 of 60

AD9523-1

JITTER AND NOISE CHARACTERISTICS

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

LVPECL Mode, HSTL Mode, LVDS Mode 109 fs Integrated BW = 200 kHz to 5 MHz 115 fs Integrated BW = 200 kHz to 10 MHz 150 fs Integrated BW = 12 kHz to 20 MHz 177 fs Integrated BW = 10 kHz to 61 MHz 187 fs Integrated BW = 1 kHz to 61 MHz 124 fs Integrated BW = 1 MHz to 61 MHz

PLL2 CHARACTERISTICS

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

VCO (ON CHIP)

Frequency Range 2940 3100 MHz Gain 45 MHz/V

PLL2 FIGURE OF MERIT (FOM) −226 dBc/Hz MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Minimum and Low 250 MHz Maximum and High 125 MHz

Application example based on a typical setup (see Table 3); f = 122.88 MHz

LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

VOLTAGE

Input High 2.0 V Input Low 0.8 V

INPUT LOW CURRENT ±80 ±250 µA

CAPACITANCE 3 pF RESET TIMING

Pulse Width Low 50 ns Inactive to Start of Register

Programming

SYNC TIMING

Pulse Width Low 1.5 ns High speed clock is the CLK input signal

100 ns

The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523-1

Rev. B | Page 9 of 60

AD9523-1

STATUS OUTPUT PINS—STATUS1, STATUS0

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

VOLTAGE

Output High 2.94 V Output Low 0.4 V

SERIAL CONTROL PORT—SPI MODE

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

Voltage

Input Logic 1 2.0 V Input Logic 0 0.8 V

Current

Input Logic 1 30 µA Input Logic 0 −110 µA

Input Capacitance 2 pF

SCLK (INPUT) IN SPI MODE

Voltage

Input Logic 1 2.0 V Input Logic 0 0.8 V

Current

Input Logic 1 240 µA Input Logic 0 1 µA

Input Capacitance 2 pF

SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)

Voltage

Input Logic 1 2.0 V Input Logic 0 0.8 V

Current

Input Logic 1 1 µA Input Logic 0 1 µA

Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t

) 25 MHz

SCLK

8 ns

HIGH

12 ns

LOW

SDIO to SCLK Setup, tDS 3.3 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 14 ns CS to SCLK Setup, tS

CS to SCLK Setup and Hold, tS, tC CS Minimum Pulse Width High, t

PWH

CS has an internal 40 kΩ pull-up resistor

The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523-1

SCLK has an internal 40 kΩ pull-down resistor in SPI mode but not in I2C mode

10 ns 0 ns 6 ns

Rev. B | Page 10 of 60

AD9523-1

SERIAL CONTROL PORT—I²C MODE

VDD = VDD3_REF, unless otherwise noted.

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

SDA, SCL (WHEN INPUTTING DATA)

Input Logic 1 Voltage 0.7 × VDD V Input Logic 0 Voltage 0.3 × VDD V Input Current with an Input Voltage Between

0.1 × VDD and 0.9 × VDD Hysteresis of Schmitt Trigger Inputs 0.015 × VDD V Pulse Width of Spikes That Must Be

Suppressed by the Input Filter, t

SPIKE

SDA (WHEN OUTPUTTING DATA)

Output Logic 0 Voltage at 3 mA Sink Current 0.4 V Output Fall Time from VIH

MIN

to VIL

MAX

with

a Bus Capacitance from 10 pF to 400 pF

TIMING

Clock Rate (SCL, f

) 400 kHz

I2C

Bus Free Time Between a Stop and Start

Condition, t

IDLE

Setup Time for a Repeated Start Condition,

t

SET; STR

Hold Time (Repeated) Start Condition, t

Setup Time for a Stop Condition, t Low Period of the SCL Clock, t High Period of the SCL Clock, t SCL, SDA Rise Time, t SCL, SDA Fall Time, t Data Setup Time, t Data Hold Time, t

20 + 0.1 C

RISE

20 + 0.1 C

FAL L

100 ns

SET; DAT

100 880 ns

HLD; DAT

Capacitive Load for Each Bus Line, C

1

CB is the capacitance of one bus line in picofarads (pF).

2

According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL

falling edge.

HLD; STR

SET; STP

1.3 µs

LOW

0.6 µs

HIGH

1

400 pF

B

−10 +10 µA

50 ns

1

20 + 0.1 C

250 ns

B

Note that all I

(0.3 × VDD) and VIL

VIH

MIN

1.3 µs

0.6 µs

After this period, the first clock pulse is generated

0.6 µs

1

300 ns

B

1

300 ns

B

This is a minor deviation from the original I²C specification of 0 ns minimum2

2

C timing values are referred to

levels (0.7 × VDD)

MAX

Rev. B | Page 11 of 60

AD9523-1

ABSOLUTE MAXIMUM RATINGS

Table 16.

Parameter Rating

VDD3_PLL, VDD3_REF, VDD3_OUT[x:y],

−0.3 V to +3.6 V

LDO_VCO to GND REFA, REFA, REFB, REFB to GND SCLK/SCL, SDIO/SDA, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3

, OUT4, OUT4, OUT5, OUT5,

−0.3 V to +3.6 V

OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,

OUT9, OUT9

, OUT10, OUT10, OUT11, OUT11, OUT12, OUT12, OUT13, OUT13 to GND

SYNC, RESET, PD, REF_SEL to GND

−0.3 V to +3.6 V STATUS0, STATUS1 to GND −0.3 V to +3.6 V SP0, SP1, EEPROM_SEL to GND −0.3 V to +3.6 V VDD1.8_OUT[x:y], LDO_PLL1, LDO_DIV_M1

2 V

to GND Junction Temperature1 115°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 17 for θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 17. Thermal Resistance

Package Type

72-Lead LFCSP,

10 mm × 10 mm

1

Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Additional power dissipation information can be found in the

Power Dissipation and Thermal Considerations section.

ESD CAUTION

Airflow Velocity (m/sec) θ

1, 2

1, 3

θ

JA

JC

1, 4

θ

JB

1, 2

Ψ

Unit

JT

0 21.3 1.7 12.6 0.1 °C/W

1.0 20.1 0.2 °C/W

2.5 18.1 0.3 °C/W

Rev. B | Page 12 of 60

AD9523-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PLL1_OUT

ZD_IN

VDD1.8_OUT[0:1]

OUT0

VDD3_OUT[0:1]

OUT1

VDD1.8_OUT[2:3]

OUT2

VDD3_OUT[2:3]

OUT3

EEPROM_SEL

STATUS0/SP0

STATUS1/SP1

7271706968676665646362616059585756

55

REFA

REFA REFB REFB

PD

1 2 3 4 5 6 7 8 9

10

11 12 13 14 15 16 17SYNC 18VDD3_REF

PIN 1 INDICATOR

AD9523-1

TOP VIEW

(Not to Scale)

192021222324252627282930313233

CS

SDO

OUT13

RESET

SDIO/SDA

SCLK/SCL

OUT13

REF_TEST

VDD3_OUT[12:13]

OUT11

OUT12

OUT11

OUT12

VDD1.8_OUT[12:13]

34

OUT10

VDD3_OUT[10: 11]

54

VDD1.8_OUT[4:5]

53

OUT4

52

OUT4

51

VDD3_OUT[4:5]

50

OUT5

49

OUT5

48

VDD1.8_OUT[6:7]

47

OUT6

46

OUT6

45

VDD3_OUT[6:7]

44

OUT7

43

OUT7

42

VDD1.8_OUT[8:9]

41

OUT8

40

OUT8

39

VDD3_OUT[8:9]

38

OUT9

37

OUT9

35OUT10

36VDD1.8_OUT [10: 11]

LDO_PLL1 VDD3_PLL

LF1_EXT_CAP

OSC_CTRL

OSC_IN OSC_IN

LF2_EXT_CAP

LDO_VCO

VDD3_VCO

LDO_DIV_M1

REF_SEL

NOTES

1. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THEANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

09278-002

Table 18. Pin Function Descriptions

Pin No. Mnemonic Type

1 LDO_PLL1 P/O

1

Description

1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 F decoupling capacitor from this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close

proximity to the device. 2 VDD3_PLL P 3.3 V Supply PLL1 and PLL2. Use the same supply as VCXO. 3 REFA I

Reference Clock Input A. Along with REFA

, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 4

REFA

I

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input. 5 REFB I

Reference Clock Input B. Along with REFB

, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 6

REFB

I

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 7 LF1_EXT_CAP O PLL1 External Loop Filter Capacitor. Connect this pin to ground. 8 OSC_CTRL O Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator. 9 OSC_IN I

PLL1 Oscillator Input. Along with OSC_IN

, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 10

OSC_IN

I

Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Rev. B | Page 13 of 60

AD9523-1

Pin No. Mnemonic Type

11 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin. 12 LDO_VCO P/O

13 VDD3_VCO P 3.3 V Supply for VCO and VCO M1 Divider. 14 LDO_DIV_M1 P/O

15

PD 16 REF_SEL I Reference Input Select. This pin has an internal 40 kΩ pull-down resistor. 17

SYNC

18 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference and VCO Divider M2. 19

20

RESET

CS 21 SCLK/SCL I

22 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA). 23 SDO O

24 REF_TEST I Test Input to PLL1 Phase Detector. 25

OUT13

26 OUT13 O

27 VDD3_OUT[12:13] P 3.3 V Supply for Output 12 and Output 13 Clock Drivers. 28

OUT12

29 OUT12 O

30 VDD1.8_OUT[12:13] P 1.8 V Supply for Output 12 and Output 13 Clock Dividers. 31

OUT11

32 OUT11 O

33 VDD3_OUT[10:11] P 3.3 V Supply for Output 10 and Output 11 Clock Drivers. 34

OUT10

35 OUT10 O

36 VDD1.8_OUT[10:11] P 1.8 V Supply for Output 10 and Output 11 Clock Dividers. 37

OUT9

38 OUT9 O

39 VDD3_OUT[8:9] P 3.3 V Supply for Output 8 and Output 9 Clock Drivers. 40

OUT8

41 OUT8 O

42 VDD1.8_OUT[8:9] P 1.8 V Supply for Output 8 and Output 9 Clock Dividers. 43

OUT7

44 OUT7 O

1

Description

2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 F decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device.

1.8 V LDO Regulator Decoupling Pin for VCO Divider M1. Connect a 0.47 F decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device.

I Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.

I

Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pullup resistor.

I

Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up resistor.

I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.

2

Serial Control Port Clock Signal for SPI Mode (SCLK) or I

C Mode (SCL). Data clock for serial program-

ming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.

Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin.

O

Complementary Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

Rev. B | Page 14 of 60

AD9523-1

Pin No. Mnemonic Type

45 VDD3_OUT[6:7] P 3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers. 46

OUT6

47 OUT6 O

48 VDD1.8_OUT[6:7] P 1.8 V Supply for Output 6 and Output 7 Clock Dividers. 49

OUT5

50 OUT5 O

51 VDD3_OUT[4:5] P 3.3 V Supply for Output 4 and Output 5 Clock Drivers. 52

OUT4

53 OUT4 O

54 VDD1.8_OUT[4:5] P 1.8 V Supply for Output 4 and Output 5 Clock Dividers. 55 STATUS1/SP1 I/O

56 STATUS0/SP0 I/O

57 EEPROM_SEL I

58

OUT3

59 OUT3 O

60 VDD3_OUT[2:3] P 3.3 V Supply for Output 2 and Output 3 Clock Drivers. 61

OUT2

62 OUT2 O

63 VDD1.8_OUT[2:3] P 1.8 V Supply for Output 2 and Output 3 Clock Dividers. 64

OUT1

65 OUT1 O

66 VDD3_OUT[0:1] P 3.3 V Supply for Output 0 and Output 1 Clock Drivers. 67

OUT0

68 OUT0 O

69 VDD1.8_OUT[0:1] P 1.8 V Supply for Output 0 and Output 1 Clock Dividers. 70 ZD_IN I

71

ZD_IN

72 PLL1_OUT O

EP EP, GND GND

1

P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.

1

Description

O

Complementary Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

Lock Detect and Other Status Signals (STATUS1)/I down resistor.

Lock Detect and Other Status Signals (STATUS0)/I down resistor.

EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9523-1 to load the hard-coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.

O

Complementary Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

O

Complementary Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output.

External Zero Delay Clock Input. Along with ZD_IN reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

I

Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in Register 0x1BA, Bit 4 (see Table 52).

Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.

2

C Address (SP1). This pin has an internal 40 kΩ pull-

2

C Address (SP0). This pin has an internal 40 kΩ pull-

, this pin is the differential input for the PLL

Rev. B | Page 15 of 60

AD9523-1

TYPICAL PERFORMANCE CHARACTERISTICS

f

= 122.88 MHz, REFA differential at 30.72 MHz, f

VCXO

60

50

40

HSTL = 16mA

= 2949.12 MHz, and doubler is off, unless otherwise noted.

VCO

45

40

35

30

CURRENT (mA)

20

10

0

0 200 400 600 800 1000 1200

HSTL = 8mA

FREQUENCY (MHz)

Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

HSTL Mode at 16 mA and 8 mA

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

0 200 400 600 800 1000 1200

LVD S = 7mA

LVD S = 3 .5m A

FREQUENC Y (MHz)

Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

LVDS Mode at 7 mA and 3.5 mA

25

20

CURRENT (mA)

15

10

5

0

0 200 400 600 800 1000 1200

09278-003

FREQUE NCY (MHz )

09278-005

Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode

35

30

25

20

15

CURRENT (mA)

10

5

0

0 100 200 300 400 500 600

09278-004

FREQUENCY (MHz)

20pF

10pF

2pF

09278-006

Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

CMOS Mode at 20 pF, 10 pF, and 2 pF Load

Rev. B | Page 16 of 60

AD9523-1

A

3.5

3.0

2.5

2.0

L SWING (V p-p)

1.5

1.0

DIFFERENTI

0.5

HSTL = 16mA

HSTL = 8mA

4.0

3.5

3.0

2.5

2.0

1.5

AMPLITUDE (V)

1.0

0.5

2pF

10pF

20pF

0

0 200 400 600 800 1000 1200

FREQUENC Y (MHz)

Figure 7. Differential Voltage Swing vs. Frequency;

HSTL Mode at 16 mA and 8 mA

1.6

1.4

1.2

1.0

0.8

L SWING (V p-p)

0.6

0.4

DIFFERENTI

0.2

0

0 200 400 600 800 1000 1200

FREQUENCY (MHz)

Figure 8. Differential Voltage Swing vs. Frequency, LVPECL Mode

1.4

1.2

LVD S = 7 mA

0

0 100 200 300 400 500 600

09278-007

FREQUENCY (MHz)

09278-010

Figure 10. Amplitude vs. Frequency and Capacitive Load;

CMOS Mode at 2 pF, 10 pF, and 20 pF Load

1

CH1 200mV 2. 5ns/DIV

09278-008

40.0GS/s

A CH1 104mV

09278-013

Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz

1.0

0.8

0.6

0.4

DIFFERENTIAL SWING (V p-p)

0.2

0

0 200 400 600 800 1000 1200

LVDS = 3.5mA

FREQUENCY (MHz)

Figure 9. Differential Voltage Swing vs. Frequency;

09278-009

1

CH1 500mV Ω 2.5ns/DIV

40.0GS/s

A CH1 80mV

Figure 12. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz

09278-049

LVDS Mode at 7 mA and 3.5 mA

Rev. B | Page 17 of 60

AD9523-1

–

80

–90

–100

1: 1kHz, –120.0dBc/Hz 2: 10kHz, –130.6dBc/Hz 3: 100kHz, –137.4dBc/Hz 4: 1MHz, –145.7dBc/Hz 5: 10MHz, –159.6dBc/Hz 6: 40MHz, –160.3dBc/Hz 7: 800kHz, –143.7dBc/Hz

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

–180

100 1k 10k 100k 1M 10M

1

2

3

NOISE: ANALYSIS RANGE x: START 10kHz TO STO P 40MHz INTG NOISE: –78.1dBc/40MHz RMS NOI SE: 175.4 µRAD

10.0mdeg RMS JITTER: 151.4fsec RESIDUAL FM: 2. 1kHz

7

FREQUENCY (Hz)

Figure 13. Phase Noise, Output = 184.32 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On

4

5

6

09278-113

80

–90

–100

1: 1kHz, –123.1dBc/Hz 2: 10kHz, –133.8dBc/Hz 3: 100kHz, –140.5dBc/Hz 4: 1MHz, –149.0Bc/Hz 5: 10MHz, –161.5dBc/Hz 6: 40MHz, –162.1dBc/Hz 7: 800kHz, –146.9dBc/Hz

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

NOISE: ANALYSIS RANGE x: START 1 0kHz TO STOP 40MHz

–160

INTG NOISE: –81.0dBc/40MHz RMS NOISE: 126.6µRAD

7.3mdeg

–170

RMS JITTER: 164.0fsec RESIDUAL FM: 1.7kHz

–180

100 1k 10k 100k 1M 10M

1

2

3

FREQUENCY (Hz)

Figure 15. Phase Noise, Output = 122.88 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On

7

4

5

6

09278-014

80

–90

–100

1: 1kHz, –118.3dBc/Hz 2: 10kHz, –127.5dBc/Hz 3: 100kHz, –126.0dBc/Hz 4: 1MHz, –151.8dBc/Hz 5: 10MHz, –159.6dBc/Hz 6: 40MHz, –160.3dBc/Hz 7: 800kHz, –149.5dBc/Hz

–110

–120

–130

1

2

3

–140

–150

PHASE NOISE (dBc/Hz)

NOISE: ANALYSIS RANGE x: START 10k Hz

–160

INTG NOISE: –73.1dBc/40MHz RMS NOISE: 312.0µRAD

17.9mdeg

–170

RMS JITTER: 269.4fsec RESIDUAL FM: 2. 0kHz

–180

100 1k 10k 100k 1M 10M

TO STOP 40MHz

FREQUENCY (Hz)

Figure 14. Phase Noise, Output = 184.32 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On;

Optimized for Low 800 kHz Offset Noise

80

–90

–100

1: 1kHz, –122.0Bc/Hz 2: 10kHz, –130.7dBc/Hz 3: 100kHz, –129.3dBc/Hz 4: 1MHz, –154.9dBc/Hz 5: 10MHz, –161.5dBc/Hz 6: 40MHz, –162.1dBc/Hz 7: 800kHz, –152.7dBc/Hz

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

7

4

5

6

–170

–180

100 1k 10k 100k 1M 10M

09278-012

1

2

NOISE: ANALYSIS RANGE x: START 10kHz

INTG NOISE: –76.3dBc/40MHz RMS NOISE: 217.0µRAD

12.4mdeg RMS JITTER: 281.1fsec RESIDUAL FM: 1.6kHz

TO STOP 40M Hz

FREQUENCY (Hz)

3

7

4

5

6

09278-015

Figure 16. Phase Noise, Output = 122.88 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On;

Optimized for Low 800 kHz Offset Noise

Rev. B | Page 18 of 60

ANALOG DEVICES AD9523-1 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

CONDITIONS

SUPPLY CURRENT

POWER DISSIPATION

OSC_CTRL OUTPUT CHARACTERISTICS

REF_TEST INPUT CHARACTERISTICS

PLL1 OUTPUT CHARACTERISTICS

TIMING ALIGNMENT CHARACTERISTICS

JITTER AND NOISE CHARACTERISTICS

PLL2 CHARACTERISTICS

STATUS OUTPUT PINS—STATUS1, STATUS0

SERIAL CONTROL PORT—SPI MODE

SERIAL CONTROL PORT—I²C MODE

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS