Analog Devices AD9481 Service Manual

8-Bit, 250 MSPS

FEATURES

DNL = ±0.35 LSB INL = ±0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 439 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs De-multiplexed CMOS outputs Power-down mode Clock duty cycle stabilizer

APPLICATIONS

Digital oscilloscopes Instrumentation and measurement Communications

Point-to-point radios Digital predistortion loops

GENERAL DESCRIPTION

The AD9481 is an 8-bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range.

To minimize system cost and power dissipation, the AD9481 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications.

The digital outputs are TTL/CMOS-compatible with an option of twos complement or binary output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture.

3.3 V A/D Converter AD9481

FUNCTIONAL BLOCK DIAGRAM

VREF SENSE

REFERENCE

VIN+ VIN–

DS+ DS–

CLK+ CLK–

T AND H

CLOCK

MGMT

PDWN S1

The AD9481 is available in a Pb-free, 44-lead, surface-mount package (TQFP-44) specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Superior linearity. A DNL of ±0.35 makes the AD9481

suitable for many instrumentation and measurement applications

2. Power-down mode. A power-down function may be exercised

to bring total consumption down to 15 mW.

3. De-multiplexed CMOS outputs allow for easy interfacing

with low cost FPGAs and standard logic.

AGND DRGND DRVDD AVDD

AD9481

PORT

A

8-BIT

8

ADC

PIPELINE

CORE

Figure 1.

LOGIC

PORTB8

8

D7A TO D0A

D7B TO D0B

DCO+ DCO–

05045-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9481

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 1.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits ACCURACY

No Missing Codes Full VI Guaranteed Offset Error 25°C I −40 40 mV Gain Error

1

Differential Nonlinearity (DNL) Full VI −0.85 ±0.35 0.85 LSB Integral Nonlinearity (INL) Full VI −0.9 ±0.26 0.9 LSB

TEMPERATURE DRIFT

Offset Error Full V 30 µV/°C Gain Error Full V 0.03 % FS/°C Reference Full V ±0.025 mV/°C

REFERENCE

Internal Reference Voltage Full VI 0.97 1.0 1.03 V Output Current I

Input Current

VREF

I

Input Current2 25°C I 10 µA

SENSE

2

3

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range Common-Mode Voltage Full VI 1.6 1.9 2.1 V Input Resistance Full VI 8.4 10 11.2 kΩ Input Capacitance 25°C V 4 pF Analog Bandwidth, Full Power 25°C V 750 MHz

POWER SUPPLY

AVDD Full IV 3.0 3.3 3.6 V DRVDD Full IV 3.0 3.3 3.6 V

Supply Currents

5

IAVDD

IDRVDD5 Full VI 39 42.5 mA Power Dissipation5 25°C V 439 mW Power-Down Dissipation 25°C V 15 37 mW Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and 1 V p-p input range).

2

Internal reference mode; SENSE = AGND.

3

External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD.

4

In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.

5

Supply current measured with rated encode and a 20 MHz analog input. Power dissipation measured with dc input, see the T section for power vs. clock

rate.

= −40°C, T

MIN

4

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

25°C I −6.0 6.0 % FS

25°C IV 1.5 mA 25°C I 100 µA

Full V 1 V p-p

Full VI 133 145 mA

erminology

Rev. 0 | Page 3 of 28

AD9481

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 2.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

CLOCK AND DS INPUTS (CLK+, CLK−, DS+, DS−)

Differential Input Full IV 200 mV p-p Common-Mode Voltage

1

Input Resistance Full VI 4.2 5.5 6.0 kΩ Input Capacitance 25°C V 4 pF

LOGIC INPUTS (PDWN, S1)

Logic 1 Voltage Full IV 2.0 V Logic 0 Voltage Full IV 0.8 V Logic 1 Input Current Full VI ±160 µA Logic 0 input Current Full VI 10 µA Input Resistance 25°C V 30 kΩ Input Capacitance 25°C V 4 pF

DIGITAL OUTPUTS

Logic 1 Voltage

2

Logic 0 Voltage Full VI 0.05 V Output Coding Full IV Twos complement or binary

1

The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.

2

Capacitive loading only.

= −40°C, T

MIN

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Full VI 1.38 1.5 1.68 V

Full VI DRVDD − 0.05 mV

Rev. 0 | Page 4 of 28

AD9481

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 3.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 19.7 MHz 25°C V 46 dB fIN = 70.1 MHz 25°C I 44.5 45.7 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 19.7 MHz 25°C V 45.9 dB fIN = 70.1 MHz 25°C I 44.4 45.7 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 19.7 MHz 25°C V 7.5 Bits fIN = 70.1 MHz 25°C I 7.2 7.5 Bits

WORST SECOND OR THIRD HARMONIC DISTORTION

fIN = 19.7 MHz 25°C V −64.8 dBc fIN = 70.1 MHz 25°C I −64.8 −54 dBc

WORST OTHER

fIN = 19.7 MHz 25°C V −68 dBc fIN = 70.1 MHz 25°C I −65.8 −56 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 19.7 MHz 25°C V −64.8 dBc fIN = 70.1 MHz 25°C I −64.8 −54 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

= 69.3 MHz, f

IN1

= 70.3 MHz 25°C V −64.9 dBc

IN2

1

DC and Nyquist bin energy ignored.

= −40°C, T

MIN

1

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Rev. 0 | Page 5 of 28

AD9481

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.

Table 4.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

CLOCK

Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full IV 20 MSPS Clock Pulse-Width High (tEH) Full IV 1.2 2 ns Clock Pulse-Width Low (tEL) Full IV 1.2 2 ns DS Input Setup Time (t DS Input Hold Time (t

OUTPUT PARAMETERS

Valid Time (tV)

2

Propagation Delay (tPD) Full VI 4 5.4 ns Rise Time (tR) 10% to 90% Full V 670 ps Fall Time (tF) 10% to 90% Full V 360 ps DCO Propagation Delay (t Data-to-DCO Skew (tPD − t A Port Data to DCO− Rising (t B Port Data to DCO+ Rising (t Pipeline Latency (A, B) Full IV 8 Cycles

APERTURE

Aperture Delay (tA) 25°C V 1.5 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms

OUT-OF-RANGE RECOVERY TIME 25°C V 1 Cycle

1

C

equals 5 pF maximum for all output switching specifications.

LOAD

2

Valid time is approximately equal to minimum tPD.

3

T

equals clock rising edge to DCO (+ or −) rising edge delay.

CPD

4

Data changing to (DCO+ or DCO−) rising edge delay.

5

T

, T

are both clock rate dependent delays equal to T

SKA

SKB

) Full IV 0.5 ns

SDS

) Full IV 0.5 ns

HDS

1

Full VI 2.5 ns

3

)

CPD

4

)

CPD

5

)

SKA

) Full IV 4 ns

SKB

− (Data to DCO skew).

CYCLE

Full VI 2.5 3.9 5.3 ns Full VI −0.5 +0.5 ns Full IV 4 ns

Rev. 0 | Page 6 of 28

AD9481

A

TIMING DIAGRAM

N–1

VIN

CLK+ CLK–

DS+ DS–

INTERLEAVED DATA OUT

PORT A

D7A TO D0

D7B TO D0B

STATIC INVALID N

PORT B

STATIC INVALID INVALID N+1

DCO+ DCO–

t

EH

t

HDS

STATIC

t

A

N

N+1

8 CYCLES

t

EL

1/f

S

t

SDS

N+7

N+8

t

PD

CPD

t

SKA

N+9

t

SKB

N+10

t

V

05045-002

Figure 2. Timing Diagram

Rev. 0 | Page 7 of 28

AD9481

ABSOLUTE MAXIMUM RATINGS

Thermal impedance (θJA) = 46.4°C/W (4-layer PCB).

Table 5.

Min.

Parameter

ELECTRICAL

AVDD (With respect to AGND) −0.5 V +4.0 V DRVDD

(With respect to DRGND) AGND (With respect to DRGND) −0.5 V +0.5 V Digital I/0

(With respect to DRGND) Analog Inputs

(With respect to AGND)

ENVIRONMENTAL

Operating Temperature −40°C +85°C Junction Temperature 150°C Storage Temperature 150°C

Rating

−0.5 V +4.0 V

−0.5 V DRVDD + 0.5 V

−0.5 V AVDD + 0.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Max. Rating

EXPLANATION OF TEST LEVELS

Table 6.

Level Description

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 28

AD9481

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DS+43DS–42S341AVDD40AGND39VIN+38VIN–37AGND36AVDD35AGND34VREF

44

CLK+

CLK– AVDD AGND

DRVDD DRGND

D7A (MSB)

D6A D5A D4A D3A

1

PIN 1

2 3 4 5 6 7 8 9

10

11

12

(Not to Scale)

14

15

AD9481

TOP VIEW

16

17

18

19

20

33

SENSE

32

AGND

31

AVDD

30

AVDD

29

PDWN

28

S1

27

DRGND

26

D7B (MSB)

25

D6B

24

D5B

23

D4B

Table 7. Pin Function Descriptions

Pin No. Name Description

1 CLK+ Input Clock—True 2 CLK− Input Clock—Complement 3 AVDD 3.3 V Analog Supply 4 AGND Analog Ground 5 DRVDD 3.3 V Digital Output Supply 6 DRGND Digital Ground 7 D7A Data Output Bit 7—Channel A (MSB) 8 D6A Data Output Bit 6—Channel A 9 D5A Data Output Bit 5—Channel A 10 D4A Data Output Bit 4—Channel A 11 D3A Data Output Bit 3—Channel A 12 D2A Data Output Bit 2—Channel A 13 D1A Data Output Bit 1—Channel A 14 D0A Data Output Bit 0—Channel A (LSB) 15 DRGND Digital Ground 16 DCO− Data Clock Output—Complement 17 DCO+ Data Clock Output—True 18 DRVDD 3.3 V Digital Output Supply 19 D0B Data Output Bit 0—Channel B (LSB) 20 D1B Data Output Bit 1—Channel B 21 D2B Data Output Bit 2—Channel B 22 D3B Data Output Bit 3—Channel B 23 D4B Data Output Bit 4—Channel B 24 D5B Data Output Bit 5—Channel B

D2A13D1A

D0A (LSB)

DCO–

DRGND

DCO+

DRVDD

Figure 3. Pin Configuration

Pin No. Name Description

25 D6B Data Output Bit 6—Channel B 26 D7B Data Output Bit 7—Channel B (MSB) 27 DRGND Digital Ground 28 S1

29 PDWN Power-Down Selection 30 AVDD 3.3 V Analog Supply 31 AVDD 3.3 V Analog Supply 32 AGND Analog Ground 33 SENSE Reference Mode Selection 34 VREF Voltage Reference Input/Output 35 AGND Analog Ground 36 AVDD 3.3 V Analog Supply 37 AGND Analog Ground 38 VIN− Analog Input—Complement 39 VIN+ Analog Input—True 40 AGND Analog Ground 41 AVDD 3.3 V Analog Supply 42 S3

43 DS−

44 DS+ Data Sync True (If Unused, Tie to DGND)

D0B (LSB)

D1B21D2B22D3B

05045-003

Data Format Select and Duty Cycle Stabilizer Select

DCO Enable Select (Tie to AVDD for DCO Active)

Data Sync Complement (If Unused, Tie to DRVDD)

Rev. 0 | Page 9 of 28

AD9481

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation

2

⎛

FULLSCALE

⎜

Z

⎜

=

Power

FULLSCALE

log10

INPUT

⎜

0.001

⎜ ⎜

⎝

⎞

rmsV

⎟ ⎟ ⎟ ⎟

⎟ ⎠

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Clock Pulse-Width/Duty Cycle

Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing

in the Clocking the AD9481 section. At a given clock rate,

t

EH

these specifications define an acceptable clock duty cycle.

Crosstalk

Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input)

SINAD

ENOB

=

MEASURED

6.02

dB1.76−

Gain Error

Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels.

Noise (for Any Range within the ADC)

This value includes both thermal and quantization noise.

SignalSNRFS

V

noise

⎛

××=

10.0010Z

⎜

⎜ ⎝

−−

10

⎞

dBFSdBcdBm

⎟

⎟ ⎠

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

Signal is the signal level within the ADC reported in dB below

full scale.

Rev. 0 | Page 10 of 28

AD9481

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power supply voltage.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc.

Two -Ton e SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (degrades as signal level is lowered) or in dBFS (always relates back to converter full scale).

Wors t Oth e r S p u r

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc.

Transient Response Time

The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Out-of-Range Recovery Time

This is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Rev. 0 | Page 11 of 28

AD9481

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, internal reference mode, unless otherwise noted.

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

–90

0408020 60 100 120

Figure 4. FFT: f

= 250 MSPS, AIN = 10.3 MHz @ −1 dBFS

S

(MHz)

SNR = 45.8dB H2 = –65.2dBc H3 = –63.2dBc SFDR = 63.2dBc

05045-004

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

–90

0408020 60 100 120

Figure 7. FFT: f

= 250 MSPS, AIN = 170 MHz @ −1 dBFS

S

(MHz)

SNR = 45.6dB H2 = –72.9dBc H3 = –65.2dBc SFDR = 59.6dBc

05045-007

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

–90

0408020 60 100 120

Figure 5. FFT: f

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

–90

0408020 60 100 120

Figure 6. FFT: f

= 250 MSPS, AIN = 70 MHz @ −1 dBFS, Single-Ended Input

S

= 250 MSPS, AIN = 70 MHz @ −1 dBFS

S

(MHz)

SNR = 45.8dB H2 = –68.5dBc H3 = –63.5dBc SFDR = 63.8dBc

SNR = 45.9dB H2 = –66.6dBc H3 = –70.1dBc SFDR = 65.9dBc

05045-005

05045-006

90

85

(dB)

80

75

70

65

60

55

50

45

40

0 40035030025020015010050

H3

H2

SFDR

SNR

SINAD

AIN (MHz)

Figure 8. Analog Inp ut Frequency Sweep,

= −1 dBFS, FS = 1 V, fS = 250 MSPS

A

IN

90

85

(dB)

80

75

70

65

60

55

50

45

40

0 40035030025020015010050

SFDR

H3

H2

SNR

SINAD

AIN (MHz)

Figure 9. Analog Inp ut Frequency Sweep,

=−1 dBFS, FS = 0.75 V, fS = 250 MSPS, External VREF Mode

A

IN

05045-008

05045-009

Rev. 0 | Page 12 of 28

AD9481

75

70

65

60

(dB)

55

50

45

40

0 300

SFDR

SNR

SINAD

SAMPLE CLOCK (MHz)

Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency,

= 70 MHz @ −1 dB

A

IN

25020015010050

05045-010

140

120

100

80

60

CURRENT (mA)

40

20

0

0 100 20050 150 250 300

Figure 13. I

SAMPLE CLOCK (MSPS)

and I

AVDD

DRVDD

A

= 70 MHz @ −1 dBFS

IN

I

AVDD

I

DRVDD

vs. Clock Rate, C

LOAD

05045-013

= 5 pF

80

70

60

50

40

(dB)

30

20

10

0

–70 0–10–20–30–40–50–60

Figure 11. SFDR vs. A

0

F1, F2 = –7dBFS 2F2–F1 = –65.9dBc

–10

2F1–F2 = –64.9dBc

–20

–30

–40

(dB)

–50

–60

–70

–80

–90

0408020 60 100 120

SFDR (dBc)

60dB REFERENCE LINE

ANALOG INPUT DRIVE LEVEL (dBFS)

Input Level; AIN = 70 MHz @ 250 MSPS

IN

SFDR (dBFS)

(MHz)

Figure 12. Two-Tone Intermodulation Distortion

(69.3 MHz and 70.3 MHz; f

= 250 MSPS)

S

05045-011

05045-012

50

49

48

DCS ON

47

46

45

(dB)

44

43

42

41

40

20 40 6030 50 70 80

CLOCK POSITIVE DUTY CYCLE (%)

DCS OFF

Figure 14. SNR, SINAD vs. Clock Pulse-Width High,

= 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off

A

IN

50.0

47.5

45.0

SNR, SINAD (dB)

42.5

40.0

0.5 1.10.9 1.50.7 1.3 1.7 1.9 EXTERNAL VREF VOLTAGE (V)

SNR

SINAD

SFDR

75

70

65

60

55

Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, A

70 MHz @ −1 dBFS, 250 MSPS

05045-014

SFDR (dBc)

05045-015

=

IN

Rev. 0 | Page 13 of 28

AD9481

2.0

70

1.5

1.0

0.5

0

–0.5

GAIN ERROR (%)

–1.0

–1.5

–2.0

–40–200 20406080

FS = 1V EXTERNAL REFERENCE

INTERNAL REFERENCE

TEMPERATURE (°C)

FS = 1V

Figure 16. Full-Scale Gain Error vs. Temperature,

= 70.3 MHz @ −0.5 dBFS, 250 MSPS

A

IN

70

65

60

55

(dB)

50

45

40

–40–200 20406080

TEMPERATURE (°C)

SFDR

SINAD

Figure 17. SINAD, SFDR vs. Temperature,

= 70 MHz @ −1 dBFS, 250 MSPS

A

IN

05045-016

05045-017

65

SFDR

60

(dB)

55

50

45

3.0 3.1 3.2 3.3 3.4 AVDD (V)

SINAD

Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage,

= 70.3 MHz @ −1 dBFS, 250 MSPS

A

IN

0.5

0.4

0.3

0.2

0.1

0

LSB

–0.1

–0.2

–0.3

–0.4

–0.5

0 50 100 150 200 250

CODE

Figure 20. Typical DNL Plot,

= 10.3 MHz @ −0.5 dBFS, 250 MSPS

A

IN

SNR

3.5 3.6

05045-019

05045-020

0.10

0.05

–0.05

CHANGE IN VREF (%)

–0.10

–0.15

0

2.7 3.63.53.43.33.23.13.02.92.8 AVDD (V)

Figure 18. VREF Sensitivity to AVDD

05045-018

Rev. 0 | Page 14 of 28

0.50

0.25

0

LSB

–0.25

–0.50

0 50 100 150 200 250

CODE

Figure 21. Typical INL Plot,

= 10.3 MHz @ −0.5 dBFS, 250 MSPS

A

IN

05045-021

AD9481

0.2

0.1

0

–0.1

–0.2

DELAY CHANGE (ps)

T

_R

–0.3

–0.4

–40 –20 200 406080

CPD

T

_R

PD

TEMPERATURE (°C)

TPD_F

T

CPD

Figure 22. Propagation Delay Sensitivity vs. Temperature

_F

05045-048

Rev. 0 | Page 15 of 28

AD9481

C

S

EQUIVALENT CIRCUITS

16.7kΩ 16.7kΩ

AVDD

VIN+

LK+

150Ω

1.2pF

25kΩ

Figure 23. Analog Inputs

AVDD

12kΩ

150Ω 150Ω

10kΩ

Figure 24. Clock Inputs

30kΩ

25kΩ

12kΩ

10kΩ

150Ω

1.2pF

VDD

CLK–

VIN–

05045-023

05045-024

PDWN

30kΩ

05045-026

Figure 26. Power-Down Input

DRVDD

05045-027

Figure 27. Data, DCO Outputs

1

05045-025

Figure 25. S1 Input

Rev. 0 | Page 16 of 28

AD9481

APPLICATIONS

The AD9481 uses a 1.5 bit per stage architecture. The analog

1.3kΩ

2kΩ

49.9Ω

499Ω

523Ω

499Ω

AD8138

499Ω

33Ω

Figure 29. Driving the ADC with the AD8138

SENSE = GND

20pF

AVDD

VIN+

AD9481

VIN–

AGND

05045-030

inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 8-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are CMOS-compatible.

ANALOG INPUTS

The analog input to the AD9481 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN− should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal. The analog inputs self-bias to approximately 1.9 V; this common-mode voltage can be externally overdriven by approximately ±300 mV if required.

0.1µF

The AD9481 can be easily configured for different full-scale ranges. See the Voltage Reference section for more information. Optimal performance is achieved with a 1 V p-p analog input.

A wideband transformer, such as the Mini-Circuits ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at the secondary side helps reduce any wideband noise getting aliased by the ADC.

(R, C OPTIONAL)

33Ω

49.9Ω

0.1µF

10pF

33Ω

Figure 28. Driving the ADC with an RF Transformer

AVDD

VIN+

AD9481

VIN–

AGND

05045-029

For dc-coupled applications, the AD8138/AD8139 or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 29 shows an example with the AD8138. The AD9481 PCB has an optional AD8351 on board, as shown in Figure 39 and Figure 40. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz. The AD9481’s linearity and SFDR start to degrade at higher analog frequencies (see the Typical Performance Characteristics section). For higher frequency applications, the AD9480 with LVDS outputs and superior AC performance should be considered.

VIN+

2.0V500mV 2.0V

VIN–

DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s

Figure 30. Analog Input Full Scale

VOLTAGE REFERENCE

A stable and accurate 1.0 V reference is built into the AD9481. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 32 shows the typical reference variation with temperature. Table 8 summarizes the available reference configurations.

VIN+ VIN–

ADC

CORE

VREF

+

0.1µF10µF 7kΩ

SELECT

LOGIC

SENSE

05045-031

Rev. 0 | Page 17 of 28

7kΩ

0.5V

Figure 31. Internal Reference Equivalent Circuit

05045-032

AD9481

Fixed Reference

The internal reference can be configured for a differential span of 1 V p-p (see Figure 34). It is recommended to place a 0.1 µF capacitor as close as possible to the VREF pin; a 10 µF capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9481 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 depicts how the internal reference voltage is affected by loading.

1.0085

1.0080

1.0075

1.0070

1.0065

1.0060

VREF (V)

1.0055

1.0050

1.0045

1.0040

1.0035 –40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 32. Typical Reference Variation with Temperature

05045-033

VREF

0.1µF10µF

SENSE

05045-034

Figure 33. Internal Fixed Reference (1 V p-p)

0

–0.1

–0.2

–0.3

% CHANGE IN VREF VOLTAGE

–0.4

–0.5

0 0.5 1.51.0 2.0 2.5 3.0

IREF (mA)

05045-035

Figure 34. Internal VREF vs. Load Current

Table 8. Reference Configurations

SENSE Voltage Resulting VREF Reference Differential Span

AVDD N/A (external reference input) External 1 × external reference voltage

0.5 V (Self-Biased) 0.5 × (1 + R1/R2) V Programmable 1 × VREF (0.75 V p-p to 1.5 V p-p) AGND to 0.2 V 1.0 V Internal fixed 1 V p-p

Rev. 0 | Page 18 of 28

AD9481

External Reference

An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9481 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full-scale voltage. VREF can be externally set to voltages from 0.75 V to 1.5 V; optimum performance is typically obtained at VREF = 1 V. (See the Typical Performance Characteristics section.)

MAY REQUIRE

EXTERNAL

REFERENCE OR

DAC INPUT

RC FILTER

VREF

AVDD

SENSE

Figure 35. External Reference

05045--036

Programmable Reference

The programmable reference can be used to set a differential input span anywhere between 0.75 V p-p and 1.5 V p-p by using an external resistor divider. The SENSE pin self-biases to 0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2 equal to 3.5 kΩ).

VREF

0.1µF

10µF

Figure 36. Programmable Reference

R1

SENSE

R2

05045-037

CLOCKING THE AD9481

Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9481, and the user is advised to give commensurate thought to the clock source.

The AD9481 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 100 MSPS and 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 70 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can

change dynamically, requiring a wait time of 5 µs after a dynamic clock frequency increase before valid data is available. The clock duty cycle stabilizer can be disabled at Pin 28 (S1).

The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs (ac coupling is optional). If the clock buffer is greater than two inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination shown in Figure 37.

0.1µF

PECL GATE

0.1µF

510kΩ510kΩ

Figure 37. Clocking the AD9481

AD9481

CLK+

CLK–

05045-028

DS INPUTS

The data sync inputs (DS+, DS−) can be used in applications which require that a given sample appear at a specific output port (A or B) relative to a given external timing signal.

The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs).

The DS inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. When DS+ is held high (DS− low), the ADC data outputs and DCO outputs do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints t (On initial synchronization, t within the required setup time (t edge N, the analog value at that point in time is digitized and available at Port A, eight cycles later in interleaved mode. The next sample, N + 1, is sampled by the next rising clock edge and available at Port B, eight cycles after that clock edge.

Driving each ADC’s DS inputs by the same sync signal accomplishes synchronization between multiple ADCs. In applications which require synchronization, one-shot synchronization is recommended. An easy way to accomplish synchronization is by a one-time sync at power-on reset.

SDS

and t

, relative to a clock rising edge.

HDS

is not relevant.) If DS+ falls

HDS

) before a given clock rising

SDS

Rev. 0 | Page 19 of 28

AD9481

Table 9. S1 Voltage Levels

Duty Cycle

S1 Voltage Data Format

(0.9 × AVDD) → AVDD (2/3 × AVDD) ± (0.1 × AVDD) Offset binary Enabled (1/3 × AVDD) ± (0.1 × AVDD) Twos complement Enabled AGND → (0.1 × AVDD)

Offset binary Disabled

Twos complement Disabled

DIGITAL OUTPUTS

The CMOS digital outputs are TTL-/CMOS-compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (< 2 inch, for a total C CMOS mode, it is also recommended to place low value series damping resistors on the data lines close to the ADC to reduce switching transient effects on performance.

Table 10. Output Coding (FS = 1 V)

Code (VIN+) − (VIN−) Offset Binary Twos Complement 255 > +0.512 V 1111 1111 0111 1111 255 +0.512 V 1111 1111 0111 1111 254 +0.508 V 1111 1110 0111 1110

• • • •

• • • • 129 +0.004 V 1000 0001 0000 0001 128 +0.0 V 1000 0000 0000 0000 127 −0.004 V 0111 1111 1111 1111

• • • •

• • • • 2 −0.504 V 0000 0010 1000 0010 1 −0.508 V 0000 0001 1000 0001 0 −0.512 V 0000 0000 1000 0000 0 < −0.512 V 0000 0000 1000 0000

< 5 pF). When operating in

LOAD

Stabilizer

INTERLEAVING TWO AD9481s

Instrumentation applications may prefer to interleave (or pingpong) two AD9481s to achieve twice the sample rate, or 500 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is extremely important as well and requires very low skew between clock signals driving the ADCs (< 2 ps clock skew for a 100 MHz analog input frequency).

DATA CLOCK OUT

A data clock is available at DCO+ and DCO−. These clocks can facilitate latching off-chip, providing a low skew clocking solution. The on-chip delay of the DCO clocks tracks with the on-chip delay of the data bits, (under similar loading) such that the variation between t

PD

and t

is minimized. It is

CPD

recommended to keep the trace lengths on the data and DCO pins matched and 2 inches maximum. A series damping resistor at the clock outputs is also recommended. The DCO outputs can be disabled and placed in a high impedance state by tying S3 to ground (tie to AVDD for DCO active). Switching both into and out of high impedance is accomplished in 4 ns from S3 switching.

POWER-DOWN INPUT

The ADC can be placed into a low power state by setting the PDWN pin to AVDD. Time to go into (or come out of ) power down equals 30 ns typically from PDWN switching.

Rev. 0 | Page 20 of 28

AD9481

AD9481 EVALUATION BOARD

The AD9481 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a

3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at an 80-pin output connector, P3, P23. (Note that P3, P23 are represented schematically as two 40-pin connectors, and this connector is implemented as one 80-pin connector on the PCB.) The board has several different modes of operation and is shipped in the following configuration:

ANALOG INPUTS

The evaluation board accepts a 700 mV p-p analog input signal centered at ground at SMB Connector J3. This signal is terminated to ground through 50 Ω by R22. The input can be alternatively terminated at the T1 transformer secondary by R21 and R28. T1 is a wideband RF transformer that provides the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. An optional transformer, T4, can be placed if desired (remove T1, as shown in Figure 39 and Figure 40).

• Offset binary

• Internal voltage reference

POWER CONNECTOR

Power is supplied to the board via two detachable 4-pin power strips.

Table 11. Power Connector

Terminal Comments

VDL (3.3 V)

AVDD1 3.3 V Analog supply for ADC ~ 140 mA DRVDD1 3.3 V Output supply for ADC ~ 30 mA VCTRL1 3.3 V Supply for support clock circuitry ~ 60 mA Op amp, ext. ref

1

AVDD, DRVDD, VDL, and VCTRL are the minimum required power

connections.

Output supply for external latches and data ready clock buffer ~ 30 mA

Optional supply for op amp and ADR510 reference

The analog signal can be low-pass filtered by R21, C8 and R28, C9 at the ADC input.

GAIN

Full scale is set by the sense jumper. This jumper applies a bias to the SENSE pin to vary the full-scale range; the default position is SENSE = ground, setting the full scale to 1 V p-p.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional AD8351 op amp that can serve as a convenient solution for dccoupled applications. To use the AD8351 op amp, remove R29, R31, and C3. Populate R12, R17, and R36 with 25 Ω resistors, and populate C1, C21, C23, C31, C39, and C30 with 0.1 µF capacitors. Populate R54, R10, and R11 with 10 Ω resistors, and R34 and R32 with 1 kΩ resistors. Populate R15 with a 1.2 kΩ resistor and R14 with a 100 Ω resistor. Populate R37 with a 10 kΩ resistor.

CLOCK

The clock input is terminated to ground through 50 Ω at SMA Connector J1. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for best performance. J1 input should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL (default) or AVDD by jumper placement at the device.

OPTIONAL CLOCK BUFFER

The PCB has been designed to accommodate the SNLVDS1 line driver. The SNLVDS1 is used as a high speed LVDS-level optional encode clock. To use this clock, please remove C2, C5, and C6. Place 0.1 µF capacitors on C34, C35, and C26. Place a 10 Ω resistor on R48, and place a 100 Ω resistor on R6. Place a 0 Ω resistor on both R49 and R53. For best results using the line driver, J1 input should be > 2.5 V p-p.

DS

The DS inputs are available on the PCB at J2 and J4. If driving DS+ externally, place a 0 Ω resistor at C48 and remove R53.

Rev. 0 | Page 21 of 28

AD9481

OPTIONAL XTAL

The PCB has been designed to accommodate an optional crystal oscillator that can serve as a convenient clock source. The footprint can accept both through-hole and surface-mount devices, including Vectron XO-400 and Vectron VCC6 family oscillators.

VCC

OUT–

VCC

Figure 38. XTAL Footprint

OUT+

GND

05045-038

To use either crystal, populate C38 and C40 with 0.1 µF capacitors. Populate R48 and R49 with 0 Ω resistors. Place R50, R51, R59, and R60 with 1 kΩ resistors. Remove C6 and C5. If the Vectron VCC6 family crystal is being used, populate R57 with a 10 Ω resistor. If using the XO-400 crystal, place jumper E21 or E22 to E23.

VOLTAGE REFERENCE

The AD9481 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when sense is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper on E5 to E3, and by placing a 0 Ω resistor on R55. When using an external programmable reference, (R20, R30) remove the sense jumper.

DATA OUTPUTS

The ADC outputs are buffered on the PCB by LVT574 latches on the data outputs. The latch outputs have series terminating resistors at the output pins to minimize reflections.

Rev. 0 | Page 22 of 28

AD9481

EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 12.

No. Quantity Reference Designator Device Package Value

1 24

2 1 C13 Capacitor Tantalum (3528) 10 µF 3 5 C32 to C36 Capacitors Tantalum (6032) 10 µF 4 4 J1 to J4 SMA SMA Degrees 5 3 P1, P12 to P13 4-pin power connectors Post Z5.531.3425.0 6 3 P1, P12 to P13 4-pin power connectors Detachable connector 25.602.5453.0 7 2 P3, P23 80-pin connectors Connector TSW-140-08-L-D-RA 8 7 R1, R5, R19, R22, R27, R35, R53 Resistors 0603 50 Ω 9 8 R2 to R4, R6 to R9, R18, R14 Resistors 0603 100 Ω 10 7 R13, R42 to R45, R32, R34 Resistors 0603 1 kΩ 11 2 R16, R52 Resistors 0603 130 Ω 12 2 R23, R24 Resistors 0603 510 Ω 13 2 R25, R26 Resistors 0603 82 Ω 14 2 R29, R31 Resistors 0603 00 Ω 15 2 R33, R37 Resistors 0603 10 kΩ 16 1 R46 Resistor 0603 2 kΩ 17 3 R12, R17, R36 Resistors 0603 25 Ω 18 1 R15 Resistor 0603 1.2 kΩ 19 3 R54, R10 to R11 Resistors 0603 10 Ω 20 2 RP1 to RP2 Resistor Pack 100 Ω Res. Array 742C163100JTR 21 4 U3, U5 to U6, U8 Resistor Pack 100 Ω 100 Ω Res. Array EXB-38V101JV 22 2 U4, U7 74LVT574 SO20 74LVT574WM 23 1 T1 Transformer CD542 ADT1-1WT 24 1 U1 AD8351 MSOP-10 Op Amp 25 1 U2 74VCX86 SO-14 XOR 26 1 U10 27 1 U91 VCC6PECL6 VCC6-QAB-250M000 Vectron Crystal 28 1 U12 AD9481 TQFP-44 ADC 29 1 U11 MC100-LVEL16D S08NB Clock Buffer 30 1 T21 ETC1-1-13 1-1 TX M/A-COM/ETC 1-1-13 31 11 C1, C7 to C9, C16, C20, C30, C31, C38 to C40 Capacitors 0402 X1 32 18

33 16 E98 to E102, E73 to E84 Jumpers

C1 to C6, C10 to C12, C14 to C15, C17 to C19, C22 to C29, C31, C48 to C49

1

R20 to R21, R28, R30, R38 to R41, R48 to R51, R55 to R60

1

Not placed.

Capacitors 0402 0.1 µF

ADR510 SOT-23 Voltage Regulator

1

Resistors 0603 X

Rev. 0 | Page 23 of 28

AD9481

PCB SCHEMATICS

GND

DR+

39

P37P38

P39

OUTPUT

P40

CONNECTOR

40

GND

DB7X

15

16

RP1

100Ω

2345678

1

VDLGND

19181716151413

20

Q0Q1Q2Q3Q4Q5Q6

VCC

U4

74LVT574

D0D1D2D3D4D5D6D7GND

OUT_EN

2345678

1

876

100Ω

RPAK_4

1

P1

2

P2

3

P3

GND

4

P4

VAMP

P1

1

P1

GND

2

P2

VDL

3

P3

GND

4

P4

DRVDD

P12

1

GND

P1

2

AVDD

P2

3

P3

GND

P13

4

P4

VCTRL

GND

P35P36

DB6X

234

DB7

E25

DB7X

P33P34

DB6

DB5X

DB5

GND

5

DB6X

DB5X

P29

P31P32

P30

DB4X

DB4

DB7

DB4X

DB3X

DB2X

DB1X

P21P22

P23P24

P25P26

P27P28

DB1X

DB2X

DB3X

10

121314

11

876

5

234

1

U8

DB2

DB3

DB1

DB6

DB5

DB4

GND S1 PWDN AVDD AVDD GND

33 32 31 30 29 28 27 26 25 24 23

R20XXR30

E1

E2

E13 E14

E15 E16

GND

AVDD

U10

ADR510

R33

DB0X

P19

P20

DB0X

9

12

Q7

9

DB0

10kΩ

E3 E5

XX

V+

1

VAMP

P17P18

11

10

S1

3

P13P14

P15P16

VDL

CLOCK

GND

RPAK_4

U3

D4B D5B D6B D7B

DRGND

PWDN AVDD AVDD AGND

SENSE

TRIM/NC

V–

2

P11P12

GND

P9

P10

R40

DB3

D3B

VREF

GND

P5P6

P7P8

8

101214161820222426283032343638

X

CLKLAT+

C20

E19

DB2

DB1

D1B

D2B

AVDD

AGND

GND

AVDD

C12

0.1µF

+

C13

10µF

X

R55

C14

0.1µF

R1

GND

135791113151719212325272931333537

P23

P1

P3

P2

P4

246

P39

OUTPUT

P40

CONNECTOR

GND

NOTE: TWO 40 PIN OUTPUT CONNECTOR

GND

IMPLEMENTED AS ONE 80 PIN CONNECTOR

16

RP2

100Ω

1

R41

X

VDLGND

19181716151413

20

VCC

U7

74LVT574

OUT_EN

2345678

1

COUT–

COUT+

C16

X

R2

100Ω

X

GND

R3

100Ω

E18

GND

DB0

DA0

DA1

16171819202122

15

DCO–

DCO+

DRGNDAVDD

AD9481

VIN+

AGND

GND

AVDD

E27

C49

0.1µF

D0A

S3

D1A

DS–

4443424140393837363534

121314

DA2

D2A

DS+

AMPOUT

E29

E28

AMPOUT

E26

R53

C48

0.1µF

R35

C9

C8

50Ω

D3A D4A D5A D6A D7A DRGND DRVDD AGND AVDD CLK–

1 2 3 4 5 6 7 8 9 10 11

CLK+

GND

X

GND

D0B

AGND

GND

50Ω

DRVDD

U12

VIN–

GND

J4

DS–

GND

J2

DS+

Figure 39. PCB Schematic (1 of 2)

DR–

GND

DA7X

DA6X

DA5X

DA4X

DA3X

DA2X

DA1X

DA0X

39

P17P18

P19

P21P22

P23P24

P25P26

P27P28

P29

P31P32

P33P34

P35P36

P37P38

P20

P30

40

DA7X

DA6X

DA5X

DA4X

DA3X

DA2X

DA1X

DA0X

9

10

121314

15

2345678

Q0Q1Q2Q3Q4Q5Q6

11

12

Q7

CLOCK

D0D1D2D3D4D5D6D7GND

9

10

GND

876

5

876

5

RPAK_4

234

1

DA0

DA1

DA3

DA4

R31

SECPRI

E30

DA2

DA3

DA5

DA6

GND

0Ω

R28XR21

T1–

CM

432561

CM

DA7

DRVDD

AVDD

C10

U6

0.1µF

T1-1T

R22

1

CM

C3

DA4

T1

50Ω

234

TIN1

0.1µF

DA5

DA6

GND

DA7

R29

RPAK_4

0Ω

X

T1+

GND

J3

ANALOG

INPUT

GND

135791113151719212325272931333537

P1

P3

P5P6

P7P8

P9

P11P12

P13P14

P15P16

P10

P2

P4

246

8

101214161820222426283032343638

R39

X

R38

X

VDL

CLKLAT–

U5

E6

C6

0.1µF

OP AMP CONFIGURATION

REMOVE C3

REMOVE R29 AND R31

VCTRL

R16

130Ω

VCTRL

GND

C11

0.1µF

8

1

E10

AMPIN

E9

E11

AVDD

VCTRL

J1

CLK+

Q

7

VCC R

2

P3

GND

E8

R52

R25

6

Q

100LVEL16

CLK

3

C2

CLK

T1+

162534

T2 ETC1-1-13

CLK–

TIN1

OPTIONAL TRANSFORMER

C5

0.1µF

Q–

R26

82Ω

130Ω

GND

82Ω

GND

U11

Q

5

VEE

4

VBB

CLKN

R24

510Ω

R23

510Ω

0.1µF R27

50Ω

GND

05045-040

E72VCTRL

E7VDL

E12DRVDD

E4AVDD

E70AVDD

E71DRVDD

CM

T1–

PRI SEC

CM

GND

X = NOT NORMALLY POPULATED

XX = NOT POPULATED, USER SELECTED

Q–

Q

P15P14

P17P16

CLK

USED IF BYPASSING EL16

PADS FOR SHORTING EL16,

CLKN

GND

C4

0.1µF

Rev. 0 | Page 24 of 28

AD9481

05045-041

CLK–

CLK+

X

5

4

VC

OUTPUTB

E/DNCGND

213

X

VCTRL

R49

OUTPUT

X

R57

X

R51

XX

GND

XX

R50

VCTRL

GND

X = NOT NORMALLY POPULATED

XX = NOT POPULATED, USER SELECTED

R48

R60

X

GNDVCTRL

X

R59

C29

0.1µF

C28

0.1µF

C27

0.1µF

C26

0.1µF

+

C32

10µF

VDL

VAMPF

C17

0.1µF

C24

0.1µF

C18

0.1µF

C25

0.1µF

+

C33

10µF

AVDD

GND

DRVDD

GND

C1

X

VDL

OPTIONAL XTALS

GND

X

R58

C15

0.1µF

+

C35

10µF

GND

VCTRL

C22

0.1µF

C19

0.1µF

+

C34

10µF

1

8

OUTVCC

VEE –OUT

U13

XO-400

7

14

C40

X

E22

E24

E23

AVDD

VCTRL

6

VCC 6 PECL6

GND

C38

GND

X

R54

+

C36

10µF

GND

VAMP

GND

X

C31

R34

R32

VAMPF

R44

DR–

CLKAT–

DR+

CLKLAT+

VDL

GND

R4

3A

9

E52

GND

100Ω

8 3Y

3B

101213

COUT–

R6

100Ω

E45

E50

VDL

E46

R5

50Ω

4A

COUT–

R7

E49

GND

PWR

11

14

4Y

4B

100Ω

E48

E47

VDL

GND

R18

R19

50Ω

100Ω

3

6

1Y

2Y

U2

74VCX86

1A

1B

2A

2B

1

245

COUT+

R9

R8

100Ω

E54

E51

E56

E55

E53

VDL

GND

E21E20

GND

7

VCTRL

E35 E36

VCTRL

1kΩ

S3

E90

E89

E88

GND

AVDD

VCTRL PWDN

GND

X

R46

R45

S1

E32 E39

E33 E38

E34 E37

R42

R43

R13

1kΩ

AMPOUT

X

C39

GNDVAMPF

X

R17

X

VAMPF

VPOS

VOCM

10

9

U1

AD8351

1

2

RGP1

PWUP

X

R37

X

C21

OPHI

8

3 INHI

AMPIN

C7

R56

R10

X

R36

OPLO 7

4

INLO

X

AMPOUT

R11

X

C30

GND

COMM 6

5

RPG2

X

C23

X

R12

R15

R14

X

GND

Figure 40. PCB Schematic (2 of 2)

Rev. 0 | Page 25 of 28

AD9481

PCB LAYERS

August 3, 2004

Figure 41. PCB Top-Side Silkscreen

05045-042

05045-044

Figure 43. PCB Ground Layer

Figure 42. PCB Top-Side Copper Routing

05045-043

Rev. 0 | Page 26 of 28

Figure 44. PCB Split Power Plane

05045-045

AD9481

05045-046

Figure 45. PCB Bottom-Side Copper Routing

Figure 46. PCB Bottom-Side Silkscreen

05045-047

Rev. 0 | Page 27 of 28

AD9481

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20 MAX

12.00 SQ

44

1

PIN 1

34

33

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0° MIN

0.20

VIEW A

0.09

7°

3.5° 0°

0.08 MAX COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026ACB

11

12

TOP VIEW

(PINS DOWN)

0.80

BSC

0.45

0.37

0.30

10.00 SQ

23

22

Figure 47. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44)—Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9481BSUZ-250 AD9481-PCB

1

Z = Pb-free part.

2

Evaluation board shipped with AD9481BSUZ-250 installed.

1

2

–40°C to +85°C 44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44 Evaluation Board

D05045–0–10/04(0)

Rev. 0 | Page 28 of 28

Analog Devices AD9481 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

AC SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

APPLICATIONS

ANALOG INPUTS

VOLTAGE REFERENCE

Fixed Reference

External Reference

Programmable Reference

CLOCKING THE AD9481

DS INPUTS

DIGITAL OUTPUTS

INTERLEAVING TWO AD9481s

DATA CLOCK OUT

POWER-DOWN INPUT

AD9481 EVALUATION BOARD

ANALOG INPUTS

POWER CONNECTOR

GAIN

OPTIONAL OPERATIONAL AMPLIFIER

CLOCK

OPTIONAL CLOCK BUFFER

OPTIONAL XTAL

VOLTAGE REFERENCE

DATA OUTPUTS

EVALUATION BOARD BILL OF MATERIALS (BOM)

PCB SCHEMATICS

PCB LAYERS

OUTLINE DIMENSIONS

ORDERING GUIDE