Analog Devices AD9481 Service Manual

8-Bit, 250 MSPS

FEATURES

DNL = ±0.35 LSB INL = ±0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 439 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs De-multiplexed CMOS outputs Power-down mode Clock duty cycle stabilizer

APPLICATIONS

Digital oscilloscopes Instrumentation and measurement Communications

Point-to-point radios Digital predistortion loops

GENERAL DESCRIPTION

The AD9481 is an 8-bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range.

To minimize system cost and power dissipation, the AD9481 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications.

The digital outputs are TTL/CMOS-compatible with an option of twos complement or binary output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture.

3.3 V A/D Converter AD9481

FUNCTIONAL BLOCK DIAGRAM

VREF SENSE

REFERENCE

VIN+ VIN–

DS+ DS–

CLK+ CLK–

T AND H

CLOCK

MGMT

PDWN S1

The AD9481 is available in a Pb-free, 44-lead, surface-mount package (TQFP-44) specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Superior linearity. A DNL of ±0.35 makes the AD9481

suitable for many instrumentation and measurement applications

2. Power-down mode. A power-down function may be exercised

to bring total consumption down to 15 mW.

3. De-multiplexed CMOS outputs allow for easy interfacing

with low cost FPGAs and standard logic.

AGND DRGND DRVDD AVDD

AD9481

PORT

A

8-BIT

8

ADC

PIPELINE

CORE

Figure 1.

LOGIC

PORTB8

8

D7A TO D0A

D7B TO D0B

DCO+ DCO–

05045-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9481

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 1.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits ACCURACY

No Missing Codes Full VI Guaranteed Offset Error 25°C I −40 40 mV Gain Error

1

Differential Nonlinearity (DNL) Full VI −0.85 ±0.35 0.85 LSB Integral Nonlinearity (INL) Full VI −0.9 ±0.26 0.9 LSB

TEMPERATURE DRIFT

Offset Error Full V 30 µV/°C Gain Error Full V 0.03 % FS/°C Reference Full V ±0.025 mV/°C

REFERENCE

Internal Reference Voltage Full VI 0.97 1.0 1.03 V Output Current I

Input Current

VREF

I

Input Current2 25°C I 10 µA

SENSE

2

3

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range Common-Mode Voltage Full VI 1.6 1.9 2.1 V Input Resistance Full VI 8.4 10 11.2 kΩ Input Capacitance 25°C V 4 pF Analog Bandwidth, Full Power 25°C V 750 MHz

POWER SUPPLY

AVDD Full IV 3.0 3.3 3.6 V DRVDD Full IV 3.0 3.3 3.6 V

Supply Currents

5

IAVDD

IDRVDD5 Full VI 39 42.5 mA Power Dissipation5 25°C V 439 mW Power-Down Dissipation 25°C V 15 37 mW Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and 1 V p-p input range).

2

Internal reference mode; SENSE = AGND.

3

External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD.

4

In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.

5

Supply current measured with rated encode and a 20 MHz analog input. Power dissipation measured with dc input, see the T section for power vs. clock

rate.

= −40°C, T

MIN

4

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

25°C I −6.0 6.0 % FS

25°C IV 1.5 mA 25°C I 100 µA

Full V 1 V p-p

Full VI 133 145 mA

erminology

Rev. 0 | Page 3 of 28

AD9481

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 2.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

CLOCK AND DS INPUTS (CLK+, CLK−, DS+, DS−)

Differential Input Full IV 200 mV p-p Common-Mode Voltage

1

Input Resistance Full VI 4.2 5.5 6.0 kΩ Input Capacitance 25°C V 4 pF

LOGIC INPUTS (PDWN, S1)

Logic 1 Voltage Full IV 2.0 V Logic 0 Voltage Full IV 0.8 V Logic 1 Input Current Full VI ±160 µA Logic 0 input Current Full VI 10 µA Input Resistance 25°C V 30 kΩ Input Capacitance 25°C V 4 pF

DIGITAL OUTPUTS

Logic 1 Voltage

2

Logic 0 Voltage Full VI 0.05 V Output Coding Full IV Twos complement or binary

1

The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.

2

Capacitive loading only.

= −40°C, T

MIN

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Full VI 1.38 1.5 1.68 V

Full VI DRVDD − 0.05 mV

Rev. 0 | Page 4 of 28

AD9481

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; T clock inputs, unless otherwise noted.

Table 3.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 19.7 MHz 25°C V 46 dB fIN = 70.1 MHz 25°C I 44.5 45.7 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 19.7 MHz 25°C V 45.9 dB fIN = 70.1 MHz 25°C I 44.4 45.7 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 19.7 MHz 25°C V 7.5 Bits fIN = 70.1 MHz 25°C I 7.2 7.5 Bits

WORST SECOND OR THIRD HARMONIC DISTORTION

fIN = 19.7 MHz 25°C V −64.8 dBc fIN = 70.1 MHz 25°C I −64.8 −54 dBc

WORST OTHER

fIN = 19.7 MHz 25°C V −68 dBc fIN = 70.1 MHz 25°C I −65.8 −56 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 19.7 MHz 25°C V −64.8 dBc fIN = 70.1 MHz 25°C I −64.8 −54 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

= 69.3 MHz, f

IN1

= 70.3 MHz 25°C V −64.9 dBc

IN2

1

DC and Nyquist bin energy ignored.

= −40°C, T

MIN

1

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Rev. 0 | Page 5 of 28

AD9481

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.

Table 4.

AD9481-250 Parameter Temp Test Level Min Typ Max Unit

CLOCK

Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full IV 20 MSPS Clock Pulse-Width High (tEH) Full IV 1.2 2 ns Clock Pulse-Width Low (tEL) Full IV 1.2 2 ns DS Input Setup Time (t DS Input Hold Time (t

OUTPUT PARAMETERS

Valid Time (tV)

2

Propagation Delay (tPD) Full VI 4 5.4 ns Rise Time (tR) 10% to 90% Full V 670 ps Fall Time (tF) 10% to 90% Full V 360 ps DCO Propagation Delay (t Data-to-DCO Skew (tPD − t A Port Data to DCO− Rising (t B Port Data to DCO+ Rising (t Pipeline Latency (A, B) Full IV 8 Cycles

APERTURE

Aperture Delay (tA) 25°C V 1.5 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms

OUT-OF-RANGE RECOVERY TIME 25°C V 1 Cycle

1

C

equals 5 pF maximum for all output switching specifications.

LOAD

2

Valid time is approximately equal to minimum tPD.

3

T

equals clock rising edge to DCO (+ or −) rising edge delay.

CPD

4

Data changing to (DCO+ or DCO−) rising edge delay.

5

T

, T

are both clock rate dependent delays equal to T

SKA

SKB

) Full IV 0.5 ns

SDS

) Full IV 0.5 ns

HDS

1

Full VI 2.5 ns

3

)

CPD

4

)

CPD

5

)

SKA

) Full IV 4 ns

SKB

− (Data to DCO skew).

CYCLE

Full VI 2.5 3.9 5.3 ns Full VI −0.5 +0.5 ns Full IV 4 ns

Rev. 0 | Page 6 of 28

AD9481

A

TIMING DIAGRAM

N–1

VIN

CLK+ CLK–

DS+ DS–

INTERLEAVED DATA OUT

PORT A

D7A TO D0

D7B TO D0B

STATIC INVALID N

PORT B

STATIC INVALID INVALID N+1

DCO+ DCO–

t

EH

t

HDS

STATIC

t

A

N

N+1

8 CYCLES

t

EL

1/f

S

t

SDS

N+7

N+8

t

PD

CPD

t

SKA

N+9

t

SKB

N+10

t

V

05045-002

Figure 2. Timing Diagram

Rev. 0 | Page 7 of 28

AD9481

ABSOLUTE MAXIMUM RATINGS

Thermal impedance (θJA) = 46.4°C/W (4-layer PCB).

Table 5.

Min.

Parameter

ELECTRICAL

AVDD (With respect to AGND) −0.5 V +4.0 V DRVDD

(With respect to DRGND) AGND (With respect to DRGND) −0.5 V +0.5 V Digital I/0

(With respect to DRGND) Analog Inputs

(With respect to AGND)

ENVIRONMENTAL

Operating Temperature −40°C +85°C Junction Temperature 150°C Storage Temperature 150°C

Rating

−0.5 V +4.0 V

−0.5 V DRVDD + 0.5 V

−0.5 V AVDD + 0.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Max. Rating

EXPLANATION OF TEST LEVELS

Table 6.

Level Description

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 28

AD9481

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DS+43DS–42S341AVDD40AGND39VIN+38VIN–37AGND36AVDD35AGND34VREF

44

CLK+

CLK– AVDD AGND

DRVDD DRGND

D7A (MSB)

D6A D5A D4A D3A

1

PIN 1

2 3 4 5 6 7 8 9

10

11

12

(Not to Scale)

14

15

AD9481

TOP VIEW

16

17

18

19

20

33

SENSE

32

AGND

31

AVDD

30

AVDD

29

PDWN

28

S1

27

DRGND

26

D7B (MSB)

25

D6B

24

D5B

23

D4B

Table 7. Pin Function Descriptions

Pin No. Name Description

1 CLK+ Input Clock—True 2 CLK− Input Clock—Complement 3 AVDD 3.3 V Analog Supply 4 AGND Analog Ground 5 DRVDD 3.3 V Digital Output Supply 6 DRGND Digital Ground 7 D7A Data Output Bit 7—Channel A (MSB) 8 D6A Data Output Bit 6—Channel A 9 D5A Data Output Bit 5—Channel A 10 D4A Data Output Bit 4—Channel A 11 D3A Data Output Bit 3—Channel A 12 D2A Data Output Bit 2—Channel A 13 D1A Data Output Bit 1—Channel A 14 D0A Data Output Bit 0—Channel A (LSB) 15 DRGND Digital Ground 16 DCO− Data Clock Output—Complement 17 DCO+ Data Clock Output—True 18 DRVDD 3.3 V Digital Output Supply 19 D0B Data Output Bit 0—Channel B (LSB) 20 D1B Data Output Bit 1—Channel B 21 D2B Data Output Bit 2—Channel B 22 D3B Data Output Bit 3—Channel B 23 D4B Data Output Bit 4—Channel B 24 D5B Data Output Bit 5—Channel B

D2A13D1A

D0A (LSB)

DCO–

DRGND

DCO+

DRVDD

Figure 3. Pin Configuration

Pin No. Name Description

25 D6B Data Output Bit 6—Channel B 26 D7B Data Output Bit 7—Channel B (MSB) 27 DRGND Digital Ground 28 S1

29 PDWN Power-Down Selection 30 AVDD 3.3 V Analog Supply 31 AVDD 3.3 V Analog Supply 32 AGND Analog Ground 33 SENSE Reference Mode Selection 34 VREF Voltage Reference Input/Output 35 AGND Analog Ground 36 AVDD 3.3 V Analog Supply 37 AGND Analog Ground 38 VIN− Analog Input—Complement 39 VIN+ Analog Input—True 40 AGND Analog Ground 41 AVDD 3.3 V Analog Supply 42 S3

43 DS−

44 DS+ Data Sync True (If Unused, Tie to DGND)

D0B (LSB)

D1B21D2B22D3B

05045-003

Data Format Select and Duty Cycle Stabilizer Select

DCO Enable Select (Tie to AVDD for DCO Active)

Data Sync Complement (If Unused, Tie to DRVDD)

Rev. 0 | Page 9 of 28

Analog Devices AD9481 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

AC SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS