ANALOG DEVICES AD9253 Service Manual

Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS

A

Serial LVDS 1.8 V Analog-to-Digital Converter

Data Sheet

FEATURES

1.8 V supply operation Low power: 110 mW per channel at 125 MSPS with scalable

power options SNR = 74 dB (to Nyquist) SFDR = 90 dBc (to Nyquist) DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced

signal option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Multichip sync and clock divider

Programmable output clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment

GENERAL DESCRIPTION

The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sampleand-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9253

FUNCTIONAL BLOCK DIAGRAM

VDD PDWN DRVDD

SDIO/OLM

ADC

14

DIGITAL

SERIALIZER

14

DIGITAL

SERIALIZER

1V

AD9253

14

DIGITAL

SERIALIZER

14

DIGITAL

SERIALIZER

CLOCK

MANAGEMENT

CLK+

SYNC

SCLK/DTP

VIN+A

VIN–A

VIN+B

VIN–B

RBIAS

VREF

SENSE

AGND

VIN+C

VIN–C

VIN+D

VIN–D

VCM

PIPELINE

REF

SELECT

PIPELINE

SERIAL PORT

INTERFACE

CSB

Figure 1.

as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package.

2. Low power of 110 mW/channel at 125 MSPS with scalable

power options.

3. Pin compatible to the AD9633 12-bit quad ADC.

4. Ease of Use. A data clock output (DCO) operates at

frequencies of up to 500 MHz and supports double data rate (DDR) operation.

5. User Flexibility. The SPI control offers a wide range of

flexible features to meet specific system requirements.

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

SERIAL

LVD S

CLK–

D0+A D0–A

D1+A D1–A

D0+B D0–B

D1+B D1–B

FCO+ FCO– D0+C D0–C D1+C D1–C

D0+D D0–D

D1+D D1–D DCO+ DCO–

10065-001

AD9253 Data Sheet

REVISION HISTORY

10/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet AD9253

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 1.

AD9253-80 AD9253-105 AD9253-125

Parameter1 Temp

RESOLUTION 14 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed

Offset Error Full −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR

Offset Matching Full −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 % FSR

Gain Error Full −10 −5 0 −10 −5 0 −10 −5 0 % FSR

Gain Matching Full 1 1.6 1 1.6 1.1 1.6 % FSR

Differential Nonlinearity (DNL) Full −1

25°C ±0.8

Integral Nonlinearity (INL) Full −4.0

25°C ±1.5

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.0 1.02 0.98 1.0 1.02 0.98 1.0 1.02 V

Load Regulation at 1.0 mA (V

= 1 V) Full 2 2 2 mV

REF

Input Resistance Full 7.5 7.5 7.5 kΩ

INPUT-REFERRED NOISE

V

= 1.0 V 25°C 0.94 0.94 0.94 LSB rms

REF

ANALOG INPUTS

Differential Input Voltage (V

= 1 V) Full 2 2 2 V p-p

REF

Common-Mode Voltage Full 0.9 0.9 0.9 V

Differential Input Resistance 5.2 5.2 5.2 kΩ

Differential Input Capacitance Full 3.5 3.5 3.5 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

2

I

Full 131 144 158 172 183 200 mA

AVDD

I

(ANSI-644 Mode)2 Full 63 81 67 95 71 100 mA

DRVDD

I

(Reduced Range Mode)2 25°C 42

DRVDD

TOTAL POWER CONSUMPTION

DC Input Full 326

Sine Wave Input (Four Channels Including

Full 349 405 405 481 457 540 mW

Output Drivers ANSI-644 Mode)

Sine Wave Input (Four Channels Including

25°C 311 371 425 mW

Output Drivers Reduced Range Mode) Power-Down Full 2 2 2 mW Standby3 Full 178 209 236 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on all four channels.

3

Can be controlled via the SPI.

Min Typ Max Min Typ Max Min Typ Max Unit

+1.6 −0.8

+4.0 −4.0

±0.75 ±0.75 LSB

±2.0 ±2.0 LSB

48

375 423 mW

+1.5 −0.8

4.0 −4.0

53

+1.5 LSB

+4.0 LSB

mA

Rev. 0 | Page 3 of 40

AD9253 Data Sheet

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 2.

AD9253-80 AD9253-105 AD9253-125

Parameter1 Temp

Min Typ Max Min Typ Max Min Typ Max

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 75.4 75.1 75.3 dBFS fIN = 30.5 MHz 25°C 74.9 75.0 75.2 dBFS fIN = 70 MHz Full 72.2 74.7 72.2 74.4 73 74.2 dBFS fIN = 140 MHz 25°C 72.3 73.1 72.2 dBFS fIN = 200 MHz 25°C 70.7 71.2 70.7 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 75.3 75.0 75.2 dBFS fIN = 30.5 MHz 25°C 74.8 74.9 75.1 dBFS fIN = 70 MHz Full 70.8 74.6 69.8 74.2 71.6 74.1 dBFS fIN = 140 MHz 25°C 72.1 72.8 71.9 dBFS fIN = 200 MHz 25°C 70.5 70.8 70.4 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.2 12.1 12.2 Bits fIN = 30.5 MHz 25°C 12.1 12.1 12.1 Bits fIN = 70 MHz Full

11.9

12.0

12.0 Bits fIN = 140 MHz 25°C 11.6 11.8 11.6 Bits fIN = 200 MHz 25°C 11.5 11.5 11.4 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 98 98 98 dBc fIN = 30.5 MHz 25°C 93 92 92 dBc fIN = 70 MHz Full 77 94 75 89 77 90 dBc fIN = 140 MHz 25°C 85 85 85 dBc fIN = 200 MHz 25°C 84 82 83 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −98 −98 −98 dBc fIN = 30.5 MHz 25°C −93 −92 −92 dBc fIN = 70 MHz Full −94 −77 −89 −75 −90 −77 dBc fIN = 140 MHz 25°C −85 −85 −85 dBc fIN = 200 MHz 25°C −84 −82 −83 dBc

WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD)

fIN = 9.7 MHz 25°C −100 −99 −101 dBFS fIN = 30.5 MHz 25°C −99

−99 −100 dBFS fIN = 70 MHz Full −98 −77 −95 −77 −95 −84 dBFS fIN = 140 MHz 25°C −98 −98 −96 dBFS fIN = 200 MHz 25°C −95 −92 −92 dBFS

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND

AIN2 = −7.0 dBFS f

= 70.5 MHz, f

IN1

= 72.5 MHz 25°C 90 88 86 dBc

IN2

CROSSTALK2 Full −95 −95 −95 dB CROSSTALK (OVERRANGE CONDITION)3 25°C −89 −89 −89 dB POWER SUPPLY REJECTION RATIO (PSRR)

1, 4

AVDD 25°C 48 48 48 dB DRVDD 25°C 75 75 75 dB

ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is specified with 3 dB of the full-scale input range.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitudes of the spur voltage over the pin voltage, expressed in decibels.

Rev. 0 | Page 4 of 40

Unit

Data Sheet AD9253

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644

Logic Compliance LVDS Differential Output Voltage (VOD) Full 290 345 400 mV Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,

REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (VOD) Full 160 200 230 mV Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO/OLM pins sharing the same connection.

Rev. 0 | Page 5 of 40

AD9253 Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

1, 2

Temp Min Typ Max Unit

CLOCK3

Input Clock Rate Full 10 1000 MHz Conversion Rate Full 10 80/105/125 MSPS Clock Pulse Width High (tEH) Full 6.25/4.76/4.00 ns Clock Pulse Width Low (tEL) Full 6.25/4.76/4.00 ns

OUTPUT PARAMETERS3

Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (t DCO Propagation Delay (t DCO to Data Delay (t

DATA

DCO to FCO Delay (t

) Full 1.5 2.3 3.1 ns

FCO

)4 Full t

CPD

)4 Full (t

FRAME

/16) − 300 (t

SAMPLE

/16) − 300 (t

SAMPLE

+ (t

FCO

SAMPLE

/16) (t

SAMPLE

/16) (t

SAMPLE

/16) ns

/16) + 300 ps

SAMPLE

/16) + 300 ps

SAMPLE

Lane Delay (tLD) 90 ps Data to Data Skew (t

DATA-MAX

− t

) Full ±50 ±200 ps

DATA-MIN

Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16

Clock cycles

APERTURE

Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

t

/16 is based on the number of bits in two LVDS data lanes. t

SAMPLE

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

SAMPLE

= 1/fS.

Clock cycles

TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

SSYNC

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING REQUIREMENTS See Figure 74

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min t

SCLK pulse width high 10 ns min

HIGH

t

SCLK pulse width low 10 ns min

LOW

t

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the

10 ns min

SCLK falling edge (not shown in Figure 74)

t

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative to the

10 ns min

SCLK rising edge (not shown in Figure 74)

Rev. 0 | Page 6 of 40

Unit

Data Sheet AD9253

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Ta b le 2 1 for SPI register settings.

N – 1

VIN±x

t

A

N

N + 1

DDR

SDR

BITWISE

MODE

BYTEWISE

MODE

CLK–

CLK+

DCO–

DCO+

DCO–

DCO+

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

t

EH

t

CPD

t

FCO

t

PD

D12

N – 17

MSB

N – 17

D05

N – 17

MSB

N – 17

t

EL

t

FRAME

D10

N – 17

D11

N – 17

D04

N – 17

D12

N – 17

D08

N – 17

D09

N – 17

D03

N – 17

D11

N – 17

D06

N – 17

D07

N – 17

D02

N – 17

D10

N – 17

t

DATA

D04

D02

N – 17

D05

D03

N – 17

D01

LSB

N – 17

N – 170N – 170N – 17

D09

D08

N – 17

LSB

N – 170N – 17

D01

N – 170N – 17

D07

D06

N – 17

D12

D10

D08

D06

D04

D02

N – 16

t

LD

MSB

D11

D09

D07

N – 16

D05

N – 16

MSB

N – 16

D04

N – 16

D12

N – 16

D03

N – 16

D11

N – 16

D02

N – 16

D10

N – 16

D05

N – 16

D01

N – 16

D09

N – 16

LSB

N – 16

N – 160N – 16

D03

D01

N – 16

N – 160N – 16

LSB

N – 160N – 160N – 16

D08

D07

N – 16

D06

N – 16

10065-003

Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

Rev. 0 | Page 7 of 40

AD9253 Data Sheet

VIN±x

CLK–

CLK+

DCO–

DDR

N – 1

t

A

t

EH

t

CPD

t

EL

N

N + 1

DCO+

DCO–

SDR

BITWI SE

MODE

DCO+

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

D10

N – 17

MSB

N – 17

t

FCO

t

PD

D08

N – 17

D09

N – 17

D06

N – 17

D07

N – 17

t

FRAME

N – 17

D04

D05

D02

N – 17

D03

N – 17

LSB

N – 17

D01

N – 17

D10

N – 16

MSB

N – 16

t

DATA

D08

N – 16

D09

N – 16

D06

N – 16

D07

N – 16

D04

D02

N – 16

D03

N – 16

LSB

N – 16

D01

N – 16

t

LD

D05

N – 16

FCO–

FCO+

BYTEWI SE

MODE

D0–A

D0+A

D1–A

D1+A

D05

N – 17

MSB

N – 17

D04

N – 17

D10

N – 17

D03

N – 17

D09

N – 17

D02

N – 17

D08

N – 17

D01

N – 17

D07

N – 17

LSB

N – 17

D06

N – 17

D05

N – 16

MSB

N – 16

D04

N – 16

D10

N – 16

D03

N – 16

D09

N – 16

D02

N – 16

D08

N – 16

D01

N – 16

D07

N – 16

LSB

N – 16

D06

N – 16

10065-004

Figure 3. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode

N – 1

VIN±x

t

A

N

N + 1

DDR

SDR

BITWISE

MODE

BYTEWISE

MODE

CLK–

CLK+

DCO–

DCO+

DCO–

DCO+

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

t

EH

t

CPD

t

FCO

t

PD

D12

N – 17

MSB

N – 17

D05

N – 17

MSB

N – 17

t

EL

t

FRAME

D10

N – 17

D11

N – 17

D04

N – 17

D12

N – 17

D08

N – 17

D09

N – 17

D03

N – 17

D11

N – 17

D06

N – 17

D07

N – 17

D02

N – 17

D10

N – 17

t

DATA

D04

D02

N – 17

D05

D03

N – 17

D01

LSB

N – 17

N – 170N – 170N – 17

D09

D08

N – 17

LSB

N – 170N – 17

D01

N – 170N – 17

D07

D06

N – 17

D12

D10

D08

D06

D04

D02

N – 16

t

LD

MSB

D11

D09

D07

N – 16

D05

N – 16

MSB

N – 16

D04

N – 16

D12

N – 16

D03

N – 16

D11

N – 16

D02

N – 16

D10

N – 16

D05

N – 16

D01

N – 16

D09

N – 16

LSB

N – 16

N – 160N – 16

D03

D01

N – 16

N – 160N – 16

LSB

N – 160N – 160N – 16

D08

D07

N – 16

D06

N – 16

10065-005

Figure 4. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode

Rev. 0 | Page 8 of 40

Data Sheet AD9253

VIN±x

CLK–

CLK+

DCO–

DDR

N – 1

t

A

t

EH

t

CPD

t

N

EL

N + 1

DCO+

DCO–

SDR

BITWI SE

MODE

DCO+

FCO–

FCO+

D0–A

D0+A

D1–A

D1+A

D10

N – 17

MSB

N – 17

t

FCO

t

D08

N – 17

D09

N – 17

t

FRAME

t

PD

D06

D04

D02

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

LSB

N – 17

D01

N – 17

D10

N – 16

MSB

N – 16

DATA

D08

N – 16

D09

N – 16

D06

N – 16

D07

N – 16

D04

D02

N – 16

D03

N – 16

LSB

N – 16

D01

N – 16

t

LD

D05

N – 16

FCO–

FCO+

MODE

D0–A

D0+A

D1–A

D1+A

D05

N – 17

MSB

N – 17

D04

N – 17

D10

N – 17

D03

N – 17

D09

N – 17

D02

N – 17

D08

N – 17

D01

N – 17

D07

N – 17

LSB

N – 17

D06

N – 17

D05

N – 16

MSB

N – 16

D04

N – 16

D10

N – 16

D03

N – 16

D09

N – 16

D02

N – 16

D08

N – 16

D01

N – 16

D07

N – 16

LSB

N – 16

D06

N – 16

10065-006

BYTEWISE

Figure 5. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode

VIN±x

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D0–x

D0+x

N – 1

t

A

t

FCO

PD

CPD

t

EH

t

FRAME

t

DATA

D12

MSB

N–17

N – 17

D11

D10

N – 17

N – 17D9N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17

t

EL

N

LSB

N – 170N – 170N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

10065-002

Figure 6. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode

Rev. 0 | Page 9 of 40

AD9253 Data Sheet

S

VIN±x

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D0–x

D0+x

N – 1

t

A

t

EH

t

CPD

t

FCO

t

PD

MSB

N–17

t

FRAME

D10

D9

N – 17

N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17D0N – 17

t

EL

t

DATA

N

MSB

D10

N – 16

10065-082

Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode

CLK+

t

SSYNC

t

HSYNC

YNC

Figure 8. SYNC Input Timing Requirements

10065-079

Rev. 0 | Page 10 of 40

Data Sheet AD9253

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V Digital Outputs

(D0±x, D1±x, DCO+,

DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND −0.3 V to +2.0 V VIN+x, VIN−x to AGND −0.3 V to +2.0 V SCLK/DTP, SDIO/OLM, CSB to AGND −0.3 V to +2.0 V SYNC, PDWN to AGND −0.3 V to +2.0 V RBIAS to AGND −0.3 V to +2.0 V VREF, SENSE to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature

Range (Ambient) Maximum Junction

Temperature Lead Temperature

(Soldering, 10 sec) Storage Temperature

Range (Ambient)

−0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 7. Thermal Resistance

Air Flow Veloc ity

Package Type

48-Lead LFCSP 0.0 23.7 7.8 7.1 °C/W

7 mm × 7 mm 1.0 20.0 N/A N/A °C/W (CP-48-13) 2.5 18.7 N/A N/A °C/W

1

θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

(m/sec)

1

θ

JA

JB

θJC Unit

ESD CAUTION

Rev. 0 | Page 11 of 40

AD9253 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

N+C

SYNC

AVDD

VIN–C

VI

47

48

VREF

SENSE

VCM

RBIAS

VIN+B

AVDD

VIN–B

41

37

39

42

43

40

44

45

46

38

1

VIN+D

2

VIN–D

3

AVD D

4

AVD D

5

CLK–

6

CLK+

7

AVD D

8

DRVDD

9

D1–D

10

D1+D

11

D0–D

12

D0+D

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVI DES THE ANALO G GROUND F OR THE PART . THIS EXPO SED PAD MUST BE CONNECTED TO GRO UND FOR PROPER OPERATION.

(Not to Scale)

13

14

15

D1–C

D0–C

D1+C

AD9253

TOP VIEW

19

18

17

16

–

D0+C

FCO

DCO–

DCO+

20

21

D1–B

FCO+

Figure 9. 48-Lead LFCSP Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

0

1 2

AGND, Exposed Pad

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the

analog ground for the part. This exposed pad must be connected to ground for proper operation. VIN+D ADC D Analog Input True. VIN−D ADC D Analog Input Complement.

3, 4, 7, 34, 39, 45, 46 AVDD 1.8 V Analog Supply Pins. 5, 6 8, 29 9, 10

CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. DRVDD Digital Output Driver Supply. D1−D, D1+D Channel D Digital Outputs.

11, 12 D0−D, D0+D Channel D Digital Outputs. 13, 14 15, 16 17, 18 19, 20 21, 22 23, 24

D1−C, D1+C Channel C Digital Outputs. D0−C, D0+C Channel C Digital Outputs. DCO−, DCO+ Data Clock Outputs. FCO−, FCO+ Frame Clock Outputs. D1−B, D1+B Channel B Digital Outputs. D0−B, D0+B Channel B Digital Outputs.

25, 26 D1−A, D1+A Channel A Digital Outputs. 27, 28 D0−A, D0+A Channel A Digital Outputs. 30 31 32 33

SCLK/DTP SPI Clock Input/Digital Test Pattern. SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up. PDWN

Digital Input, 30 kΩ Internal Pull-Down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

35 VIN−A ADC A Analog Input Complement. 36 37

VIN+A ADC A Analog Input True. VIN+B ADC B Analog Input True.

38 VIN−B ADC B Analog Input Complement. 40 41 42 43

RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. SENSE Reference Mode Selection. VREF Voltage Reference Input and Output. VCM Analog Input Common-Mode Voltage.

Rev. 0 | Page 12 of 40

36

VIN+A VIN–A

35

AVD D

34

PDWN

33 32

CSB SDIO/OLM

31

SCLK/DTP

30

DRVDD

29 28

D0+A D0–A

27

D1+A

26 25

D1–A

22

23

24

D0–B

D1+B

D0+B

10065-007

ANALOG DEVICES AD9253 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS