Analog Devices AD8582CHIPS, AD8582AR, AD8582AN Datasheet

+5 Volt, Parallel Input

DATA

REFERENCE

12-BIT
DAC A

DAC A

REGISTER

INPUT A

REGISTER

12-BIT
DAC B

DAC B

REGISTER

INPUT B

REGISTER

12

12

2

12

V

DD

V

OUTA

V

OUTB

V

REF

AGND

DGND

MSB

RST

LDA

CS

A/B

LDB

AD8582

2.0

–2.0

4096

–1.0

–1.5

0

0.0

–0.5

0.5

1.0

1.5

307220481024

DIGITAL INPUT CODE – Decimal

LINEARITY ERROR – LSB

VDD = +5V
TA = –55°C, +25°C, +85°C

= +25°C & +85°C
= –55°C

a

FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, ±5 mA Drive
Very Low Power: 5 mW

APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals

GENERAL DESCRIPTION

The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.

Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (V
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.

The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ± 5 mA. Operation down to

4.3 V is possible with output load currents less than 1 mA.

5.0

∆∆VFS ≤ 1 LSB

4.8

DATA = FFF
TA = +25°C

H

) is trimmed

REF

Complete Dual 12-Bit DAC

AD8582

FUNCTIONAL BLOCK DIAGRAM

The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc­ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re­spective DAC registers. An address input decodes DAC A or
DAC B when the chip select
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.

The AD8582 is available in the 24-pin plastic DIP and the sur­face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.

CS input is strobed. An asynchro-

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

4.6
PROPER OPERATION

MIN – Volts

DD

V

4.4

4.2

4.0

0.01

WHEN V

VOLTAGE ABOVE

SUPPLY

DD

CURVE

0.1 100101.0

OUTPUT LOAD CURRENT – mA

Figure 1. Minimum Supply Voltage vs. Load

Figure 2. Linearity Error vs. Digital Code and Temperature

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD8582–SPECIFICA TIONS

ELECTRICAL CHARACTERISTICS

(@ VDD = +5.0 V ± 5%, RL = No Load, –40°C ≤ TA ≤ +85°C, unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

STATIC PERFORMANCE

Resolution N Note 1 12 Bits
Relative Accuracy INL –2 ±3/4 +2 LSB
Differential Nonlinearity DNL Monotonic –1 ±3/4 +1 LSB
Zero-Scale Error V
Full-Scale Voltage V

ZSE
FS

Full-Scale Tempco TCV

FS

Data = 000

H

Data = FFFH,

2

4.079 4.095 4.111 V

+0.2 +3 mV

Notes 2 and 3 ±16 ppm/°C

MATCHING PERFORMANCE

Linearity Matching Error ∆VFSA/B ±1 LSB

REFERENCE OUTPUT

Output Voltage V
Output Source Current I

REF

REF

Line Rejection LN
Load Regulation LD

REJ
REG

Note 4 –5 mA
I

= 0 mA to 5 mA 0.1 %/mA

REF

2.484 2.500 2.516 V

0.08 %/V

ANALOG OUTPUT

Output Current I
Load Regulation at Half Scale LD
Capacitive Load C

DYNAMIC CHARACTERISTICS

Crosstalk C
Voltage Output Settling Time

3

5

Digital Feedthrough F

t

OUT

REG

L

T

S

T

Data = 800
RL = 402 Ω to ∞, Data = 800
No Oscillation

H

3

H

1 3 LSB
500 pF

±5mA

>64 dB
To ±1 LSB of Final Value 16 µs
Signal Measured at DAC Output, While 35 nV s
Changing Data (LDA = LDB = “1”)

LOGIC INPUTS

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance C

TIMING SPECIFICATIONS

3, 6

Chip Select Pulse Width t
DAC Select Setup t
DAC Select Hold t
Data Setup t
Data Hold t
Load Setup t
Load Hold t
Load Pulse Width t
Reset Pulse Width t

IL
IH

IL

IL

CSW
AS
AH
DS
DH
LS
LH
LDW
RSW

2.4 V

Note 3 10 pF

30 ns
30 ns
0ns
30 ns
10 ns
20 ns
10 ns
20 ns
30 ns

0.8 V
10 µA

SUPPLY CHARACTERISTICS

Positive Supply Current I
Power Dissipation

7

DD

P

DISS

VIH = 2.4 V, VIL = 0.8 V 4 7 mA
V

= 0 V, VDD = +5 V 1 2 mA

IL

VIH = 2.4 V, VIL = 0.8 V 20 35 mW
V

= 0 V, V

IL

= +5 V 5 10 mW

DD

Power Supply Sensitivity PSS ∆VDD = ±5% 0.002 0.004 %/%

NOTES

1

1 LSB = 1 mV for 0 V to +4.095 V output range.

2

Includes internal voltage reference error.

3

These parameters are guaranteed by design and not subject to production testing.

4

Very little sink current is available at the V

5

Settling time is not guaranteed for the first six codes 0 through 5.

6

All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

7

Power dissipation is a calculated value IDD × 5 V.

Specifications subject to change without notice.

pin. Use external buffer if setting up a virtual ground.

REF

–2–

REV. 0

AD8582

WARNING!

ESD SENSITIVE DEVICE

V

OUTA

AGND

V

OUTB

V

REF

MSB

DB0 DB11

DGND V

DD

DB1 DB10
DB2 DB9
DB3 DB8
DB4 DB7

DB5 DB6

14

1
2

24
23

5
6
7

20
19
18

3
4

22
21

8

17

9

16

10

15

11

TOP VIEW

(Not to Scale)

12

13

AD8582

LDA

RST

LDB

CS

A/B

TOP VIEW

(Not to Scale)

12

13

AD8582

1

24

ABSOLUTE MAXIMUM RATINGS*

VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, V

V

to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V

OUT

V

to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V

REF

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

I

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA

OUT

Package Power Dissipation . . . . . . . . . . . . . . .(T

Thermal Resistance, θ

JA

+ 0.3 V

DD

max–TA)/θ

J

DD

JA

24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W

24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

J

Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

t

CSW

t

t

AS

t

DS

t

LS

AH

t

DH

t

t

S

LDW

± 1LSB
ERROR BAND

t

LH

t

RSW

t

S

A/B

D0–D11

LDA, LDB

RST

V

OUT

CS

Timing Diagram

PIN DESCRIPTION

Pin No. Name Description

1, 24 V

V

OUTA
OUTB

Voltage outputs from the DACs. Fixed
output voltage range of 0 V to 4.095 V
with 1 mV/LSB. An internal
temperature stabilized reference
maintains a fixed full-scale voltage
independent of time, temperature and
power supply variations.

2 AGND Analog Ground. Ground reference for

the internal bandgap reference voltage,

the DAC, and the output buffer.
3 DGND Digital ground for input logic.
4, 21

LDA, Load DAC register strobes. Transfers
LDB input register data to the DAC registers.

Active low inputs, Level sensitive latch.

May be connected together to double-

buffer load DAC registers.
5 MSB Digital Input: High presets DAC

registers to half scale (800

clears DAC registers to zero (000

upon

RST assertion.

6

RST Active low digital input that clears the

), Low

H

)

H

DAC register to zero, setting the DAC

to minimum scale when MSB pin = 0,

or half-scale when MSB pin = 1.
7–18 DB

Twelve Binary Data Bit Inputs. DB11 is

0–11

the MSB and DB0 is the LSB.
19
20
22 V
23 V

CS Chip Select. Active low input.
A/B Select DAC A = 0 or DAC B = 1.

DD
REF

Positive Supply. Nominal value +5 V, ± 5%.

Nominal 2.5 V reference output

voltage. This node must be buffered if

required to drive external loads.

Model Range Description Option

AD8582AN –40°C to +85°C 24-Pin Plastic DIP N-24
AD8582AR –40°C to +85°C 24-Lead SOIC SOL-24
AD8582Chips +25°C Die

*For die specifications contact your local Analog Devices sales office. The

AD8582 contains 1270 transistors.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8582 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

ORDERING INFORMATION*

Temperature Package Package

–3–

PIN CONFIGURATIONS

N-24

24-Pin Plastic DIP

SOL-24

24-Pin SOIC