Analog Devices AD8400 2 3 c Datasheet

1-/2-/4-Channel

CODE – Decimal

100

75

50

25

0

0 64 128 192 255

R

WA

(D), R

WB

(D) – % of Nominal R

AB

R

WA

R

WB

a

Digital Potentiometers

AD8400/AD8402/AD8403

FEATURES
256-Position
Replaces 1, 2, or 4 Potentiometers
1 k, 10 k, 50 k, 100 k
Power Shutdown—Less than 5 A

V

DGND

3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate

2.7 V to 5.5 V Single-Supply Operation
Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching

CLK

Power Supply Adjustment

GENERAL DESCRIPTION

The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR) device.
These devices perform the same electronic adjustment function as
a potentiometer or variable resistor. The AD8400 contains a single
variable resistor in the compact SO-8 package. The AD8402 contains
two independent variable resistors in space-saving SO-14 surface­mount packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each part
contains a fixed resistor with a wiper contact that taps the fixed
resistor value at a point determined by a digital code loaded into the
controlling serial input register. The resistance between the wiper and
either endpoint of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. Each variable resistor
offers a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The fixed
A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%

to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When SHDN is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made that will produce
new wiper positions when the device is taken out of shutdown.

The AD8400 is available in both the SO-8 surface-mount and the
8-lead plastic DIP package.

The AD8402 is available in both surface mount (SO-14) and
14-lead plastic DIP packages, while the AD8403 is available in a
narrow body 24-lead plastic DIP and a 24-lead surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm thin
TSSOP-14/TSSOP-24 packages for PCMCIA applications. All
parts are guaranteed to operate over the extended industrial tem­perature range of –40°C to +125°C.

channel-to-channel matching tolerance with a nominal temperature
coefficient of 500 ppm/°C. A unique switching circuit minimizes the
high glitch inherent in traditional switched resistor designs avoiding
any make-before-break or break-before-make operation.

Each VR has its own VR latch that holds its programmed resistance
value. These VR latches are updated from an SPI compatible serial­to-parallel shift register that is loaded from a standard 3-wire
serial-input digital interface. Ten data bits make up the data word
clocked into the serial input register. The data word is decoded where
the first two bits determine the address of the VR latch to be loaded,
the last eight bits are data. A serial data output pin at the opposite end
of the serial register allows simple daisy-chaining in multiple VR
applications without additional external decoding logic.

The reset (RS) pin forces the wiper to the midscale position by
loading 80

into the VR latch. The SHDN pin forces the resistor

H

FUNCTIONAL BLOCK DIAGRAM

SDI

CS

AD8403

DD

DAC

SELECT

A1, A0

2

10-BIT

SERIAL

LATCH

D

CK Q

SDO

1
2

3
4

8

RS

LATCH

CK

LATCH

CK

LATCH

CK

LATCH

CK

8-BIT

8-BIT

8-BIT

8-BIT

RS

RS

RS

RS

RS

8

8

8

8

RDAC1

SHDN

RDAC2

SHDN

RDAC3

SHDN

RDAC4

SHDN

SHDN

A1
W1
B1
AGND1

A2
W2
B2
AGND2

A3
W3
B3
AGND3

A4
W4
B4
AGND4

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

Figure 1. RWA and RWB vs. Code

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(VDD = 3 V  10% or 5 V  10%, VA = VDD, VB = 0 V,

AD8400/AD8402/AD8403–SPECIFICATIONS

–40C ≤ TA ≤ +125C unless otherwise noted.)

ELECTRICAL CHARACTERISTICS–10 k VERSION

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Tempco ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

5

Capacitance6 Ax, Bx C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R = 10 kΩ 600 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk

NOTES

11

Typicals represent average readings at 25°C and VDD = 5 V.

12

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

1

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.

1

IW = 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.

13

V

14

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

1

DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.

15

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

16

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining

1

resistor terminals are left open circuit.

17

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

18

Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of IDD versus logic voltage.

19

P

10

All Dynamic Characteristics use VDD = 5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

11

= VDD, Wiper (VW) = No Connect.

AB

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

Specifications subject to change without notice.

2

2

3

4

4

7

6

8

9

R-DNL RWB, VA = No Connect –1 ±1/4 +1 LSB
R-INL RWB, VA = No Connect –2 ±1/2 +2 LSB
R

AB

/∆TV

AB

W

AB

TA = 25°C, Model: AD840XYY10 8 10 12 kΩ

= VDD, Wiper = No Connect 500 ppm/°C

AB

IW = 1 V/R 50 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = 25°C 0.2 1 %

INL –2 ±1/2 +2 LSB
DNL V
DNL V
DNL V

/∆T Code = 80

W

WFSE

WZSE

V

A, B, W

A, B

W

I

A_SD

W_SD

IH

IL

IH

IL

OH

OL

IL

C

IL

Range 2.7 5.5 V

DD

DD

I

DD

P

DISS

= 5 V –1 ±1/4 +1 LSB

DD

= 3 V TA = 25°C–1±1/4 +1 LSB

DD

= 3 V TA = –40°C, +85°C –1.5 ± 1/2 +1.5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H

H

–4 –2.8 0 LSB
0 1.3 2 LSB

0V

15 ppm/°C

V

DD

75 pF

120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= 5 V 100 200 Ω

DD

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V

DD

V

– 0.1 V

DD

IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or +5 V, VDD = 5 V ±1 µA

5pF

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW

PSS VDD = 3 V ± 10% 0.006 0.03 %/%

6, 10

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V, ±1% Error Band 2 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
VA = VDD, VB = 0 V –65 dB

C

W

S

NWB

T

–2–

REV. C

AD8400/AD8402/AD8403

SPECIFICATIONS

(VDD = 3 V  10% or 5 V  10%, VA = VDD, VB = 0 V, –40C ≤ TA ≤ +125C unless otherwise noted.)

ELECTRICAL CHARACTERISTICS–50 k and 100 k VERSIONS

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance

Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Tempco ∆VW/∆T Code = 80
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

5

Capacitance6 Ax, Bx C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_50K R = 50 kΩ 125 kHz

Total Harmonic Distortion THD
VW Settling Time tS_50K VA = VDD, VB = 0 V, ±1% Error Band 9 µs

Resistor Noise Voltage e

Crosstalk

NOTES

11

Typicals represent average readings at 25°C and VDD = 5 V.

12

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

1

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.

1

IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.

13

V

14

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

1

DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.

15

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

16

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining

1

resistor terminals are left open circuit.

17

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

18

Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of IDD versus logic voltage.

19

P

10

All Dynamic Characteristics use VDD = 5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

11

= VDD, Wiper (VW) = No Connect.

AB

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

Specifications subject to change without notice.

2

2

3

4

4

7

6

8

9

R-DNL RWB, VA = No Connect –1 ±1/4 +1 LSB
R-INL RWB, VA = No Connect –2 ±1/2 +2 LSB
R

AB

R

AB

/∆TV

AB

W

AB

TA = 25°C, Model: AD840XYY50 35 50 65 kΩ
TA = 25°C, Model: AD840XYY100 70 100 130 kΩ

= VDD, Wiper = No Connect 500 ppm/°C

AB

IW = 1 V/R 53 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = 25°C 0.2 1 %

INL –4 ±1 +4 LSB
DNL V
DNL V
DNL V

WFSE

WZSE

V

A, B, W

A, B

W

I

A_SD

W_SD

IH

IL

IH

IL

OH

OL

IL

C

IL

Range 2.7 5.5 V

DD

DD

I

DD

P

DISS

= 5 V –1 ±1/4 +1 LSB

DD

= 3 V TA = 25°C–1±1/4 +1 LSB

DD

= 3 V TA = –40°C, +85°C –1.5 ± 1/2 +1.5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H

H

–1 –0.25 0 LSB
0 +0.1 +1 LSB

0V

15 ppm/°C

V

DD

15 pF

80 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= 5 V 100 200 Ω

DD

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V

DD

V

– 0.1 V

DD

IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA

5pF

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW

PSS VDD = 3 V ± 10% 0.006 0.03 %/%

6, 10

BW_100K R = 100 kΩ 71 kHz

W

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %

tS_100K VA = VDD, VB = 0 V, ±1% Error Band 18 µs

_50K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz

NWB

e

_100K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz

NWB

C

T

VA = VDD, VB = 0 V –65 dB

REV. C

–3–

(VDD = 3 V  10% or 5 V  10%, VA = VDD, VB = 0 V,

AD8400/AD8402/AD8403–SPECIFICATIONS

–40C ≤ TA ≤ +125C unless otherwise noted.)

ELECTRICAL CHARACTERISTICS–1 k VERSION

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Temperature Coefficent ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

5

Capacitance6 Ax, Bx C
Capacitance6 Wx C
Shutdown Supply Current
Shutdown Wiper Resistance R

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% 0.0035 0.008 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_1K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk

NOTES

11

Typicals represent average readings at 25°C and VDD = 5 V.

12

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

1

positions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC 29 test circuit.

1

IW = 500 µA for VDD = 3 V and IW = 2.5 mA for VDD = 5 V for 1 kΩ version.

13

V

14

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.

15

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

16

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining

resistor terminals are left open circuit.

17

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

18

Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of IDD versus logic voltage.

19

P

DISS

10

All Dynamic Characteristics use VDD = 5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

11

= VDD, Wiper (VW) = No Connect.

AB

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

Specifications subject to change without notice.

2

2

3

4

4

7

6

8

9

R-DNL RWB, VA = No Connect –5 –1 +3 LSB
R-INL RWB, VA = No Connect –4 ±1.5 +4 LSB
R

AB

/∆TV

AB

W

AB

TA = 25°C, Model: AD840XYY1 0.8 1.2 1.6 kΩ

= VDD, Wiper = No Connect 700 ppm/°C

AB

IW = 1 V/R

AB

53 100 Ω

CH 1 to 2, VAB = VDD, TA = 25°C 0.75 2 %

INL –6 ±2 +6 LSB
DNL V
DNL V

/∆T Code = 80

W

WFSE

WZSE

V

A, B, W

A, B

W

I

A_SD

W_SD

IH

IL

IH

IL

OH

OL

IL

C

IL

Range 2.7 5.5 V

DD

DD

I

DD

P

DISS

= 5 V –4 –1.5 +2 LSB

DD

= 3 V, TA = 25°C –5 –2 +5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H

H

–20 –12 0 LSB
0 6 10 LSB

0V

25 ppm/°C

V

DD

75 pF

120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= 5 V 50 100 Ω

DD

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V

DD

V

– 0.1 V

DD

IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA

5pF

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW

PSS ∆VDD = 3 V ± 10% 0.05 0.13 %/%

6, 10

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VA = VDD, VB = 0 V, ±1% Error Band 0.5 µs
RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz
VA = VDD, VB = 0 V –65 dB

C

W

S

NWB

T

–4–

REV. C

AD8400/AD8402/AD8403

SPECIFICATIONS

(VDD = 3 V  10% or 5 V  10%, VA = VDD, VB = 0 V, –40C ≤ TA ≤ +125C unless otherwise noted.)

ELECTRICAL CHARACTERISTICS–ALL VERSIONS

Parameter Symbol Conditions Min Typ1Max Unit

SWITCHING CHARACTERISTICS

Input Clock Pulsewidth tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

Reset Pulsewidth t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.

3

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of 1 V/ µs should be maintained.

4

Propagation Delay depends on value of VDD, RL, and CL—see Applications section.

Specifications subject to change without notice.

1

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

V

DD

0V

V

SDI

CLK

CS

OUT

2, 3

4

DAC REGISTER LOAD

DS

DH

t

PD

CSS

CSW

RS

CSH

CS1

CL

Clock Level High or Low 10 ns

5ns
5ns

RL = 1 kΩ to 5 V, CL ≤ 20 pF 1 25 ns

10 ns
10 ns
50 ns
0ns
10 ns

1

SDI

(DATA IN)

SDO

(DATA OUT)

CLK

CS

V

OUT

0

1

A'x OR D'x A'x OR D'x

0

t

PD_MIN

1

0

1

0

V

DD

0V

t

CSS

Ax OR DxAx OR Dx

t

DS

t

DH

t

t

CH

t

CL

PD_MAX

t

CS1

t

CSH

1% ERROR BAND

t

t

S

CSW

1 %

REV. C

Figure 2a. Timing Diagram

Figure 2b. Detail Timing Diagram

t

1

RS

0

V

DD

V

OUT

VDD/2

RS

t

S



1% ERROR BAND



1%

Figure 2c. Reset Timing Diagram

–5–

AD8400/AD8402/AD8403

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

A

DD

AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . . . ±20 mA

Digital Input and Output Voltage to GND . . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . –40°C to +125°C

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

J

ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB

9

2

Table I. Serial Data Word Format

8

2

7

2

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Package Power Dissipation . . . . . . . . . . . . . (T

max – TA)/θ

J

JA

Thermal Resistance (θJA)

P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83° C/W

P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . . 180°C/W

TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . . 143°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8400/AD8402/AD8403 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

0

2

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REV. C