Analog Devices AD8400, AD8402, AD8403 Service Manual
R
1-/2-/4-Channel
FEATURES
256-position variable resistance device
Replaces 1, 2, or 4 potentiometers
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Power shutdown—less than 5 µA
3-wire,SPI-compatible serial data input
10 MHz update data loading rate
2.7 V to 5.5 V single-supply operation
APPLICATIONS
Mechanical potentiometer replacement
Programmable filters, delays, time constants
Volume control, panning
Line impedance matching
Power supply adjustment
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single-, dual-, or
quad-channel, 256-position, digitally controlled variable resistor
(VR) device.
ment function as a mechanical potentiometer or variable
resistor. The AD8400 contains a single variable resistor in the
compact SOIC-8 package. The AD8402 contains two independent
variable resistors in space-saving SOIC-14 surface-mount
packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each
part contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by the digital code
loaded into the controlling serial input register. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. Each variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional
switched resistor designs, avoiding any make-before-break
or break-before-make operation.
1
These devices perform the same electronic adjust-
(continued on Page 3)
Digital Potentiometers
AD8400/AD8402/AD8403
FUNCTIONAL BLOCK DIAGRAM
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8
8
8
8
AD8403
V
DD
DGND
SDI
CLK
CS
DAC
SELECT
1
2
3
4
A1, A0
2
10-BIT
8
SERIAL
LATCH
D
CK RSQ
SDO SHDNRS
Figure 1.
100
R
)
AB
75
50
(D) (% of Nominal R
WB
25
(D),
WA
R
0
0 64 128 192 255
WA
CODE ( Decimal )
Figure 2. RWA and RWB vs. Code
RDAC1
SHDN
RDAC2
SHDN
RDAC3
SHDN
RDAC4
SHDN
R
WB
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
1092-001
01092-002
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
AD8400/AD8402/AD8403
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution................................................................................ 11
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Electrical Characteristics—10 kΩ Version................................ 4
Electrical Characteristics—50 kΩ and 100 kΩ Versions......... 6
Electrical Characteristics—1 kΩ Version.................................. 8
Electrical Characteristics—All Versions .................................10
Timing Diagrams........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
Serial Data-Word Format.......................................................... 11
REVISION HISTORY
10/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Features...........................................................................1
Changes to Table 1.............................................................................4
Changes to Table 2.............................................................................6
Changes to Table 3.............................................................................8
Changes to Table 5...........................................................................11
Added Figure 36...............................................................................18
Replaced Figure 37 ..........................................................................19
Changes to Theory of Operation Section.....................................20
Changes to Applications Section...................................................24
Updated Outline Dimensions........................................................26
Changes to Ordering Guide...........................................................28
Pin Configurations and Function Descriptions......................... 12
Typical Performanc e Character istics ........................................... 14
Test Circ uit s..................................................................................... 19
Theory of Operation ...................................................................... 20
Programming the Variable Resistor......................................... 20
Programming the Potentiometer Divider............................... 21
Digital Interfacing...................................................................... 21
Applications..................................................................................... 24
Active Filter .................................................................................24
Outline Dimensions .......................................................................26
Ordering Guide .......................................................................... 28
11/01—Rev. B to Rev. C
Addition of new Figure.....................................................................1
Edits to Specifications.......................................................................2
Edits to Absolute Maximum Ratings..............................................6
Edits to TPCs 1, 8, 12, 16, 20, 24, 35...............................................9
Edits to
the Programming the Variable Resistor Section..........................13
Rev. D | Page 2 of 32
AD8400/AD8402/AD8403
GENERAL DESCRIPTION
(continued from Page 1)
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPIcompatible, serial-to-parallel shift register that is loaded from
a standard 3-wire, serial-input digital interface. Ten data bits
make up the data-word clocked into the serial input register.
The data-word is decoded where the first two bits determine
the address of the VR latch to be loaded, and the last eight bits
are the data. A serial data output pin at the opposite end of the
serial register allows simple daisy chaining in multiple VR
applications without additional external decoding logic.
RS
The reset (
into the VR latch. The
to-end open-circuit condition on the A terminal and shorts the
wiper to the B terminal, achieving a microwatt power shutdown
state. When
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface is still active in shutdown so
that code changes can be made that will produce new wiper
positions when the device is taken out of shutdown.
) pin forces the wiper to midscale by loading 80H
SHDN
pin forces the resistor to an end-
SHDN
is returned to logic high, the previous latch
The AD8400 is available in the SOIC-8 surface mount. The
AD8402 is available in both surface-mount (SOIC-14) and
14-lead PDIP packages, while the AD8403 is available in a
narrow-body, 24-lead PDIP and a 24-lead, surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
Rev. D | Page 3 of 32
AD8400/AD8402/AD8403
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −2 ±1/2 +2 LSB
Nominal Resistance
3
R
AB
TA = 25°C, model: AD840XYY10 8 10 12 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 500 ppm/°C
Wiper Resistance R
R
Nominal Resistance Match ∆R/R
W
W
AB
VDD = 5V, IW = VDD/RAB 50 100 Ω
VDD = 3V, IW = VDD/RAB 200 Ω
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −2 ±1/2 +2 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
H
15 ppm/°C
−4 −2.8 0 LSB
0 1.3 2 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Capacitance Bx C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R
5
7
V
I
A_SD
A, B, W
A, B
W
W_SD
0 V
f = 1 MHz, measured to GND, code = 80
f = 1 MHz, measured to GND, code = 80
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
SHDN
= 0
= 0, VDD = 5 V
H
H
75 pF
120 pF
0.01 5 µA
100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
IH
IL
IH
IL
OH
OL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
1
Max Unit
DD
V
Rev. D | Page 4 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_10 K R = 10 kΩ 600 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk
1
Typical represents average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
11
W
S
NWB
C
T
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
= 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.
I
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V, ±1% error band 2 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0
9 nV/√Hz
VA = VDD, VB = 0 V −65 dB
Figure 37
vs. logic voltage.
DD
Rev. D | Page 5 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = No Connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = No Connect −2 ±1/2 +2 LSB
Nominal Resistance
R
3
R
AB
AB
TA = 25°C, Model: AD840XYY50 35 50 65 kΩ
TA = 25°C, Model: AD840XYY100 70 100 130 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, Wiper = No Connect 500 ppm/°C
Wiper Resistance R
R
Nominal Resistance Match ∆R/R
W
W
AB
VDD = 5V, IW = VDD/R
VDD = 3V, IW = VDD/R
AB
AB
50 100 Ω
200 Ω
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −4 ±1 +4 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
H
15 ppm/°C
−1 −0.25 0 LSB
0 +0.1 +1 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Bx CA, C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R
5
7
VA, VB, V
B
W
I
A_SD
W_SD
0 V
W
f = 1 MHz, measured to GND, code = 80
f = 1 MHz, measured to GND, code = 80
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
= 0
SHDN
= 0, VDD = 5 V
H
H
15 pF
80 pF
0.01 5 µA
100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
IH
IL
IH
IL
OH
OL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
1
Max Unit
DD
V
Rev. D | Page 6 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_50 K R = 50 kΩ 125 kHz
BW_100 K R = 100 kΩ 71 kHz
Total Harmonic Distortion THD
W
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VW Settling Time tS_50 K VA = VDD, VB = 0 V, ±1% error band 9 µs
t
Resistor Noise Voltage e
e
Crosstalk
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
= VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
I
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
11
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
_100 K VA = VDD, VB = 0 V, ±1% error band 18 µs
S
C
NWB
NWB
T
_50 K
_100 K
R
= 25 kΩ, f = 1 kHz, RS = 0
WB
R
= 50 kΩ, f = 1 kHz, RS = 0
WB
VA = VDD, VB = 0 V −65 dB
20 nV/√Hz
29 nV/√Hz
Figure 37
vs. logic voltage.
DD
Rev. D | Page 7 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—1 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = no connect −5 −1 +3 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −4 ±1.5 +4 LSB
Nominal Resistance
3
R
AB
TA = 25°C, model: AD840XYY1 0.8 1.2 1.6 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 700 ppm/°C
Wiper Resistance R
R
W
W
Nominal Resistance Match ∆R/R
VDD = 5V, IW = VDD/R
VDD = 3V, IW = VDD/R
CH 1 to CH 2, VAB = VDD, TA = 25°C 0.75 2 %
AB
AB
AB
53 100 Ω
200 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −6 ±2 +6 LSB
Differential Nonlinearity4 DNL VDD = 5 V −4 −1.5 +2 LSB
DNL VDD = 3 V, TA = 25°C −5 −2 +5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H 25 ppm/°C
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
−20 −12 0 LSB
0 6 10 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Bx CA, C
Capacitance6 Wx C
Shutdown Supply Current
Shutdown Wiper Resistance R
5
7
VA, VB, VW 0 V
f = 1 MHz, measured to GND, code = 80H 75 pF
B
f = 1 MHz, measured to GND, code = 80H 120 pF
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
= 0
SHDN
= 0, VDD = 5 V
0.01 5 µA
50 100 Ω
I
W
A_SD
W_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance6 C
IH
IL
IH
IL
OH
OL
IL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% 0.0035 0.008 %/%
PSS ∆VDD = 3 V ± 10% 0.05 0.13 %/%
1
Max Unit
DD
V
Rev. D | Page 8 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_1 K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
11
W
S
NWB
C
T
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in . I
I
= 2.5 mA for VDD = 5 V for 1 kΩ version.
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VA = VDD, VB = 0 V, ±1% error band 0.5 µs
RWB = 500 Ω, f = 1 kHz, RS = 0
3 nV/√Hz
VA = VDD, VB = 0 V −65 dB
Figure 38
Figure 37
= 500 µA for VDD = 3 V and
W
vs. logic voltage.
DD
Rev. D | Page 9 of 32
AD8400/AD8402/AD8403
V
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ
SWITCHING CHARACTERISTICS
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay
CS
Setup Time
CS
High Pulse Width
Reset Pulse Width t
CLK Fall to CS Rise Hold Time
CS
Rise to Clock Rise Setup
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3
See the timing diagram in for location of measured values. All input control voltages are specified with tFigure 3
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
of 1 V/µs should be maintained.
4
Propagation delay depends on the value of VDD, RL, and CL (see the section). Applications
TIMING DIAGRAMS
1
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
V
DD
0V
Figure 3. Timing Diagram
V
SDI
CLK
CS
OUT
2, 3
4
DAC REG ISTE R LOAD
CL
DS
DH
t
PD
t
CSS
t
CSW
RS
t
CSH
t
CS1
Clock level high or low 10 ns
5 ns
5 ns
RL = 1 kΩ to 5 V, CL ≤ 20 pF 1 25 ns
10 ns
10 ns
50 ns
0 ns
10 ns
= tF = 1 ns (10% to 90% of VDD) and
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
DD
R
t
1
RS
0
V
DD
OUT
01092-003
VDD/2
Figure 5. Reset Timing Diagram
RS
±1% ERROR BAND
1
SDI
(DATA IN)
SDO
(DATA OUT)
CLK
V
OUT
0
1
A'x OR D'x A'x OR D'x
0
t
PD_MIN
1
0
1
CS
0
V
DD
0V
t
CSS
Figure 4. Detailed Timing Diagram
Ax OR DxAx OR Dx
t
DS
t
DH
t
t
CH
t
CL
PD_MAX
t
CS1
t
CSH
±1% ERROR BAND
t
t
S
CSW
±1%
01092-004
1
Max Unit
t
S
±1%
01092-005
Rev. D | Page 10 of 32
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