FEATURES
250 MHz–1000 MHz Operating Frequency
+2.5 dBm P1 dB @ 800 MHz
–155 dBm/Hz Noise Floor
0.5 Degree RMS Phase Error (IS95)
0.2 dB Amplitude Balance
Single 2.7 V–5.5 V Supply
Pin-Compatible with AD8346
16-Lead Exposed Paddle TSSOP Package
APPLICATIONS
Cellular Communication Systems
W-CDMA/CDMA/GSM/PCS/ISM Transceivers
Fixed Broadband Access Systems LMDS/MMDS
Wireless LAN
Wireless Local Loop
Digital TV/CATV Modulators
Single Sideband Upconverter
Quadrature Modulator
AD8345
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
COM3
COM1
LOIN
LOIP
VPS1
ENBL
1
2
3
4
5
6
7
8
AD8345
PHASE
SPLITTER
BIAS
+
16
15
14
13
12
11
10
9
QBBP
QBBN
COM3
COM3
VPS2
VOUT
COM2
COM3
PRODUCT DESCRIPTION
The AD8345 is a silicon RFIC quadrature modulator, designed
for use from 250 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable the high performance direct
modulation of an IF carrier.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase-splitter
network. The two I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50 Ω drive at VOUT.
APPLICATIONS
The AD8345 Modulator can be used as the IF transmit modulator in digital communication systems such as GSM and PCS
transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV systems.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 Modulator is supplied in a 16-lead TSSOP package with exposed paddle. Its performance is specified over a
–40°C to +85°C temperature range. This device is fabricated on
Analog Devices’ advanced silicon bipolar process.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
(VS = 5 V; LO= –2 dBm @ 800 MHz, 50 ⍀ source and load impedances, I and Q inputs
0.7 V ⴞ 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency.
TA = 25ⴗC, unless otherwise noted.)
ParametersConditionsMinTypMaxUnit
RF OUTPUT
Operating Frequency
1
2501000MHz
Output Power–3–1+2dBm
Output P1 dB2.5dBm
Noise Floor20 MHz Offset from LO, All BB–155dBm/Hz
Inputs at 0.7 V
Quadrature Error(CDMA IS95 Setup, Refer to Figure 13)0.5Degree rms
I/Q Amplitude Balance(CDMA IS95 Setup, Refer to Figure 13)0.2dB
LO Leakage–42–33dBm
Sideband Rejection–42–34dBc
Third Order Distortion–52dBc
Second
Order Distortion–60dBc
Equivalent Output IP325dBm
Equivalent Output IP259dBm
Output Return Loss (S22)–20dB
RESPONSE TO CDMA IS95(Refer to Figure 13)
BASEBAND SIGNALS
ACPR–72dBc
EVM1.3%
Rho0.9995
LO INPUT
LO Drive level–10–20dBm
LOIP Input Return Loss (S11)
2
No Termination on LOIP, LOIN at–5dB
AC Ground
50 Ω Terminating Resistor, Differential–9dB
Drive via Balun
BASEBAND INPUTS
Input Bias Current10µA
Input Capacitance2pF
DC Common Level0.60.70.8V
Bandwidth (3 dB)Full Power (0.7 V ± 0.3 V on Each80MHz
Input, Refer to TPC 2)
ENABLE
Turn-OnEnable High to Output within 0.5 dB of2.5µs
Final Value
Turn-OffEnable Low to Supply Current Dropping1.5µs
below 2 mA
ENBL High Threshold (Logic 1)+V
/2V
S
ENBL Low Threshold (Logic 0)+VS/2V
POWER SUPPLIES
Voltage2.75.5V
Current Active506578mA
Current Standby70µA
NOTES
1
For information on operation below 250 MHz, see Figure 4.
2
See LO Drive section for more details on input matching.
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8345 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD8345ARE–40°C to +85°CTube (16-Lead TSSOP with Exposed Pad)RE-16
AD8345ARE-REEL13" Tape and Reel
AD8345ARE-REEL77" Tape and Reel
AD8345-EVALEvaluation Board
REV. 0
–3–
AD8345
PIN FUNCTION DESCRIPTIONS
Equivalent
Pin No.MnemonicFunctionCircuit
1, 2IBBP, IBBNI Channel Baseband Differential Input Pins. These high impedance inputs shouldCircuit A
be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p
on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are
not self-biasing so external biasing circuitry must be used in ac-coupled applications.
3, 9, 13, 14COM3Ground Pin for Input V-to-I Converters and Mixer Core.
4COM1Ground Pin for the LO Phase-Splitter and LO Buffers.
5, 6LOIN, LOIPDifferential LO Drive Pins. Internal dc bias (approximately 1.8 V @ V
is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible.
7VPS1Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled
using local 1000 pF and 0.01 µF capacitors.
8ENBLEnable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C
10COM2Ground Pin for the Output Stage of Output Amplifier.
11VOUT50 Ω DC-Coupled RF Output. Pin should be ac-coupled.Circuit D
12VPS2Power supply pin for baseband input voltage to current converters and mixer core.
This pin should be decoupled using local 1000 pF and 0.01 µF capacitors.
15, 16QBBN, QBBPQ Channel Baseband Differential Input Pins. Inputs should be dc biased toCircuit A
approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin
(0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not
self-biasing so external biasing circuitry must be used in ac-coupled applications.