Analog Devices AD8202 c Datasheet

High Common-Mode Voltage,

FEATURES

High common-mode voltage range

−8 V to +28 V at a 5 V supply voltage
Operating temperature range: −40°C to +125°C
Supply voltage range: 3.5 V to 12 V
Low-pass filter (1-pole or 2-pole)

EXCELLENT AC AND DC PERFORMANCE

±1 mV voltage offset
±1 ppm/°C typ gain drift
80 dB CMRR min dc to 10 kHz

PLATFORMS

Transmission control
Diesel injection control
Engine management
Adaptive suspension control
Vehicle dynamics control

GENERAL DESCRIPTION

The AD8202 is a single-supply difference amplifier for amplifying
and low-pass filtering small differential voltages in the presence of a
large common-mode voltage. The input CMV range extends from

−8 V to +28 V at a typical supply voltage of 5 V.

Single-Supply Difference Amplifier

AD8202

FUNCTIONAL BLOCK DIAGRAM

+V

A2

3

INDUCTIVE
LOAD

+IN

–IN

647

G = ×2

+IN

A2

–IN

5V

NC

+V

AD8202

GND

A1

S

AD8202

5

OUT

10kΩ

10kΩ

2

GND

OUT

S

A2

04981-001

OUTPUT

8

+IN

1

–IN

BATTERY

NC A1

200kΩ200kΩ

NC = NO CONNECT

Figure 1. SOIC (R) Package Die Form

CLAMP

DIODE

14V

G = ×10

+IN

A1

–IN

4-TERM

SHUNT

POWER
DEVICE

100kΩ

The AD8202 is offered in die and packaged form. Both package
options are specified over a wide temperature range of −40°C to
+125°C, making the AD8202 well-suited for use in many auto­motive platforms.

Automotive platforms demand precision components for better
system control. The AD8202 provides excellent ac and dc
performance, which keeps errors to a minimum in the user’s
system. Typical offset and gain drift in the SOIC package are

0.3 µV/°C and 1 ppm/°C, respectively. Typical offset and gain
drift in the MSOP package are 2 µV/°C and 1 ppm/°C, respec­tively. The device also delivers a minimum CMRR of 80 dB
from dc to 10 kHz.

The AD8202 features an externally accessible 100 kΩ resistor at
the output of the preamp A1, which can be used for low-pass
filter applications and for establishing gains other than 20.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

COMMON

NC = NO CONNECT

Figure 2. High-Line Current Sensor

POWER
DEVICE

BATTERY

14V

CLAMP

DIODE

COMMON NC = NO CONNECT

4-TERM

SHUNT

INDUCTIVE
LOAD

Figure 3. Low-Line Current Sensor

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

+IN

–IN

5V

NC

+V

AD8202

GND

A1

OUT

S

04981-002

OUTPUT

A2

04981-003

AD8202

TABLE OF CONTENTS

Specifications—Single Supply......................................................... 3

Gain Trim .................................................................................... 14

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 12

Applications..................................................................................... 13

Current Sensing .......................................................................... 13

Gain Adjustment ........................................................................ 13

REVISION HISTORY

2/05—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Figure 14........................................................................ 8

Changes to Figure 22........................................................................ 9

1/05—Rev. A to Rev. B

Changes to the General Description.............................................. 1

Changes to Specifications................................................................ 3

Added Figure 14 to Figure 33.......................................................... 8

Changes to Figure 38...................................................................... 14

Changes to Figure 40 and Figure 41............................................. 15

Changes to Ordering Guide.......................................................... 16

Low-Pass Filtering ...................................................................... 14

High-Line Current Sensing with LPF
and Gain Adjustment

Driving Charge Redistribution ADCs..................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

................................................................. 15

11/04—Rev. 0 to Rev. A

Changes to the Features................................................................... 1

Changes to the General Description.............................................. 1

Changes to Specifications (Table 1) ............................................... 3

Changes to Absolute Maximum Ratings (Table 2) ...................... 4

Changes to Pin Function Descriptions (Table 3) ......................... 5

Changes to Figure 5.......................................................................... 5

Changes to Figure 9 and Figure 10................................................. 6

Updated Outline Dimensions....................................................... 12

Changes to the Ordering Guide.................................................... 12

7/04—Revision 0: Initial Version

Rev. C | Page 2 of 16

AD8202

SPECIFICATIONS—SINGLE SUPPLY

TA = operating temperature range, VS = 5 V, unless otherwise noted.

Table 1.

AD8202 SOIC AD8202 MSOP AD8202 Die
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

SYSTEM GAIN

Initial 20 20 20 V/V
Error

0.02 ≤ V

OUT

≤

4.8 V dc @ 25°C

vs. Temperature 1 20 1 25 1 30 ppm/°C

VOLTAGE OFFSET

Input Offset (RTI) VCM = 0.15 V; 25°C −1 +1 −2 +2 −1 +1 mV
vs. Temperature −40°C to +125°C −10 +0.3 +10 −20 +2 +20 −10 +0.3 +10 µV/°C

−40°C to +150°C −15 +5 +15 µV/°C
INPUT

Input Impedance

Differential 260 325 390 260 325 390 260 325 390 kΩ

Common-Mode 135 170 205 135 170 205 135 170 205 kΩ
CMV Continuous −8 +28 −8 +28 −8 +28 V
Common-Mode Rejection

1

VCM = −8 V to +28 V
f = dc 82 82 82 dB
f = 1 kHz 82 82 82 dB
f = 10 kHz

2

PREAMPLIFIER

Gain 10 10 10 V/V
Gain Error −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 %
Output Voltage Range 0.02 4.8 0.02 4.8 0.02 4.8 V
Output Resistance 97 100 103 97 100 103 97 100 103 kΩ

OUTPUT BUFFER

Gain 2 2 2 V/V
Gain Error 0.02 ≤ V

≤ 4.8 V dc −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 %

OUT

Output Voltage Range 0.02 4.8 0.02 4.8 0.02 4.8 V
Input Bias Current 40 40 40 nA
Output Resistance 2 2 2 Ω

DYNAMIC RESPONSE

System Bandwidth

Slew Rate

= 0.1 V p-p;

V

IN

= 2.0 V p-p

V

OUT

= 0.2 V dc;

V

IN

V

= 4 V step

OUT

NOISE

0.1 Hz to 10 Hz 10 10 10 µV p-p
Spectral Density, 1 kHz (RTI) 275 275 275 nV/√Hz

POWER SUPPLY

Operating Range 3.5 12 3.5 12 3.5 12 V

= 0.1 V dc 0.25 1.0 0.25 1.0 0.25 1.0 mA

Quiescent Current vs.

V

O

Temperature

PSRR VS = 3.5 V to 12 V 75 83 75 83 75 83 dB

TEMPERATURE RANGE

For Specified Performance −40 +125 −40 +125 −40 +150 °C

See notes on next page.

−0.3 +0.3 −0.3 +0.3 %

80 80 80 dB

30 50 30 50 30 50 kHz

0.28 0.28 0.28 V/µs

Rev. C | Page 3 of 16

AD8202

1

Source imbalance < 2 Ω.

2

The AD8202 preamplifier exceeds 80 dB CMRR at 10 kHz. However, because the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-

pin capacitance between Pins 1, 8 and 3, 4 might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-to­pin coupling can be neglected in all applications by using filter capacitors at Node 3.

Rev. C | Page 4 of 16

AD8202

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 12.5 V
Transient Input Voltage (400 ms) 44 V
Continuous Input Voltage (Common Mode) 35 V
Reversed Supply Voltage Protection 0.3 V
Operating Temperature Range

Die −40°C to +150°C
SOIC −40°C to +125°C

MSOP −40°C to +125°C
Storage Temperature −65°C to +150°C
Output Short-Circuit Duration Indefinite
Lead Temperature Range (Soldering, 10 sec) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec­trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. C | Page 5 of 16

AD8202

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

–IN

GND

2

A1

3

(Not to Scale)

A2

4

NC = NO CONNECT

AD8202

TOP VIEW

8

+IN
NC

7

+V

6

S

OUT

5

04981-004

Figure 4. 8-Lead SOIC

Table 3. 8-Lead SOIC Pin Function Descriptions

Pin No. Mnemonic X Y

1 −IN −409.0 −205.2
2 GND −244.6 −413.0
3 A1 +229.4 −413.0
4 A2 +410.0 −308.6
5 OUT +410.0 +272.4
6 +Vs +121.0 +417.0
7 NC NA NA
8 +IN −409.0 +205.2

1048µm

+IN

–IN

1036µm

+V

S

A1GND

Figure 5. Metallization Photograph

OUT

A2

04981-005

Rev. C | Page 6 of 16

AD8202

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, VCM = 0 V, RL = 10 kΩ, unless otherwise noted.

90

80

70

60

50

40

PSRR (dB)

30

20

10

0

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 6. Power Supply Rejection Ratio vs.

Frequency Valid for CM Range −8 V to +28 V

30

04981-006

0

–5

–10

–15

–20

–25

COMMON-MODE VOLTAGE (V)

–30

–35

345678910111213

POWER SUPPLY (V)

–55°C

–40°C

+25°C

+125°C

+150°C

Figure 9. Negative Common-Mode Voltage vs. Voltage Supply

40

04981-009

25

20

15

OUTPUT (dB)

10

5

0

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 7. AD8202 Bandwidth

100

95

90

85

CMRR (dB)

80

75

70

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 8. Common -Mode Rejection Ratio vs. Frequency

Valid for CM Range −8 V to +28 V

04981-007

04981-008

35

30

–55°C

25

20

15

10

COMMON-MODE VOLTAGE (V)

5

0

3654871091112

+150°C

+125°C

–40°C

+25°C

POWER SUPPLY (V)

Figure 10. Positive Common-Mode Voltage vs. Voltage Supply

5.0

4.5

4.0

3.5

3.0

2.5

2.0

OUTPUT SWING (V)

1.5

1.0

0.5
0

10 100 1k 10k

LOAD RESISTANCE (Ω)

Figure 11. Output Swing vs. Load Resistance

04981-010

13

04981-011

Rev. C | Page 7 of 16

AD8202

0

–10

–20

–30

–40

–50

OUTPUT MINUS SUPPLY (mV)

–60

NO LOAD

10k LOAD

HITS

30

25

20

15

10

5

V

= 5V

SUPPLY

TEMPERATURE RANGE =

°

C TO 125°C

25

–70

3654871091112

SUPPLY VOLTAGE (V)

Figure 12. Output Minus Supply vs. Supply Voltage

OUTPUT

1

2

CH1 500mVΩ 50mVΩ M 20µs 2.5MS/s 400NS/PT

CH2

INPUT

A CH1 1.73V

Figure 13. Pulse Response

25

20

15

HITS

10

V

= 5V

SUPPLY

TEMPERATURE RANGE =

°

C TO+25°C

–40

04981-012

13

04981-013

HITS

HITS

0

–9.0

–8.0

–7.0

–6.0

–5.0

–4.0

–3.0

–2.0

–10.0

–1.0

V

DRIFT (µV/°C)

OS

Figure 15. Offset Drift Distribution, SOIC

40

35

30

25

20

15

10

5

0

–900

–800

–700

–600

–500

–400

–300

–1500

–1400

–1300

–1100

–1200

–1000

Figure 16. V

35

30

25

20

15

–200

V

Distribution, SOIC

OS

2.0

1.003.0

TEMPERATURE = 25°C

200

1000300

400

–100

(µV)

OS

TEMPERATURE = –40°C

500

4.0

600

5.0

700

800

6.0

900

7.0

1000

8.0

1100

1200

9.0

1300

10.0

1400

04981-027

04981-028

1500

5

0

–9.0

–8.0

–7.0

–6.0

–5.0

–4.0

–3.0

–2.0

–10.0

–1.0

V

DRIFT (µV/°C)

OS

Figure 14. Offset Drift Distribution, SOIC

2.0

1.003.0

4.0

5.0

6.0

7.0

8.0

9.0

04981-025

10.0

Rev. C | Page 8 of 16

10

5

1200

1300

1400

04981-029

1500

0

–1500

–1400

–1300

–1200

–900

–800

–1100

–1000

Figure 17. V

–700

–600

–500

–400

–300

Distribution, SOIC

OS

–200

V

OS

–100

1000300

(µV)

200

400

500

600

700

800

900

1000

1100

AD8202

HITS

30

25

20

15

10

5

0

–900

–800

–700

–600

–500

–400

–1500

–1400

–1300

–1100

–1200

–1000

Figure 18. V

40

35

30

–300

Distribution, SOIC

OS

TEMPERATURE = 125°C

200

1000300

–200

–100

V

(µV)

OS

TEMPERATURE = 25°C

400

500

600

700

800

900

1000

1100

1200

1300

1400

04981-030

1500

HITS

50

45

40

35
30

25

20

15

10

5
0

0

0.01

0.02

0.04

0.03

0.05

0.06

0.07

0.08

0.09

0.10

0.11

0.12

0.13

ERROR (%)

TEMPERATURE = –40°C

0.17

0.14

0.16

0.15

0.18

0.19

0.20

0.21

0.22

0.23

0.24

0.25

0.26

0.27

0.28

0.29

04981-033

0.30

Figure 21. SOIC Gain Accuracy

8

7

6

V

= 5V

SUPPLY

TEMPERATURE RANGE =
–40°C TO

+

25°C

HITS

HITS

HITS

HITS

5

4

3

2

1

0

–28

–26

–24

–22

–20

–18

–16

–14

–12

–10

–6–8–4

–2

DRIFT (µV/°C)

V

OS

Figure 22. Offset Drift Distribution, MSOP

12

10

8

6

4

2

0

–28

–26

–24

–22

–20

–18

–16

–14

–12

–10

–6–8–4

–2

V

DRIFT (µV/°C)

OS

Figure 23. Offset Drift Distribution, MSOP

02468

02468

101214181620222428

V

= 5V

SUPPLY

TEMPERATURE RANGE =

25°C TO 125°C

101214181620222428

04981-034

26

04981-036

26

25

20

15

10

5

0.27

0.28

0.29

04981-031

0.30

0

0

0.01

0.02

0.04

0.03

0.05

0.06

0.07

0.08

0.09

0.10

0.11

0.12

0.13

0.14

0.15

ERROR (%)

0.16

0.17

0.18

0.19

0.20

0.21

0.22

0.23

0.24

0.25

0.26

Figure 19. SOIC Gain Accuracy

45

40

35

30

25

20

15

10

5

0

0

0.01

0.02

0.04

0.03

0.05

0.06

0.07

0.08

0.09

0.10

0.11

0.12

ERROR (%)

TEMPERATURE = 125°C

0.17

0.13

0.14

0.16

0.15

0.18

0.19

0.20

0.21

0.22

0.23

0.24

0.25

0.26

0.27

0.28

0.29

04981-032

0.30

Figure 20. SOIC Gain Accuracy

Rev. C | Page 9 of 16

AD8202

14

12

TEMPERATURE = 25°C

14

12

TEMPERATURE = 25°C

HITS

HITS

HITS

HITS

HITS

HITS

10

8

6

4

2

0.25

0.27

04981-040

0.29

0

0.01

0.05

0.03

0.07

0.09

0.11

0.13

0.17

0.15

0.19

0.21

–0.15

–0.13

–0.11

–0.07

–0.09

–0.05

–0.03

–0.01

ERROR (%)

0.23

Figure 27. MSOP Gain Accuracy

14

12

10

8

6

4

2

0

0.01

–0.15

–0.13

–0.11

–0.07

–0.09

–0.05

0.03

–0.03

–0.01

ERROR (%)

TEMPERATURE = 125°C

0.05

0.07

0.09

0.11

0.13

0.15

0.17

0.19

0.21

0.23

0.25

0.27

04981-041

0.29

Figure 28. MSOP Gain Accuracy

14

12

10

8

6

4

2

0

0.01

–0.15

–0.13

–0.11

–0.07

–0.09

–0.05

0.03

–0.03

–0.01

ERROR (%)

TEMPERATURE = –40°C

0.05

0.07

0.09

0.11

0.13

0.15

0.17

0.19

0.21

0.23

0.25

0.27

04981-042

0.29

Figure 29. MSOP Gain Accuracy

10

8

6

4

2

1800

1800

1800

2000

2000

2000

04981-037

2200

04981-038

2200

04981-039

2200

0

–2200

–2000

–1800

–1600

–1400

–1200

–1000

–800

Figure 24. V

10

9
8

7

6

5

4

3

2

1
0

–2200

–2000

–1800

–1600

–1400

–1200

–1000

–800

Figure 25. V

9

8

7

6

5

4

3

2

1
0

–2200

–2000

–1800

–1600

–1400

–1200

–1000

–800

Figure 26. V

0

200

400

–600

–400

–200

V

OS

Distribution, MSOP

OS

–600

–400

–200

V

OS

Distribution, MSOP

OS

–600

–400

–200

V

OS

Distribution, MSOP

OS

600

(µV)

TEMPERATURE = 125°C

0

200

400

600

(µV)

TEMPERATURE = –40°C

0

200

400

600

(µV)

800

800

800

1000

1000

1000

1200

1200

1200

1400

1400

1400

1600

1600

1600

Rev. C | Page 10 of 16

AD8202

HITS

18

16

14

12

10

8

6

4

2

0

–70

–65

–60

–45

–55

–50

–40

–35

–30

–25

–20

–15

CMRR (µV/V)

TEMPERATURE = 25°C

0

5

–5

10152030253540455055656070

–10

Figure 30. CMRR Distribution, −8 V to +28 V Common Mode

04981-043

1000

800

600

400

200

V)

µ

(

0

OS

V

–200

–400

–600

–800

–1000

–10 –5 10502015 30

+125°C

Figure 31. V

+25°C

COMMON-MODE VOLTAGE (V)

OS

+85°C

vs. Common-Mode Voltage

–40°C

25

04981-044

Rev. C | Page 11 of 16

AD8202

THEORY OF OPERATION

The AD8202 consists of a preamp and buffer arranged as shown
in Figure 32. Like-named resistors have equal values.

The preamp uses a dynamic bridge (subtractor) circuit. Identi­cal networks (within the shaded areas), consisting of R

, attenuate input signals applied to Pins 1 and 8. When

and R

G

equal amplitude signals are asserted at inputs 1 and 8, and the
output of A1 is equal to the common potential (that is, 0), the
two attenuators form a balanced-bridge network. When the
bridge is balanced, the differential input voltage at A1, and
thus its output, is 0.

Any common-mode voltage applied to both inputs keeps the
bridge balanced and the A1 output at zero. Because the resistor
networks are carefully matched, the common-mode signal
rejection approaches this ideal state.

However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive R

, by way of RG, to adjust the voltage at its inverting

B

input until it matches the voltage at its noninverting input.

By attenuating voltages at Pins 1 and 8, the amplifier inputs are
held within the power supply range, even if Pin 1 and Pin 8
input levels exceed the supply or fall below common (ground).
The input network also attenuates normal (differential) mode
voltages. R

and RG form an attenuator that scales A1 feedback,

C

forcing large output signals to balance relatively small differen­tial inputs. The resistor ratios establish the preamp gain at 10.

Because the differential input signal is attenuated and then
amplified to yield an overall gain of 10, Amplifier A1 operates at
a higher noise gain, multiplying deficiencies such as input offset
voltage and noise with respect to Pins 1 and 8.

+IN

8

R

R

R

R

G

–IN

1

R

A

A

A1

R

R

CM

R

B

B

R

R

G

C

C

CM

A3

100kΩ

(TRIMMED)

AD8202

3

, RB, RC,

A

4

A2

5

R

F

R

F

To minimize these errors while extending the common-mode
range, a dedicated feedback loop is employed to reduce the
range of common-mode voltage applied to A1 for a given over­all range at the inputs. By offsetting the voltage range applied to
the compensator, the input common-mode range is also offset
to include voltages more negative than the power supply.
Amplifier A3 detects the common-mode signal applied to A1
and adjusts the voltage on the matched R

resistors to reduce

CM

the common-mode voltage range at the A1 inputs. By adjusting
the common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.

The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for low­pass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio trimmed for high accuracy.

The output of the preamp drives a gain-of-2 buffer amplifier,
A2, implemented with carefully matched feedback resistors, R

F

The 2-stage system architecture of the AD8202 enables the
user to incorporate a low-pass filter prior to the output buffer.
By separating the gain into two stages, a full-scale, rail-to-rail
signal from the preamp can be filtered at Pin 3, and a half-scale
signal, resulting from filtering, can be restored to full scale by
the output buffer amp. The source resistance seen by the invert­ing input of A2 is approximately 100 kΩ to minimize the effects
of A2’s input bias current. However, this current is quite small
and errors resulting from applications that mismatch the resis­tance are correspondingly small.

.

2

COM

Figure 32. Simplified Schematic

04981-014

Rev. C | Page 12 of 16

AD8202

+

APPLICATIONS

+V

The AD8202 difference amplifier is intended for applications
where it is required to extract a small differential signal in the
presence of large common-mode voltages. The differential input
resistance is nominally 325 kΩ, and the device can tolerate
common-mode voltages higher than the supply voltage and
lower than ground.

The open-collector output stage sources current to within
20 mV of ground and to within 200 mV of V

.

S

V

DIFF

2

V

V

CM

DIFF

2

AD8202

100kΩ

S

NC+IN

OUT+V

S

10kΩ10kΩ

OUT

20R

R

EXT

= 100kΩ

EXT

+ 100kΩ

GAIN

20 – GAIN

GAIN =

R

EXT

A2A1GND–IN

CURRENT SENSING

High-Line, High Current Sensing

Basic automotive applications using the large common-mode
range are shown in Figure 2 and Figure 3. The capability of the
device to operate as an amplifier in primary battery-supply
circuits is shown in Figure 2; Figure 3 illustrates the ability of
the device to withstand voltages below system ground.

Low Current Sensing

The AD8202 can also be used in low current sensing applications,
such as the 4 to 20 mA current loop shown in Figure 33. In such
applications, the relatively large shunt resistor can degrade the
common-mode rejection. Adding a resistor of equal value on the
low impedance side of the input corrects for this error.

10Ω

1%

+IN

10Ω
1%

–IN

Figure 33. 4 to 20 mA Current Loop Receiver

5V

NC

+V

S

AD8202

GND

A1

NC = NO CONNECT

OUT

A2

OUTPUT

04981-015

GAIN ADJUSTMENT

The default gain of the preamplifier and buffer are ×10 and ×2,
respectively, resulting in a composite gain of ×20. With the
addition of external resistor(s) or trimmer(s), the gain may be
lowered, raised, or finely calibrated.

Gains Less than 20

Because the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pins 3 and 4 to GND decreases
the gain by a factor R

/(100 kΩ + R

EXT

) as shown in Figure 34.

EXT

R

EXT

NC = NO CONNECT

04981-016

Figure 34. Adjusting for Gains Less than 20

The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer. In
many cases this can be ignored, but if desired, it can be nulled
by inserting a resistor equal to 100 kΩ minus the parallel sum of

and 100 kΩ, in series with Pin 4. For example, with R

R

EXT

EXT

=
100 kΩ (yielding a composite gain of ×10), the optional offset
nulling resistor is 50 kΩ.

Gains Greater than 20

Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 35, increases the

/(R

gain. The gain is multiplied by the factor R
for example, it is doubled for R

= 200 kΩ. Overall gains as

EXT

EXT

− 100 kΩ);

EXT

high as 50 are achievable in this way. The accuracy of the gain
becomes critically dependent on the resistor value at high gains.
Also, the effective input offset voltage at Pin 1 and Pin 8 (about
six times the actual offset of A1) limits the part’s use in high
gain, dc-coupled applications.

+V

S

NC+IN

V

DIFF

2

V

V

CM

DIFF

2

NC = NO CONNECT

AD8202

100kΩ

OUT+V

S

10kΩ10kΩ

R

A2A1GND–IN

Figure 35. Adjusting for Gains Greater than 20

EXT

OUT

GAIN =

R

EXT

R

EXT

= 100kΩ

20R

– 100kΩ

GAIN – 20

EXT

GAIN

04981-017

Rev. C | Page 13 of 16

AD8202

GAIN TRIM

Figure 36 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor, R

The following approximation is useful for small gain ranges:

ΔG ≈ (10 MΩ ÷ R

Thus, the adjustment range is ±2% for R

= 1 MΩ, and so on.

R

EXT

V

DIFF

2

V

V

CM

DIFF

2

EXT

)%

+IN

–IN

5V

+V

NC

AD8202

GND

A1

= 5 MΩ; ±10% for

EXT

OUT

S

A2

R

EXT

.

EXT

OUT

GAIN TRIM
20kΩ MIN

Low-pass filters can be implemented in several ways by
using the AD8202. In the simplest case, a single-pole filter
(20 dB/decade) is formed when the output of A1 is connected
to the input of A2 via the internal 100 kΩ resistor by tying Pin 3
and Pin 4 and adding a capacitor from this node to ground, as
shown in Figure 37. If a resistor is added across the capacitor to
lower the gain, the corner frequency increases; it should be
calculated using the parallel sum of the resistor and 100 kΩ.

5V

+IN

+V

NC

AD8202

GND

A1

S

V

DIFF

2

V

V

CM

DIFF

2

–IN

OUT

A2

fC=

C IN FARADS

C

OUTPUT

2πC10

1

5

NC = NO CONNECT

04981-018

Figure 36. Incremental Gain Trim

Internal Signal Overload Considerations

When configuring gain for values other than 20, the maxi­mum input voltage with respect to the supply voltage and
ground must be considered, because either the preamplifier
or the output buffer reaches its full-scale output (approximately

– 0.2 V) with large differential input voltages. The input of

V

S

the AD8202 is limited to (V

– 0.2) ÷ 10 for overall gains ≤ 10,

S

because the preamplifier, with its fixed gain of ×10, reaches
its full-scale output before the output buffer. For gains greater
than 10, the swing at the buffer output reaches its full scale first
and limits the AD8202 input to (V

– 0.2) ÷ G, where G is the

S

overall gain.

LOW-PASS FILTERING

In many transducer applications, it is necessary to filter the
signal to remove spurious high frequency components includ­ing noise, or to extract the mean value of a fluctuating signal
with a peak-to-average ratio (PAR) greater than unity. For
example, a full-wave rectified sinusoid has a PAR of 1.57, a
raised cosine has a PAR of 2, and a half-wave sinusoid has a
PAR of 3.14. Signals having large spikes may have PARs of 10
or more.

When implementing a filter, the PAR should be considered so
that the output of the AD8202 preamplifier (A1) does not clip
before A2, because this nonlinearity would be averaged and
appear as an error at the output. To avoid this error, both ampli­fiers should clip at the same time. This condition is achieved
when the PAR is no greater than the gain of the second ampli­fier (2 for the default configuration). For example, if a PAR of 5
is expected, the gain of A2 should be increased to 5.

NC = NO CONNECT

04981-019

Figure 37. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor

If the gain is raised using a resistor, as shown in Figure 35, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz/µF
(0.039 µF for a 20 Hz corner frequency.)

5V

+IN

+V

OUT

NC

AD8202

GND

A1

S

A2

255kΩ

C

V

DIFF

2

V

V

DIFF

CM

2

–IN

NC = NO CONNECT

Figure 38. 2-Pole, Low-Pass Filter

C

f

(Hz) = 1/C(µF)

C

OUT

04981-020

A 2-pole filter (with a roll-off of 40 dB/decade) can be imple­mented using the connections shown in Figure 38. This is a
Sallen-Key form based on a ×2 amplifier. It is useful to remember
that a 2-pole filter with a corner frequency f
with a corner at f

2

/f1). The attenuation at that frequency is 40 log (f2/f1), which is

(f

2

have the same attenuation at the frequency

1

and a 1-pole filter

2

illustrated in Figure 39. Using the standard resistor value shown
and equal capacitors (Figure 38), the corner frequency is conven­iently scaled at 1 Hz/µF (0.05 µF for a 20 Hz corner). A maxi­mally flat response occurs when the resistor is lowered to 196 kΩ
and the scaling is then 1.145 Hz/µF. The output offset is raised by
approximately 5 mV (equivalent to 250 µV at the input pins).

Rev. C | Page 14 of 16

AD8202

Y

FREQUENCY

40dB/DECADE

20dB/DECADE

ATTENUATION

40LOG (f2/f1)

A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f
THE SAME ATTENUATION –40LOG (f
AT FREQUENCY f

2

f

1

, HAVE

2

2

/f

1

f

2

2/f1

)

2

f

/f

2

1

04981-021

Figure 39. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters

HIGH-LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT

Figure 40 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.

INDUCTIVE
LOAD

BATTER

CLAMP

DIODE

14V

NC = NO CONNECT COMMON

4-TERM

SHUNT

POWER
DEVICE

Figure 40. High-Line Current Sensor Interface;

Gain = ×40, Single-Pole, Low-Pass Filter

A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on
the inductance of the load and the control frequency. The
common-mode voltage, conversely, extends from roughly 1 V
above ground for the on condition to about 1.5 V above the
battery voltage in the off condition. The conduction of the
clamping diode regulates the common-mode potential applied
to the device. For example, a battery spike of 20 V may result in
an applied common-mode potential of 21.5 V to the input of
the devices.

To produce a full-scale output of 4 V, a gain ×40 is used, adjust­able by ±5% to absorb the tolerance in the shunt. Sufficient
headroom allows 10% overrange (to 4.4 V). The roughly trian­gular voltage across the sense resistor is averaged by a 1-pole,

NC

+INA1+V

AD8202

GND

–IN

5V

OUT

S

191kΩ

20kΩ

A2

V

OS/IB

NULL

C

5% CALIBRATION RANGE
f

(Hz) = 0.796Hz/C(µF)

C

(0.22µF FOR f

= 3.6Hz)

C

OUT
4V/AMP

low-pass filter, set here with a corner frequency of 3.6 Hz,
which provides about 30 dB of attenuation at 100 Hz. A higher
rate of attenuation can be obtained using a 2-pole filter with

= 20 Hz, as shown in Figure 41. Although this circuit uses

f

C

two separate capacitors, the total capacitance is less than half
that needed for the 1-pole filter.

INDUCTIVE

CLAMP

DIODE

BATTERY

14V

NC = NO CONNECT COMMON

4-TERM

SHUNT

POWER
DEVICE

LOAD

Figure 41. 2-Pole Low-Pass Filter

+IN

–IN

5V

+V

NC

AD8202

GND

A1

OUT

S

A2

127kΩ

C

fC(Hz) = 1/C(µF)
(0.05µF FOR f

C

432kΩ

50kΩ

= 20Hz)

C

OUTPUT

04981-023

DRIVING CHARGE REDISTRIBUTION ADCS

When driving CMOS ADCs such as those embedded in popu­lar microcontrollers, the charge injection (∆Q) can cause a
significant deflection in the output voltage of the AD8202.
Though generally of short duration, this deflection may persist
until after the sample period of the ADC expires due to the
relatively high open-loop output impedance (typ 21 kΩ) of the
AD8202. Including an R-C network in the output can signifi­cantly reduce the effect. The capacitor helps to absorb the tran­sient charge, effectively lowering the high frequency output
impedance of the AD8202. For these applications, the output

− C

04981-022

signal should be taken from the midpoint of the R
combination, as shown in Figure 42.

LAG

Because the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8202 appears to be low. The
transient response, therefore, has a time constant governed by the

× R

product of the two LAG components, C

LAG

. For the values

LAG

shown in Figure 42, this time constant is programmed at approxi­mately 10 µs. Therefore, if samples are taken at several tenths of
microseconds or more, there is negligible charge stack-up.

5V

4 6

+IN

–IN

Figure 42. Recommended Circuit for Driving CMOS A/D

AD8202

A2

10kΩ

10kΩ

R

LAG

1kΩ

5

2

C

0.01µF

LAG

MICROPROCESSOR

A/D

LAG

04981-024

Rev. C | Page 15 of 16

AD8202

OUTLINE DIMENSIONS

4.00 (0.1574)

3.80 (0.1497)

5.00 (0.1968)

4.80 (0.1890)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 43. 8-Lead Standard Small Outline Package [SOIC_N], Narrow Body (R-8),

Dimensions shown in millimeters and (inches)

3.00

BSC

8

5

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

BSC

4

SEATING
PLANE

4.90

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

Figure 44. 8-Lead Mini Small Outline Package [MSOP], (RM-8),

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Package Package Description Package Outline Branding

AD8202YR −40°C to +125°C 8 Lead Standard Small Outline Package (SOIC_N) R-8
AD8202YR-REEL −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8202YR-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8202YRZ
AD8202YRZ-RL1 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8202YRZ-R71 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8202YRMZ1 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 JWY
AD8202YRMZ-RL1 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 JWY
AD8202YRMZ-R71 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 JWY
AD8202YCSURF Die

1

Z = Pb-free part.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04981–0–2/05(C)

1

−40°C to +125°C 8 Lead Standard Small Outline Package (SOIC_N) R-8

Rev. C | Page 16 of 16