ANALOG DEVICES AD8200 Service Manual

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High Common-Mode Voltage, Single-Supply

OUTPUT

INDUCTIVE LOAD

4 TERM

SHUNT

CLAMP

DIODE

BATTERY

14V

POWER DEVICE

COMMON

NC = NO CONNECT

GND

–IN

+IN

OUT

AD8200

www.BDTIC.com/ADI

Difference Amplifier

AD8200

FEATURES High Common-Mode Voltage Range –2 V to +24 V at a

5 V Supply Voltage

Operating Temperature Range

Die: –40C to +150C Supply Voltage Range: 4.7 V to 12 V Low-Pass Filter (One Pole or Two Pole)

EXCELLENT AC AND DC PERFORMANCE

1 mV Voltage Offset 10 ppm/C Typ Gain Drift

80 dB CMRR Min DC to 10 kHz

PLATFORMS Transmission Control Diesel Injection Control Engine Management Adaptive Suspension Control Vehicle Dynamics Control

GENERAL DESCRIPTION

The AD8200 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. The input CMV range extends from –2 V to +24 V at a typical supply voltage of 5 V.

The AD8200 is offered in die and packaged form. Both package options are specified over wide temperature ranges, making the AD8200 well suited for use in many automotive platforms. The SOIC package is specified over a temperature range of –40°C to +125°C. The die is specified from –40°C to +150°C.

FUNCTIONAL BLOCK DIAGRAM

SOIC (R) Package

Die Form

AD8200

G =2

+IN

–IN

10k

GND

OUT

+IN

–IN

NC A1

100k

G =10

+IN

–IN

200k200k

NC = NO CONNECT

Automotive platforms demand precision components for better system control. The AD8200 provides excellent ac and dc performance that keeps errors to a minimum in the user’s system. Typical offset and gain drift in the SOIC package are 6 µV/°C and 10 ppm/°C, respectively. The device also delivers a minimum CMRR of 80 dB from dc to 10 kHz.

The AD8200 features an externally accessible 100 kΩ resistor at the output of the preamp A1, which can be used for low-pass filter applications and for establishing gains other than 20.

INDUCTIVE

CLAMP

DIODE

BATTERY

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

14V

Figure 1. High Line Current Sensor

POWER DEVICE

COMMON

4 TERM

SHUNT

LOAD

+IN

–IN

AD8200

GND

NC = NO CONNECT

OUTPUT

OUT

Figure 2. Low Line Current Sensor

AD8200–SPECIFICATIONS

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SINGLE SUPPLY

Parameter Condition Min Typ Max Min Typ Max Unit

SYSTEM GAIN

Initial 20 20 V/V Error V vs. Temperature 10 20 25 30 ppm/°C

VOLTAGE OFFSET

Input Offset (RTI) VCM = 0.15 V; 25°C–1 +1–1 +1mV

INPUT

Input Impedance

Differential 320 400 480 320 400 480 kΩ Common-Mode 160 200 240 160 200 240 kΩ

CMV Continuous –2 +24 –2 +24 V

Common-Mode Rejection

PREAMPLIFIER

Gain 10 10 V/V Gain Error –1 +1 –1 +1 % Output Voltage Range 0.02 4.8 0.02 4.8 V Output Resistance 97 100 103 97 100 103 kΩ

OUTPUT BUFFER

Gain 2 2 V/V Gain Error –1 +1 –1 +1 % Output Voltage Range 0.02 4.8 0.02 4.8 V Output Resistance 2 2 Ω

DYNAMIC RESPONSE

3 dB Bandwidth 30 50 30 50 kHz Slew Rate 0.22 0.22 V/µs

NOISE

0.1 Hz to 10 Hz 10 10 µV p-p Spectral Density, 1 kHz, RTI 300 300 nV/√Hz

POWER SUPPLY

Operating Range 4.7 12 4.7 12 V Quiescent Current vs. V

Temperature

PSRR VS = 4.7 V to 12 V 75 80 75 80 dB

TEMPERATURE RANGE

For Specified Performance –40 +125 –40 +150 °C

NOTES

Source imbalance < 2 Ω.

The AD8200 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 k Ω resistor, even the small amounts of pinto-pin capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-topin coupling may be neglected in all applications using filter capacitors at Node 3.

Specifications subject to change without notice.

(TA = 25C, VS = 5 V, VCM = 0 V, RL = 10 k.)

AD8200 SOIC AD8200 DIE

≥ 0.1 V dc –1 +1 –1 +1 %

= 0.15 V; 125°C (SOIC)

+150°C (DIE) –2.5 +2.5 –3.5 +3.5 mV VCM = 0.15 V; –40°C–2 +2–3 +3mV

VCM = 10 V f = 1 kHz 80 80 dB f = 10 kHz

= 0.1 V dc 0.25 1 0.25 1 mA

80 80 dB

REV. B–2–

AD8200

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 V

Transient Input Voltage (300 ms) . . . . . . . . . . . . . . . . . . 44 V

Continuous Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 35 V

Reversed Supply Voltage Protection . . . . . . . . . . . . . . . . 0.3 V

Operating Temperature

DIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +150°C

SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

*Stresses beyond those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8200YR –40°C to +125°C SOIC R-8 AD8200YR-Reel –40°C to +125°C SOIC R-8 AD8200YR-Reel-7 –40°C to +125°C SOIC R-8 AD8200YCHIPS –40°C to +150°CDIE Form AD8200YCSURF –40°C to +150°CDIE Form

PIN CONFIGURATION

–IN

GND

TOP VIEW

(Not to Scale)

NC = NO CONNECT

AD8200

+IN

OUT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

METALLIZATION PHOTOGRAPH

OUT5

+IN

–IN 1

REV. B

GND

–3–

A24

AD8200–Typical Performance Characteristics

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(TA = 25C, VS = 5 V, VCM = 0 V, RL = 10 k, unless otherwise noted.)

POSITIVE COMMON-MODE RANGE – V

253

SUPPLY VOLTAGE – V

–V

TPC 1. Input Common-Mode Range vs. Supply

–2

–4

–6

–8

–10

NEGATIVE COMMON-MODE RANGE – V

–12

GAIN – dB

–5

–10

–15

–20

10k 100k 1M

FREQUENCY – Hz

TPC 4. Gain vs. Frequency

–5

–10

–15

–20

–25

OUTPUT VOLTAGE – mV

–30

–35

RL = 10k TO GND

RL =

SUPPLY VOLTAGE – V

TPC 2. Output Voltage – VS vs. Supply

OUTPUT VOLTAGE – V

100 1k 10k LOAD RESISTANCE – 

TPC 3. Output Voltage Swing vs. Load Resistance

100

CMRR – dB

100 100k

1k 10k 1M

FREQUENCY – Hz

TPC 5. Common-Mode Rejection Ratio vs. Frequency

100

PSRR – dB

100 10k1k 100k

FREQUENCY – Hz

TPC 6. Power Supply Rejection Ratio vs. Frequency

REV. B–4–

AD8200

www.BDTIC.com/ADI

TEK RUN: 2.5MS/s HI RES

, RL = 10k

OUT

CH1 500mV 50mV M 20s CH1 1.5VCH2

TPC 7. Pulse Response

THEORY OF OPERATION

The AD8200 consists of a preamp and buffer arranged as shown in Figure 3. Like-named resistors have equal values.

The preamp incorporates a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of R

, RC, and RG, attenuate input signals applied to Pins 1 and 8.

Note that when equal amplitude signals are asserted at inputs 1 and 8, and the output of A1 is equal to the common potential (i.e., zero), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1, and thus its output, will be zero.

Any common-mode voltage applied to both inputs will keep the bridge balanced and the A1 output at zero. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state.

However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive R

, by way of RG, to adjust the voltage at its inverting

input until it matches the voltage at its noninverting input.

By attenuating voltages at Pins 1 and 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply, or fall below common (ground.) The input network also attenuates normal (differential) mode voltages. R

and RG form an attenuator that scales A1 feedback,

forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at 10.

Because the differential input signal is attenuated, and then amplified to yield an overall gain of 10, the amplifier A1 operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pins 1 and 8.

+IN

–IN

100k

(TRIMMED)

AD8200

TEK RUN: 2.5MS/s AVERAGE

, RL = 10k

OUT

MAGNIFIED V

CH1 1V CH 2 10mV M 20s CH1 1.36V CH3 100mV

OUT

TPC 8. Settling Time

To minimize these errors while extending the common-mode range, a dedicated feedback loop is employed to reduce the range of common-mode voltage applied to A1, for a given overall range at the inputs. By offsetting the range of voltage applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. Amplifier A3 detects the common-mode signal applied to A1 and adjusts the voltage on the matched R

resistors to reduce the

common-mode voltage range at the A1 inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input.

The output of the dynamic bridge taken from A1 is connected to Pin 3 by way of a 100 kΩ series resistor, provided for low- pass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy.

The output of the preamp drives a gain-of-two buffer-amplifier A2, implemented with carefully matched feedback resistors R

The two-stage system architecture of the AD8200 enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal resulting from filtering can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A2 is approximately 100 kΩ, to minimize the effects of A2’s input bias current. However, this current is quite small and errors resulting from applications that mismatch the resistance are correspondingly small.

APPLICATIONS

The AD8200 difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. The input resistance is nominally 200 kΩ, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground.

The open collector output stage will source current to within 20 mV of ground.

COM

Figure 3. Simplified Schematic

REV. B

–5–

AD8200

www.BDTIC.com/ADI

CURRENT SENSING High Line, High Current Sensing

Basic automotive applications making use of the large commonmode range are shown in Figures 1 and 2. The capability of the device to operate as an amplifier in primary battery supply circuits is shown in Figure 1; Figure 2 illustrates the ability of the device to withstand voltages below system ground.

Low Current Sensing

The AD8200 can also be used in low current sensing applications, such as the 4–20 mA current loop shown in Figure 4. In such applications, the relatively large shunt resistor can degrade the common-mode rejection. Adding a resistor of equal value in the low impedance side of the input corrects for this error.

10

+IN

10

–IN

AD8200

GND

NC = NO CONNECT

OUTPUT

OUT

Figure 4. 4–20 mA Current Loop Receiver

GAIN ADJUSTMENT

The default gain of the preamplifier and buffer are ⫻10 and ⫻2, respectively, resulting in a composite gain of ⫻20. With the addition of external resistor(s) or trimmer(s), the gain may be lowered, raised, or finely calibrated.

Gains Less than 20

Since the preamplifier has an output resistance of 100 kΩ, an external resistor connected from Pins 3 and 4 to GND will decrease the gain by a factor R

DIFF

/(100 kΩ + R

EXT

AD8200

100k

) (see Figure 5).

EXT

NC+IN

OUT+V

10k10k

OUT

20R

EXT

= 100k

EXT

+ 100k

GAIN

20 – GAIN

GAIN =

EXT

A2A1GND–IN

EXT

Gains Greater than 20

Connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in Figure 6, will increase the

/(R

gain. The gain is now multiplied by the factor R 100 kΩ); for example, it is doubled for R

EXT

= 200 kΩ. Overall

EXT

–

gains as high as 50 are achievable in this way. Note that the accuracy of the gain becomes critically dependent on resistor value at high gains. Also, the effective input offset voltage at Pins 1 and 8 (about six times the actual offset of A1) limits the part’s use in very high gain, dc-coupled applications.

NC+IN

DIFF

NC = NO CONNECT

AD8200

100k

GND

OUT

10k10k

EXT

A2A1–IN

GAIN =

EXT

OUT

EXT

= 100k

20R

EXT

– 100k

GAIN – 20

GAIN

Figure 6. Adjusting for Gains Greater than 20

GAIN TRIM

Figure 7 shows a method for incremental gain trimming using a trimpot and external resistor R

EXT

The following approximation is useful for small gain ranges

∆ΩGMR

≈÷

10 %

()

Thus, the adjustment range would be ±2% for R ±10% for R

= 1 MΩ, and so on.

EXT

DIFF

NC = NO CONNECT

+IN

–IN

AD8200

GND

EXT

OUT

= 5 MΩ;

EXT

OUT

EXT

GAIN TRIM 20k MIN

Figure 7. Incremental Gain Trim

NC = NO CONNECT

Figure 5. Adjusting for Gains Less than 20

The overall bandwidth is unaffected by changes in gain using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. In many cases this can be ignored, but if desired, can be nulled by inserting a resistor equal to 100 kΩ minus the parallel sum of

and 100 kΩ, in series with Pin 4. For example, with R

EXT

= 100 kΩ (yielding a composite gain of ⫻10), the optional offset nulling resistor is 50 kΩ (see Figure 11.)

REV. B–6–

AD8200

40LOG (f2/f1)

ATTENUATION

FREQUENCY

A 1-POLE FILTER, CORNER f1, AND A 2-POLE FILTER, CORNER f

, HAVE

THE SAME ATTENUATION –40LOG (f

2/f1

)

AT FREQUENCY f

20dB/DECADE

40dB/DECADE

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Internal Signal Overload Considerations

When configuring gain for values other than 20, the maximum input voltage with respect to the supply voltage and ground must be considered, since either the preamplifier or the output buffer will reach its full-scale output (approximately V

– 0.2 V)

with large differential input voltages. The input of the AD8200 is limited to (V

– 0.2) ÷ 10, for overall gains ≤10, since the

preamplifier, with its fixed gain of ×10, reaches its full-scale output before the output buffer. For gains greater than 10, the swing at the buffer output reaches its full scale first and limits the AD8200 input to (V

– 0.2) ÷ G, where G is the overall gain.

LOW-PASS FILTERING

In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. Signals having large spikes may have PARs of 10 or more.

When implementing a filter, the PAR should be considered so the output of the AD8200 preamplifier (A1) does not clip before A2, since this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should be made to clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a PAR of 5 is expected, the gain of A2 should be increased to 5.

Low-pass filters can be implemented in several ways using the features provided by the AD8200. In the simplest case, a singlepole filter (20 dB/decade) is formed when the output of A1 is connected to the input of A2 via the internal 100 kΩ resistor by strapping Pins 3 and 4 and a capacitor added from this node to ground, as shown in Figure 8. If a resistor is added across the capacitor to lower the gain, the corner frequency will increase; it should be calculated using the parallel sum of the resistor and 100 kΩ.

DIFF

+IN

–IN

AD8200

GND

OUT

2C10

C IN FARADS

DIFF

NC = NO CONNECT

+IN

–IN

AD8200

GND

OUT

255k



= 1Hz – F

OUT

Figure 9. 2-Pole Low-Pass Filter

A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented using the connections shown in Figure 9. This is a Sallen-Key form based on a ×2 amplifier. It is useful to remember that a 2-pole filter with a corner frequency f

have the same attenuation at the frequency (f

at f

attenuation at that frequency is 40 log (f

and a 1-pole filter with a corner

2/f1

/f1). The

). This is illustrated in Figure 10. Using the standard resistor value shown and equal capacitors (Figure 9), the corner frequency is conveniently scaled at 1 Hz-µF (0.05 µF for a 20 Hz corner). A maximally flat response occurs when the resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz-µF. The output offset is raised by approximately 5 mV (equivalent to 250 ␮V at the input pins).

Figure 10. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters

NC = NO CONNECT

Figure 8. A Single-Pole, Low-Pass Filter Using the

Ω

Internal 100 k

If the gain is raised using a resistor, as shown in Figure 8, the

Resistor

corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of 200 kΩ (for which the gain would be doubled), the corner frequency is now 0.796 Hz-µF, (0.039 µF for a 20 Hz corner frequency.)

REV. B

–7–

AD8200

www.BDTIC.com/ADI

HIGH-LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT

Figure 11 is another refinement of Figure 1, including gain adjustment and low-pass filtering.

BATTERY

CLAMP

DIODE

14V

NC = NO CONNECT

4 TERM

SHUNT

POWER DEVICE

INDUCTIVE LOAD

+IN

COMMON

–IN

OUT

AD8200

GND

NULL

5% CALIBRATION RANGE

= 0.796Hz–F

(0.22F FOR f = 3.6 Hz)

OS/IB

OUTPUT 4V/AMP

191k

20k

Figure 11. High-Line Current Sensor Interface; Gain = ×40, Single-Pole, Low-Pass Filter

A power device that is either ON or OFF controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value will be higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, on the other hand, extends from roughly 1 V above ground, when the switch is ON, to about 1.5 V above the battery voltage, when the device is OFF, and the clamp diode conducts. If the maximum battery voltage spikes up to 20 V, the common-mode voltage at the input can be as high as 21.5 V.

To produce a full-scale output of 4 V, a gain ×40 is used, adjustable by ±5% to absorb the tolerance in the shunt. There is sufficient headroom to allow 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged by a 1-pole, low-pass filter, here set with a corner frequency =

3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a 2-pole filter having f

= 20 Hz, as shown in Figure 12. Although this circuit

uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter.

DRIVING CHARGE REDISTRIBUTION A/D CONVERTERS

When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection (⌬Q) can cause a significant deflection in the output voltage of the AD8200. Though generally of short duration, this deflection may persist until after the sample period of the ADC has expired, due to the relatively high open-loop output impedance of the AD8200. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the AD8200. For these applications, the output signal should be

– C

taken from the midpoint of the R

LAG

combination as

LAG

shown in Figure 13.

Since the perturbations from the analog-to-digital converter are small, the output impedance of the AD8200 will appear to be low. The transient response will, therefore, have a time constant governed by the product of the two LAG components, C

. For the values shown in Figure 13, this time constant is

LAG

programmed at approximately 10 µs. Therefore, if samples are taken at several tens of microseconds or more, there will be negligible charge “stack-up.”

+IN

–IN

AD8200

10k

1k

LAG

0.01F

MICROPROCESSOR

A/D

Figure 13. Recommended Circuit for Driving CMOS A/D

BATTERY

CLAMP

DIODE

14V

NC = NO CONNECT

4 TERM

SHUNT

POWER DEVICE

INDUCTIVE LOAD

COMMON

+IN

–IN

AD8200

GND

OUT

F (0.05F FOR f

127k

= 1Hz–F

OUTPUT

432k

50k

= 20Hz)

Figure 12. Illustration of 2-Pole Low-Pass Filtering

REV. B–8–

OUTLINE DIMENSIONS

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8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

6.20 (0.2440)

5.80 (0.2284)

AD8200

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ 0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

REV. B

–9–

AD8200

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Revision History

Location Page

11/03—Data Sheet Changed from REV. A to REV. B.

Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6/02—Data Sheet Changed from REV. 0 to REV. A.

Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

REV. B–10–

–11–

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C02054–0–11/03(B)

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–12–

ANALOG DEVICES AD8200 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

EXCELLENT AC AND DC PERFORMANCE

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

PIN CONFIGURATION

METALLIZATION PHOTOGRAPH

THEORY OF OPERATION

APPLICATIONS

Low Current Sensing

GAIN ADJUSTMENT

GAIN TRIM

LOW-PASS FILTERING

HIGH-LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT

DRIVING CHARGE REDISTRIBUTION A/D CONVERTERS

OUTLINE DIMENSIONS

Revision History